Analog IC Design
BITS Pilani
Pilani Campus
Anu Gupta
Differential Amplifier
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani
Pilani Campus
Differential Amplifier
How ?
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Differential input no cap. reqd.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Comparison with csa same power
dissipation
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
To obtain gain = CSA without
incres. power
We can keep gm same for same power consumption by keeping vov constant. This will require w/l to be increased (changed).
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Differential amplifier extra benefit
Extra node available
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CSA-CSA coupled at source
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Pmos differential pair
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Diff amplifier operation modes
Common mode Difference mode
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Difference mode operation
Adm, Output swing, CMRR,Ri, Rout
Difference mode gain
Input applied differentially
Adm = -gm Rd
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Output signal swing--doubles
vo1
2.8v 1.2v 3v
Vcm=1.6v
0.4v
vo2
vcm 1.2v
Vo1-vo2
2.4 v
Assume all overdrive 0.2v
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis using Half circuit
Vin/2
Vin/2
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Difference mode gain
Input applied is single ended. Why?
Convenience. Generating differential o/p is not always possible
Half circuit concept cannot be applied
Ac ground Vin Not ac gnd.
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Can we still get differential gain?
Vin=
Vin
vin./2
vin/2
= gm/2 Rd
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
vin
vin/2
vin
Gm= gm/2
= - gm Rd
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BITS Pilani
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Differential amp. with Current mirror load
Difference mode--single ended output cd-cg cascade
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Difference mode--single ended output
Difference mode--single ended output
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Difference mode--single ended output
Assume input splits equally.( Will they?)
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Diff. amp with current mirror load
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Ac behavior of P node
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Ac behavior of P node
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Noise behavior
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
What have we lost?
Double Output signal swing Full Noise cancellation due to asymmetry Symmetry of the circuit even if we have matched devices. So two currents through M1 and M2 will not be exactly same As source is not at ac ground and ac currents not exactly equal, an ac current flows through Iss. Hence to again make that current small, make Rss very large
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Diff amp with current mirror load
symmetry of two arms is lost
VDD i
gm4vF
-i
i = gm vin/2
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Gain Adm
i = gm vin/2
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Adm
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Acm
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Now, Rss plays a crucial role
If Iss is implemented as diode connected transistor------ Vp vin/2---two inputs may not be equal. why?
VDD i
gm4vF
-i
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Example----Vp vin/2, Rss small
VDD i -gm4vF
i vin
-i
Vp / vin 1/5; for all gm to be equal
2/gm2 1/gm1 Rss= 1/gm5
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Solution-to the problem
We still desire vin to split equally. what is the solution? Make Rss very large such that through it virtually zero ac current So here we need a very large Rss current mirror.
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High Rss current mirror
Casode CM Wilson CM
2 Vgs-Vt
v/i = gm ro2 +2ro
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wilson
i= gm (-iro-i/gm) + [v-iro] / ro v/i = gm ro2 +3ro
v -iro i
-gm ro i/gm =
= i/gm
2 Vgs-Vt
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Modified wilson (to negate mismatch
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What have we lost?
Symmetry of the circuit even if we have matched devices. So two currents through M1 and M2 will not be exactly same As source is not at ac ground and ac currents not exactly equal, an ac current flows through Iss. Hence to again make that current small, make Rss very large Careful design is required to get differential operation here
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DESIGN TIPS
DESIGN TIPS---to get differential operation with asymmetric diff. amp ---Rss very large ---Take L large to get ro very large Both will help in splitting vin nearly equally between two differential transistors, to bring p node to nearly ac ground
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Rss was unimportant in fully differential circuit onlywithconditionofperfectsymmetry
As node p at ac ground
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Small signal analysis- node p at ac ground
VDD i
-gm4vF = gm4 [gm1/gm3] vin/2
i -gm4vF
As gm3=gm4
-[gm1/gm3] vin/2
-gm4 vF = gm1 vin/2= i
Gm 1/gm2 i
vin 1/gm1 Rss= 1/gm5 i
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2i= gm vin
vout Rout= ro4 || ro2
Gm = gm;
Rss very large
i2 = -gm vin/2 + (vp-vx) ro Vx= i2/gm3 i4= i2 Iout = -gm vin/2 +[ 0-vp] ro
V2
node p not at ac ground
+i2(=i4)
i2 / gm3
i4
V1 i2 p
Gm= iout/vin = gm (
1 (1+ 1/gm3ro)
Gm gm Same expression is obtained when p is assumed at ground
Must be large
V1= vin/2+vp V2= -vin/2+vp
Rout= VX/ IX
gm4 (1/gm3) Vx 2ro2+ 1/gm3
Vx (1/gm3) 2ro2+ 1/gm3
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Rout--INTUITIVELY
gm4 (1/gm3) Vx 2ro2+ 1/gm3
Vx (1/gm3) 2ro2+ 1/gm3
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Gm, Rout
Thus node p is assumed at AC ground for all calculations
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CMRR
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Common mode rejection ratio CMRR
CMRR= |Adm/ Acm|; figure of merit
Ability to reject common signal For diff output---- Acm=0; ideal case CMRR
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CMRR---Diff. Topology but single ended output
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CMRR---Diff. Topology but single ended output
= gmRd/2
CMRR = gm x
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Current mirror load
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Common mode gain
CMRR
Rss should be large
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Large signal analysis Transfer Characteristics
Large signal analysis
Large signal analysis-
how does a variable change (voltage/current) when a another variable (voltage/current) is swept?
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Characteristics
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
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Large signal analysis---Transfer
Characteristics
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Vid (max)range of differential mode operation
2 Vov
Transistor remain in saturation
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Range Of Vin For Diff. Mode Operation
Diff. Mode Operation, Vov (VGS1 VT ) I SS n C OX W L
M 1 trans. Conducting Iss (VGS1 VT )
2 I SS n C OX W L
2VOV
VIN 1 VGS1 VP VGS 2 VIN 2 VP VT ; For M 2 Cut off [VIN 1 VIN 2 ] (VGS1 VP ) (VT VP ) VGS1 VT [VIN 1 VIN 2 ] 2V0V
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani
Pilani Campus
Differential Power Supply Single Power Supply
Dual rail circuits Vdd
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Single rail circuits
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Single Ended Input, Single Ended Output
ICMR, OCMR
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ICMR
OCMR DC voltage/s
possible at output node
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OCMR (dc) , Output signal swing (ac)
They may be same, may not be same
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
OCMR (dc) , Output signal swing (ac)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
ICMR / OCMR calculations- examples
Input common mode range[(Vdd - Iss R) + Vt] to [Vgs1+Vov3] Output common mode range Vdd - Iss R no range here. fixed value
For single output node Output swing [(Vout1-Vov1+ Vgs1 ] to [Vov1+Vov3]
Vout1+Vt
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Example 2
Input common mode range[(Vdd Vsg3) + Vt] to [Vgs1 + Vov5] Output common mode range [(Vdd Vsg3) ] no range here Output swing [(Vdd - |Vtp3| ] to
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: Vsg3 Vtp3
Else M3 goes to cutoff
[Vov1+Vov3]
ex3
Single node Output swing [(Vdd |Vtp3| ] to [Vov1+Vov3]
Input common mode range[(Vdd Vsg3) + Vt] to [Vgs1 + Vov5] : Vsg3 Vtp3 Output common mode range [(Vdd Vsg3) ] no range here
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ex4
Output swing [(Vdd - |Vtp3|+ I R ] to [Vov1+Vov3 + I R ] Input common mode range[(Vdd Vsg3 + I R ) + Vt] to
[Vgs1 + Vov5] : Vsg3 Vtp3
Output common mode range [(Vdd Vsg3 + I R ] no range here
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ex5
Input common mode range[(Vdd Vov3) + Vtn1] to [Vgs1 + Vov5] Output common mode range [(Vdd Vov3 to Vov5 + Vov1 ]
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range here
PMOS DIFF. AMP
Output signal swing 2 [(Vdd Vov3- Vov2 to Vov3 ]
vout
ICMR Input common mode range[Vdd Vov3 - Vsg2] to [Vov3 + Vov1- Vsg2] Output common mode range [(Vdd Vov3- Vov2 to Vov3 ]
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;Vov2=|Vsg2|- |Vtp2|
range here
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Common mode analysis
ACM, Transfer charac.
Common mode differential gain= 0 for perfect symmetry
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Common mode single ended gain
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Asymmetry
CMRR in diff. circuit is not infinite Input offset voltage
Rss was unimportant in fully differential circuit
only withcondition of perfect symmetry
As node p at ac ground
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Real caseasymmetry in diff pair
Rd asymmetery Diff. pair asymmetry
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Rd asymmetry Acm, cmrr changes
Gm mismatch-Acm, CMRR changes
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ID1=
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Input offset voltage
Diff output (Vo) exists even with both inputs grounded----output dc offset Vos= Vo/Adm
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Significance of offset voltage
Specification in comparator design Input less than Vos will not produce any output. Or Voltages can not be compared
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Rd mismatch
Gm mismatchw/l, Vt mismatch
Multistage amplifier
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End
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Frequency response of amplifiers
Case-1 Complementary input applied
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Transit Frequency
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MOS capacitances
Cgs Cgd Cgb Csb Cdb
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MOS Transit Frequency wT
wT = (gm-sCgd) /[s (Cgs+Cgd)]
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Transit frequency
I
Wt= Wz Wz Wt
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MOS unity gain frequency wT
Limits for MOSFETs: Metric C.S short-circuit current gain unit pt: wT = (gm-SCgd)/[s(Cgs+Cgd)] wT is approximately = gm/Cgs = 3 un(VGS -VT)/2L2 Where gm = (W/L) unCox(VGS -VT) and Cgs = (2/3)WLCox so wT 3 n(VGS -VT)/2L2 Design lessons bias at large ID minimize L (w in as L2) , (= 1/L)increases, ROUT dec. use n-channel over p-channel Bits, pilani , NOISE increases
UNITY GAIN FREQUENCY
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BJT circuits
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