Two-Cell, Three-Cell, and Four-Cell Lithium-Ion or Lithium-Polymer Battery Protection Afe

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PW RTH

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LDO, Therm Output Drive & UVLO
Power Management
LDO, TOUT, and Power Mode control
I
2
C
Capacity Prediction <1% Error
SMBus
Pack +
Pack -
Discharge / Charge /
Precharge FETs
Cell and Pack
Voltage
Measurement
Precharge
FET Drive
2-Tier Overcurrent Protection
32-kHz Clock
Generator
bq2084
768 Bytes of
User Flash
Fuse
1
st
Level OV and
UV Protection
Pack Undervoltage
Power Mode
Control
Precharge Control
Delay Counters
Cell Balancing Algorithm and Control
Cell Balancing
Drive
System Interface
System Watchdog
Voltage Level Translator
System Interface
32 kHz
Power Mode Control
Fail-Safe Protection
T1
1
st
Level OC
Protection
Temperature Measurement
<1% Error
T
INT
Supply V oltage
bq29312A
PCH FET Drive
RAM Registers SBS v1.1 Data
bq29312 RAM/Comms Validation
2

n
d

L
e
v
e
l

O
v
e
r
v
o
l
t
a
g
e

P
r
o
t
e
c
t
i
o
n
XAlert
Sleep
Sense Resistor
(10 - 30 m W)
PF Input















































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t
su(STA)
SCLK
SDATA
SCLK
SDATA
SCLK
SDATA
t
w(H)
t
w(L)
t
f
t
r
t
r
t
f
Start
Condition
SDA
Input
SDA
Change
Stop
Condition
t
h(STA)
t
h(DAT)
t
su(DAT)
t
h(ch)
Start Condition
t
v
1 2 3 7 8 9
MSB ACK
Stop Condition
t
su(STOP)
1 2 3 7 8 9
MSB ACK
t
su(BUF)

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1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
OD
PMS
PACK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
GND
SDATA
SCLK
PW PACKAGE
(TOP VIEW)
B
A
T
D
S
G
V
C
1
VC3
VC4
SR2
SR1
VC5
G
N
D
XALERT
REG
TOUT
ZVCHG
P
A
C
K
O
D
W
D
I
C
E
L
L
S
D
A
T
A
G
N
D
VC2
S
C
L
K
SLEEP
CHG
P
M
S
RTH PACKAGE
(TOP VIEW)











































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GND
C
E
L
L
1
.
.
4
SR1
SR2
Overload
Comparator
Short-Circuit
SHORT-CIRCUIT
DELAY
Open-
Drain
Output
Watchdog
Timer
OD
Cell Voltage
Translation
Power
Mode
Circuit
Drive
Control
VCELL
R
SNS
R
CELL
C
CELL
TOUT
R
THERM
C
THERM
THERMISTOR
Cell
Selection
Switches
3.3V LDO
POR
SHIP_ON
SLEEP_ON
BAT PACK REG
C
(REG)
FET
Logic
Gate Driver CHG_ON
DSG_ON
ZVCHG_ON
DSG CHG ZVCHG
PACK- PACK+
R
(ZVCHG)
PMS
GG VDD
VC1
VC2
VC5
CELL 3
CELL 4
VC3
VC4 CELL 1
CELL 2
GG TS
INPUT
GGANALOG
INPUT
SLEEP
REG
WDI
SLEEP
CONTROL
32-kHz INPUT
FROM GG
GG INTERFACE
SDATA
ALERT TO GG
OPEN-DRAIN
OUTPUT
GG INTERFACE
SCLK
SDATA
SCLK
XALERT
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
Status
Output Ctl
State Ctl
Function Ctl
CELL_SEL
OCDV
OCDT
SCC
SCD
Registers
Comparator
OVERCURRENT
REG
200 k
200 k
0.2-A
Current Source
_
+
-


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No Power
POWER SUPPLY TO PACK
FETS: OFF(*2)
REG: start Working
I
2
C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
INITIALIZE
FETS: OFF
REG: ON
I
2
C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : ON
THERMISTOR PWER CTRL : OFF
HOST FAULT MODE
REG >2.4 V REG < 2.3 V
FETS: ON *2
REG: ON
I
2
C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
NORMAL MODE
RESET WDTF LATCH
HOST CLOCK STOP
STATE CTL REGISTER b1 = 1
AND NO SUPPLY POWER TO PACK
FETS: OFF
REG: ON
I
2
C: ON
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
SLEEP MODE
SLEEP MODE EXIT BY
STATE CTL REGISTER b0 = 0
AND SLEEP PIN = GND
*1
FETS: OFF
REG: OFF
I
2
C: OFF
CURRENT FAULT : OFF
CELL MONITOR : OFF
WATCHDOG : OFF
THERMISTOR PWER CTRL : OFF
SHIP MODE
SHIP MODE SET BY STATE CTL REGISTER
b1 = 1 AND NO SUPPLY POWER TO PACK
FETS: OFF
REG: ON
I
2
C: ON
CURRENT FAULT : ON
CELL MONITOR : ON
WATCHDOG : ON
THERMISTOR PWER CTRL : ON
CURRENT DETECT MODE
STATE CTL REGISTER b0 = 1
or SLEEP PIN = REG or OPEN
*1
RESET CURRENT LATCH
IFAULT
SHIP MODE SET BY
STATE CTL REGISTER
b1 = 1 AND NO SUPPLY
POWER TO PACK
Interrupt Request When
Enrering These States
*1: Interrupt Request is Granted When Only External Sleep Pin Changes
*2: When PMS connect to Pack, Default State of CHG FET is ON.
SHIP MODE EXIT BY POWER
SUPPLY TO PACK


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I
2
C
OUTPUT CTRL (b3)
XZVCHG
OUTPUT CTRL (b2-b1)
DSG, CHG
OUTPUT CTRL (b0)
LTCLR
STATUS (b0)
SCDSG
XALERT Pin
LTCLR
Write = 1
LTCLR
Write = 0
Read STATUS
Register
Access Enable Access Enable
Access Enable
Short Current Timeout
in Discharge Direction
Status Disable
Status Disable





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GG Clock Never Starts
REG
GG 32-kHz Output
t
WDTINT
~ 700 mS
CHG, DSG, and
ZVCHG = OFF
EXT FET Control
GG Clock Stop
CHG, DSG, and
ZVCHG = OFF
t
WDWT
About 100 mS
REG
GG 32-kHz Output
Watchdog Sense
EXT FET Control




















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A5
SCLK
SDATA
A6 ACK R/W A0 A4 R5 R6 R7 R0 D7 ACK D6 D5 D0 ACK
0 0 0 0


Slave Address Register Address Data Start Stop
Note: Slave = bq29312
A5
SCLK
SDATA
Stop
A6 ACK R/W A0 R6 R7 R0 A6 ACK A0 R/W ACK D7
0 1 0
D6 D0 NACK


0 0
Slave Address Register Address
Data
Start
Note: Slave = bq29312
Slave Address
Slave Drives
The Data
Master Drives
NACK and Stop
A5
SCLK
SDATA
Stop
A6 ACK R/W A0 R6 R7 R0 A6 ACK A0 R/W ACK D7
0 0 0
D0 NACK A5
Stop Start


Slave Address
Register
Address
Start
Note: Slave = bq29312
Slave Address
Slave Drives
The Data
Master Drives
NACK and Stop




















n o t








n o t












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PACK
ZVCHG
PMS
REG
CHG DSG
BAT
ZVCHG-FET
R
(ZVCHG)
4.7 mF
Battery
DSG-FET CHG-FET Pack+
I
ZVCHG
I
FASTCHG
CV
CC
Charger
DC Input
bq29312A
I
(ZVCHG)
= 0 V Precharge Current
I
(FASTCHG)
= Fast Current
OD
NC


























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VDS
Precharge
Current
ID
VGS
Point A Point B

























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t - Time - mS

V
o
l
t
a
g
e

-

V
0 4 8 12 16
4
20
10
0
8
2
6
14
18
12
16
20
V
(PACK)
3.5

V
V
(ZVCHG)
=
V
(PACK)
- 8 V
V
(ZVCHG)
= V
(PACK)
/ 2
V
(BAT)





























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ON
ZVCHG FET = OFF
OFF
CHG FET = ON
OFF
CHG FET = ON
3.5 V+V
GS(ZVCHGFET)
0 V
3.3 V
0 V
V = VPACK*(1/2)
3.5 V (typ.)
0 V
L (1 V)
L (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A
0 V Charge
Mode
Precharge
Mode
Fast Charge Mode
V
(PACK)
REG
ZVCHG
GHD
DSG
Battery
Voltage
Charge
Current













































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PACK
ZVCHG
PMS
REG
CHG DSG
BAT
4.7 mF
Battery
DSG-FET CHG-FET Pack+
I
(ZVCHG)
I
(FASTCHG)
CV
CC
Charger
DC Input
bq29312A
I
(ZVCHG)
= 0 V Precharge Current
I
(FASTCHG)
= Fast Current
OD
NC

























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0 V Precharge Mode Fast Charge Mode
V
(PACK)
REG
PMS
CHG
DSG
Battery
Voltage
Charge
Current
Host =
Inactive
Host = Active
Set to L as
PMS = PACK
Set to L by Host
Host Sets
DSG-FET to ON
0.7 V
0 V
3.3 V
0 V
0 V
L (1 V)
0 V
L (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A













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PACK
ZVCHG
PMS
REG
CHG DSG
BAT
PCHG-FET
R
(PCHG)
4.7 mF
Battery
DSG-FET CHG-FET Pack+
I
(FASTCHG)
CV
CC
Charger
DC Input
bq29312A
I
(FASTCHG)
= Fast Current
OD
Host
SCLK SDATA
ID
VSD
ID = (V
(PACK)
- V
(BAT)
- V
DS
)/R
(PCHG)












































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Charge CV
0 V
Host : Active
3.3 V
0 V
OFF
CHG FET = OFF
OFF
0 V
DSG FET = ON
L (1 V)
OFF
L (1 V)
0 V
Fast Charge Current
0 V and Precharge Current
0 A
0 V and
Precharge Mode
Fast Charge
Mode
V
(PACK)
REG
CHG
DSG
Battery
Voltage
Charge
Current Charge
Charge Mode
OD
PCHG FET = ON
























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PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
BQ29312APW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
BQ29312APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
BQ29312APWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
BQ29312APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
BQ29312ARTHR ACTIVE VQFN RTH 24 3000 Green (RoHS &
no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR
BQ29312ARTHRG4 ACTIVE VQFN RTH 24 3000 Green (RoHS &
no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
BQ29312APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
BQ29312ARTHR VQFN RTH 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29312APWR TSSOP PW 24 2000 367.0 367.0 38.0
BQ29312ARTHR VQFN RTH 24 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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