Scribd
Upload
54 views

VHDL Codes

The document describes a problem with VHDL code for an 8-bit right shift register. The code is shifting the bits to the left instead of right as intended. The response suggests updating the for loop to shift bits from left to right, and loading the input bit into the highest order bit instead of lowest each clock cycle. Registering the signal holding the bit values is also recommended to maintain the values across clock cycles.

Uploaded by

sklove123
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
54 views

VHDL Codes

The document describes a problem with VHDL code for an 8-bit right shift register. The code is shifting the bits to the left instead of right as intended. The response suggests updating the for loop to shift bits from left to right, and loading the input bit into the highest order bit instead of lowest each clock cycle. Registering the signal holding the bit values is also recommended to maintain the values across clock cycles.

Uploaded by

sklove123
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Hello All.. I have problem in my code. I have created code for 8 bit shift register right..

ie my input is 11001011 then in 1st clock :- output should be :- 01100101 2nd clock :- output should be :- 00110010 3rd clock :- output should be :- 00011001 4th clock :- output should be :- 00001100 5th clock :- output should be :- 00000110 6th clock :- output should be :- 00000001 7th clock :- output should be :- 00000000(Ie at the end of clock 8, it should be 0h) Please correct my code :library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7); end archi; Thanks a lot
#2 July 21st, 2007, 12:27 AM

Avatar
Altera Guru Re: VHDL code for Right Shift register

Join Date: May 2007 Posts: 352 Rep Power: 2295

Your vector is std_logic_vector(7 downto 0) Left to Right, corrrect.

In your loop process, you are looping first with index value as 0. So, tmp(0+1) = tmp (0); will result in tmp(1) getting written with tmp(0). This will take the second from right location and load it with the right most location. I do not believe this will accomplish your desired shift to the right, it will move the right most value into all the locations to the left. You will then be loading the right most location with the SI value. Just draw out step by step what you are trying to do and you will see that you might want to; SO = tmp(0); for i in 1 to 7 loop tmp (i-1) = tmp(i); end loop; tmp(7) = SI; and also, where is tmp declared as a register, not just as a signal? Tmp needs to hold the value, right. I hope this helps.
#3 July 21st, 2007, 06:40 AM

shah_Satish2002
Altera Scholar Re: VHDL code for Right Shift register

Join Date: Jul 2007 Posts: 25 Rep Power: 1620

Hi..Avataar, I am really really thankful to you..


Last edited by shah_Satish2002; July 21st, 2007 at 06:11 PM..

#4 July 23rd, 2007, 11:51 AM

Joe D

Join Date: Jan 2007 Posts: 151 Rep Power: 1

Administrator

Re: VHDL code for Right Shift register

shash_satish2002, its great that you are getting responses, but my advice is that if you keep using forums to help with homework and labs, you'll never do well during your exams or in your post-university career. These questions can be answered by debug simulation and books...

#5 July 23rd, 2007, 12:23 PM

shah_Satish2002
Altera Scholar Re: VHDL code for Right Shift register

Join Date: Jul 2007 Posts: 25 Rep Power: 1620

Hello Sir, I am sorry..But actually i am doing project in company and i am just beginner in this field but this forum help me lot. Thank you sir.
#6 July 23rd, 2007, 10:30 PM

Avatar
Altera Guru Re: VHDL code for Right Shift register

Join Date: May 2007 Posts: 352 Rep Power: 2295

Shah, Where are you located, or, if you like, adjust your profile setting to allow mw to send you a private e-mail?
#7 June 12th, 2010, 03:50 PM
Join Date: Jun 2010 Posts: 18 Rep Power: 532

wadheraswati
Altera Pupil

Re: VHDL code for Right Shift register

This is a 8 BIT shift register with synchronous set SISO library ieee; use ieee.std_logic_1164.all;

entity shift is port(C, SI, S : in std_logic; SO : out std_logic); end shift;

architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, S) begin if (C'event and C='1') then if (S='1') then tmp <= (others =>'1'); else tmp <= tmp(6 downto 0) & SI; end if; end if; end process; SO <= tmp(7); end archi; i want to ask the meaning of the line that is in bold and red color i.e... tmp <= (others =>'1');
#8 June 13th, 2010, 03:47 AM
Join Date: Dec 2007 Location: Bochum Germany Posts: 4,467 Rep Power: 9419

FvM

Altera Guru

Re: VHDL code for Right Shift register

It's a synchronous preset of the SR to all '1'. By the way, a signal name of tmp for the shift register is rather unimaginative, isn't it?

Previous Thread | Next Thread

Posting Rules
You You You You may may may may not not not not post new threads post replies post attachments edit your posts Forum Jump
Quartus II and EDA Tools Discussion

BB code is On Smilies are On [IMG] code is On HTML code is Off Forum Rules

Go

Similar Threads
Thread
Shift register problem

Thread Starter
jcafaro10

Forum
Quartus II and EDA Tools Discussion

Replies
11

Last Post
September 7th,

Similar Threads
2009 11:11 AM RAM Based Shift Register AbdelFattah FPGA, Hardcopy, and CPLD Discussion 1 August 30th, 2009 10:33 AM August 10th, 2009 02:20 AM April 15th, 2009 11:36 PM August 26th, 2008 05:30 AM

10 bit shift register megafunction

corwin

Quartus II and EDA Tools Discussion

VHDL code for Left Shift register

steer.michael

Quartus II and EDA Tools Discussion

SPI interfacing + Shift Register

digitaltee

Quartus II and EDA Tools Discussion

You might also like