Compaction
Compaction
~
The operation of layout area minimization is called layout compaction
COMPACTION Of Space between the features Symbolic Layout Size of the feature Final Layout
Shape of the feature
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Compaction
Given:
i
Problem Formulation
n
M = fM1 M2 : : : M g, a set of geometric features s(M ), the minimum feature size. d(M M ), the minimum separation between features M & M
i j i
Objective:
Minimize the layout such that size(M ) s(M ) dist(M M ) d(M M ) where size(M ) and dist(M M ) are size of M and distance between M and M after the compaction, where 1 i j n.
i i i j i j i i j i i j
Algorithms for VLSI Physical Design Automation
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Compaction
Classi cation of Compaction Algorithms
Compaction Algorithms
Based on direction of movement of features
Based on minimum distance b/w features
Hierarchical Compaction
1-D Compaction
2-D Compaction
Constaint graph based
Virtual grid based
1 1 -D 2 Compaction
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Compaction
1-Dimensional Compaction
(Constraint Graph Based Compaction) Constraint Graph Generation
The constraint graph G = (V E ), is a weighted graph. Each vertex v 2 V represents a component. The set of edges, E , represents constraints.
Constraints in graph
Connectivity constraints
Separation constraints
Algorithms for VLSI Physical Design Automation
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Compaction
Connectivity Constraints
~
If the two features C and W are required to be within a distance s of each other, this connectivity constraint is represented in the graph as a pair of constraints between C and W , each with weight ;s.
x x
W s (a) -s C W
-s (b)
Algorithms for VLSI Physical Design Automation
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Compaction
Separation Constraints
Two features, A and B , are required to be at least d units d units apart from each other. The separation constraint is represented as an edge from A to B of weight d.
A B
~
d (a) d A (b) B
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Compaction
The Shadow-Propagation Method
1. The `shadow' of a feature is propagated along the direction of compaction. 2. The shadow is caused by shining an imaginary light from behind the feature under consideration. 3. Whenever the shadow is obstructed by another feature, an edge ~ is added to the graph between corresponding vertices. 4. The obstructed part is then removed.
~ M.Y. Hsueh and D. O. Pederson, U.C., Berkeley'79
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Compaction
Shadow-Propagation Algorithm
Algorithm SHADOW-PROPAGATION(Comp list component) begin
INITIALIZE-SCANLINE( component ) I= while( (LENGTH-SCANLINE( I ) < (top ; bottom)) and ( Comp list 6= ) ) curr comp = GET-NXT-COMP( Comp list ) I = LEFT-EDGE( curr comp ) if( IN-RANGE( I top bottom ) ) I = UNION( I I ) if( I 6= I ) ADD-CONSTRAINT( component curr comp ) I = UNION( I I )
i i
0
end.
Algorithms for VLSI Physical Design Automation
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Compaction
Example of Shadow Propagation
B A
~
Algorithms for VLSI Physical Design Automation
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Compaction
Interval Generation for Shadow Propagation
F Top B
Bottom (a) Top
B B
D,E
C 1 2 Bottom 3
C 4
(b)
Algorithms for VLSI Physical Design Automation
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Compaction
The Scanline Method
1. The scanline is an imaginary vertical (or horizontal) line that cuts through the layout in y-compaction (or x-compaction). 2. The rectangles, cut by the scanline, are stored in non-decreasing order of their x-coordinates of the left boundaries. 3. The scanline traverses from left to right of the layout.
~
4. When the scanline passes over the left edge of a rectangle, the rectangle is added to the scanline. 5. When the scanline passes over the right edge of a rectangle, the rectangle is deleted from the scanline.
~ A.A. Malik, ICCAD'87
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Compaction
Scanline Algorithm
Algorithm SCANLINE (G) begin while topsorted = 6 do
let R1 be the rst rectangle in topsorted and R2 be the rst rectangle in bottomsorted if YTOP(R1) YBOTTOM(R2) then INSERT(R1 scanline) topsorted = topsorted ; fR1g for each rectangle R 2 scanline that is at the left of R1 do ADD-CONSTRAINT(R R1 G) for each rectangle R 2 scanline that is at the right of R1 do ADD-CONSTRAINT(R1 R G)
i i j j
end.
Algorithms for VLSI Physical Design Automation
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Compaction
Example of Scanline Algorithm
A B
~
E F
scanline
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Compaction
Virtual Grid Based Compaction
1. Virtual grid method assumes the layout is to be drawn on a grid. 2. Each component is considered attached to a grid line. 3. The compaction operation compresses the grid along with all components placed on it keeping the grid lines straight along the way. 4. The minimum distance between two adjacent grid-lines depends on the ~ components on these grid lines. 5. The advantage of virtual grid method is that the algorithms are simple and can be easily implemented. 6. Virtual grid method does not produce compact layouts as compared to the constraint graph method.
Algorithms for VLSI Physical Design Automation
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Compaction
Virtual Grid Symbolic Inverter
A 4 3 3 D 3 4 3 G B E 5 2 1 2 4 5 H
C 5 6 3
F 3 3 1
16
12
(a)
D A
14
11
(b)
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Compaction
Split Graph Compaction
1. The grid points which contain features are added to the data structure. 2. The circuit features falling on the same virtual grid lines are grouped together. 3. The groups are rst x-compacted (and y-compacted) by determining the spacing necessary for each component in the group. ~ 4. Features are spaced with respect to the features in the neighboring groups.
D. G. Boyer and N. Weste, ICCAD'83
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Compaction
Example of Split Grid Compaction
A 4 3 3 D 3 4 3 G B E 5 2 1 2 4 5 H
C 5 6 3
F 3 3 1
16
12
(a)
10 D A 11 G
E B H
14
(b)
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Compaction
Compression-Ridge Method
1. Compression ridge is a constant width band of empty space stretching from one side of the layout to the other side. 2. Compression ridge can intersect wires that are perpendicular to it. However, it cannot intersect those wires that are parallel to it.
~
3. The width of a compression ridge is such that when the space is removed, no design rules should be violated in the resulting layout.
S. B. Akers and J. M. Geyer and D. L. Roberts, DAC'70
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Compaction
Example of Compression-Ridge Method
Compression ridge Block
(a)
(b)
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Compaction
1 -Dimensional Compaction 12
~
(Simulated Zone Re ning Process)
1. The vacant spaces in the layout is considered as `impurity'. 2. The blocks are re-arranged, row by row, after they have been moved across the free zone.
~
3. During movement in the free zone, the blocks travel through the entire width of the layout.
H. Shin and A. L. Sangiovanni-Vincentelli and C. H. Sequin, DAC'86
Algorithms for VLSI Physical Design Automation
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Compaction
Zone Re ning Process
melting zone Top
ZONE
~
Heater re-crystallization zone
Ceiling Floor
Bottom
(a)
(b)
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Compaction
The Algorithm
Begin Algorithm Input: Partially compacted layout obtained by two two applications of 1-D compactor. oor:= List of all the blocks which are visible the top ceiling:= List of all the blocks which are visible from the bottom While all the blocks are moved from ceiling to floor
g end
Select the lowest block from ceiling such that the gap between floor and ceiling is maximize Move the block to floor
Algorithms for VLSI Physical Design Automation
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Compaction
Problem instance and its XY adjacency graph
Ceiling
G D C F y2 G D E F D G C x2 x1 A B A B E F C
Floor
A nil B y1
(a)
G D E F
(b)
gap 1
gap 2
C A C B
Ceiling
G D C E F
(c)
y2
F G
E F
x2 x1 C A C B y1 C B A B
Floor
A
Algorithms for VLSI Physical Design Automation
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(e)
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Compaction
Two-Dimensional Compaction: Constraints
(x i , y i )
(x j , y j )
Bi Wj
(x j , y j )
Wi
Wj
(x i , y i )
(x j , y j ) (x i , y i )
(a)
(x i , y i ) (x j , y j )
(b)
x +w x y +h y x ;w x y ;h y x +w x y y x +w x x x x x x x y + r1 y y + r2 y x x x x y y y y c1 : x + d1 x c2 : x + d2 x c3 : y + d3 y c4 : y + d4 Where w and h are the width and height of the block B r1 r2 ] is the range between B and the wire W d is the distance between B and B .
i i
0
j j i
ij
ij
ij
ij
ij
ij
ij
ij
ij
ij
ij
ij
k ij
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Compaction
Hierarchical Compaction
1. Given a hierarchical symbolic layout, hierarchical constraint graph is generated at each level of the hierarchy of the design from bottom up. 2. Initially, constraints are generated for all the leaf cells consisting of basic features. 3. Each leaf cell is compacted using the corresponding constraint graph and ~ the boundary of the compacted leaf cell is xed. 4. Once the leaf cell is compacted and the boundary is xed, the cell can be treated as a single cell in the next level in the hierarchy and constraints can be generated for the cells in that level. 5. The compaction is carried out by generating constraints at each level.
Algorithms for VLSI Physical Design Automation
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Compaction
Example of Hierarchical Compaction
C1
E A D F B
C2 C G H I J
Hierarchical layout
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Compaction
Example of Hierarchical Compaction
E
C1
R
D
C1
G1
C2
C2
G2
A L
G
B C
G3
Hierarchical constraint graph
j
Algorithms for VLSI Physical Design Automation
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Compaction
Summary
1. The objective of a compaction algorithm is to reduce the layout area. 2. There are two major compaction strategies: the constraint-graph based compaction and the virtual grid based compaction. 3. Constraint-graph based compactors usually produce smaller area layouts ~ as compared to the virtual grid compactors. 4. Virtual grid compactors typically run faster as compared to the virtual grid compactors. 5. The speed of both type of algorithms can be improved by using hierarchy of the layout.
Algorithms for VLSI Physical Design Automation
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