Using ADS8410/13 in Daisy-Chain Mode: Application Report

Application Report
SLAA296 May 2006
Using ADS8410/13 in Daisy-Chain Mode

Bhaskar Goswami, Vikash Sethia ....................................................................................... DAP Nyquist ABSTRACT Many applications require multiple analog-to-digital converters (ADC) in a system. Daisy chaining multiple ADCs enables the use of a single data receiver or a small FPGA. It offers easy and minimal digital routing. This application report describes how multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a high-speed (200 Mbps) LVDS serial interface. This application report also suggests a way to de-serialize high-speed serial data. It discusses the board design aspects and test guidelines. It also presents reference schematics and layouts for the boards. Finally, the reference board results are presented.
Contents 1 Introduction .......................................................................................... 2 2 Description of the Device .......................................................................... 2 3 Digital Interface ..................................................................................... 2 4 Definition of Daisy Chain .......................................................................... 3 5 Block Diagram ...................................................................................... 3 6 Timing ................................................................................................ 4 7 Board Design Aspects ............................................................................ 12 8 System Block Diagram ........................................................................... 17 9 De-Serialization.................................................................................... 19 10 Limitation on Number of Devices in the Chain ................................................ 20 11 Results .............................................................................................. 20 12 Conclusion ......................................................................................... 24 Appendix A ADS8413EVM Daisy Chain Schematics, Layout, and Photograph ............... 25 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Three Devices in Daisy Chain .................................................................... 3 Four Devices in Daisy-Chain Mode .............................................................. 4 Sample and Convert With Wait (Less Than 2-MSPS Throughput) .......................... 6 Sample and Convert With No Wait or Back to Back (2-MSPS Throughput)................ 6 Data Read With CS Low and BYTE = 0 ......................................................... 7 Start of Data Read Cycle With RD and CS Low and Device in Wait or Sample Phase .. 8 Start of Data Read Cycle With End of Conversion ............................................. 9 Data Read Cycle End With MODE C/D = 0 ..................................................... 9 Data Read Operation for Devices in Daisy-Chain Mode ..................................... 10 Data Propagation From Device n to Device n+1 in Daisy-Chain Mode .................... 11 Four Devices Placed in Straight Line Fashion ................................................ 12 Four Devices Placed in Circular Fashion ...................................................... 12 LVDS Driver/ Receiver in Point-to-Point Connection ......................................... 12 CLK_O and SYNC_O Connection Between Last Device and the Deserializers.......... 13 Terminating at Both Receivers .................................................................. 13 Terminating at One Receiver .................................................................... 13 Terminating at Source End ...................................................................... 14 Analog and Digital Circuitry Are Separated in the Layout With a Virtual Boundary ..... 15
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Introduction 19 20 21 22 23 24 25 26 27 Devices Are Rotated and Placed to Reduce LVDS Trace Length.......................... LVDS Routing ..................................................................................... First and Second Device in the Chain .......................................................... Third and Forth Device in the Chain ............................................................ Last ADC in the Chain and the Deserializers ................................................. CLK_I and CLK_O of Device 1 .................................................................. CLK_I and CLK_O of Device 2 ................................................................. CLK_I and CLK_O of Device 3 .................................................................. CLK_I and CLK_O of Device 4 .................................................................. List of Tables 1 2 3 4 CONVST and CSTART Timing Control.......................................................... 6 Clock Duty Cycle .................................................................................. 21 Linearity of Four Devices in the Chain ......................................................... 23 SNR and THD of Four Devices in the Chain .................................................. 23 16 17 18 19 20 21 22 22 23
Introduction
In many applications, multiple ADCs are used to convert several analog channels. For stand-alone ADCs (i.e., ADCs without an option for daisy chain or cascade) multiple digital outputs are sometimes multiplexed with a digital multiplexer. In other cases, a high pin-count FPGA or DSP is used to receive multiple digital outputs. To avoid this complexity, the ADS8410/13 offers a daisy-chain mode (explained in detail later) in which data from multiple devices are transmitted through the chain and is received from only the last device. Layout is simpler because of point-to-point connection. The serial LVDS (low voltage differential signaling) interface offers high- speed (200 Mbps) data transmission to enable the use of more devices for a given throughput. The low differential swing in LVDS mode causes lower ground bounce in the system and less crosstalk among the digital signals. This helps to achieve a better signal-to-noise ratio in a system.
Description of the Device

The ADS8410 and ADS8413 are 16-bit 2-MSPS A/D converters with 4-V internal reference. The devices include a capacitor-based SAR A/D converter with inherent sample and hold. These devices offer a 200-Mbps serial LVDS interface. The interface is designed to support cascading and daisy chaining of multiple devices. There is a mode to select 16/8-bit data frame to interface with shift registers for converting the data to parallel format. ADS8410 has pseudo-differential input stage. The IN swing of 200 mV is useful for compensating the ground voltage mismatch between the ADC and the sensor and also for canceling the common-mode noise. The ADS8413 has unipolar differential input range, which supports differential input swing of VREF to +VREF with a common mode of +VREF/2. The devices operate at a lower power when used at lower conversion rates, because of the nap feature. Nap mode shuts down the device partially when the device is not converting. These devices are available in a 48-pin QFN package.
Digital Interface
The ADS8410/13 offers 200 Mbps LVDS interface. LVDS is current output which terminates at the receiver with a 100- resistor which converts it to voltage. The high speed offers more device integration in a system at a given ADC sampling rate. LVDS has a typical differential swing of 680 mV (+680 mV for logic 1 and 680 mV for logic 0) which is better in a low-noise system. The differential nature of this signaling filters any common-mode noise.
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Definition of Daisy Chain
Definition of Daisy Chain

In daisy-chain mode, multiple devices are connected such that each device receives the previous devices data and transfers it along with its own data. Consider a situation where N devices are in the chain. The second device receives the first devices data and passes this data along with its own data to the third device. The third device sends its own data along with first and second devices data. The Nth device sends its own data with all N - 1 devices' data. Finally, one receiver is connected to the Nth device, which collects all the data from the Nth device. Figure 1 shows how three (N = 3) devices work in a daisy chain.
st
nd
1 Device
D1
2 Device
rd
D2
D1
3 Device
D3
D2
D1
Receiver
Figure 1. Three Devices in Daisy Chain
Block Diagram
Figure 2 shows how four devices are connected in a daisy chain using the ADS8410/13. MODE C/D (cascade or daisy-chain mode) has to be logic zero to operate in daisy-chain mode. The first device in the chain is identified by LAT Y/N = 0. For all other devices, LAT Y/N = 1. LAT Y/N signifies that the first device sends out data without latency and the other devices send out data with latency. Either CSTART (LVDS) or CONVST(CMOS) is used as a conversion start signal. Depending on the CLK I/E signal, the first device either takes in an external clock or generates an internal clock. This clock is used as the master clock for all the devices in the daisy chain, and the interface is synchronized with this clock. Other devices can only accept CLK_O from the previous device as an external clock. SDI (Serial Data Input) and SYNC_I (Frame Sync Input) of the first device should be logic 0 (+ve terminal to GND and ve terminal to +VBD). BUS_BUSY = 1 signifies that the device is busy sending out data in the bus. RD is Data Read Request to the Device and also acts as a handshake signal for daisy-chain and cascade operation. RD = 1 brings about a 3-state device output. BUS_BUSY of the last device can be connected to RD of the first device. Otherwise, BUS_BUSY of the last device should be kept floating. RD of the first device should be connected to GND in this case.
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Timing
VDD/GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
VDD LAT Y/N CONVST CSZ
IN1
IN3
CLK I/E
CLK I/E
CLK I/E
IN4
ANALOG IN
ANALOG IN
ANALOG IN
ANALOG IN
LAT Y/N
LAT Y/N
MODE C/D
MODE C/D
MODE C/D
LAT Y/N
Device #1 SDI SDO
Device #2 SDI SDO CLK_O BUS_BUSY
Device #3 SDI SDO
Device #4 SDI SDO
SYNC_I SYNC_O CLK_I RD CLK_O BUS_BUSY
SYNC_I SYNC_O CLK_I RD
CONVST
CONVST
CONVST
CSTART
Separate CS , CONVST , CSTART
for each IC
Figure 2. Four Devices in Daisy-Chain Mode
6 6.1
Timing Timing Requirements

in the following timing table, all specifications are typical at 40C to 85C, +VA= +5 V, +VBD = +5 V and 3.3 V (unless otherwise noted).
PARAMETER SAMPLING AND CONVERSION RELATED tacq Acquisition time 100 391 100 40 5 5 +VBD = 5 V +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V 100 13 14 7 8 ns ns ns ns ns ns ns Figure 3, Figure 4 Figure 3, Figure 4 Figure 3 Figure 3, Figure 4 Figure 3 Figure 3, Figure 4 Figure 3, Figure 4 Figure 3, Figure 4 Figure 3 , Table 1 MIN TYP MAX UNIT REF
tconv Conversion time tw1 tw2 td1 td2 td3 td4 tw3 Pulse duration, CONVST high Pulse duration, CONVST low Delay time, CONVST rising edge to sample start Delay time, CONVST falling edge to conversion start Delay time, CONVST falling edge to busy high
Delay time, conversion end to busy low Pulse duration, CSTART high
CSTART
CSTART
CSTART
CSZ
CSZ
CS
MODE C/D
CLK I/E
ns ns
VDD
IN2
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Timing
PARAMETER tw4 Pulse duration, CSTART low MIN 45 TYP MAX UNIT ns REF Figure 3, Figure 4 , Table 1 Figure 3, Figure 4 Table 1 Figure 3, Figure 4 Table 1 Figure 3, Figure 4 Table 1
td5
Delay time, CSTART rising edge to sample start
7.5
ns
td6
Delay time, CSTART falling edge to conversion start +VBD = 5 V
7.5 15.5 16.5
ns
td7
Delay time, CSTART falling edge to busy high
+VBD = 3.3 V
ns
I/O RELATED td8 td9 td10 td11 td12 td13 tw5 td14 td15 td16 tpd1 td18 td19 tclk Delay time, RD falling edge while CS low to BUS_BUSY high Delay time, RD falling edge while CS low to SYNC_O and SDO out of 3-state condition (for device with LAT_Y/N pulled low) +VBD = 5 V +VBD = 3.3 V 16 28 29 22 7 8 6 +VBD = 5 V +VBD = 3.3 V 5 + 4*tCLK 5.5 + 4*tCLK 5 +VBD = 5 V +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V 4*tCLK 6 4*tCLK 6.5 1.3 1.4 4*tCLK 2.5 4*tCLK 3 4 11 + 0.5*tCLK 7 8 40 40.5 190 200 210 9 + tCLK 8 + 5*tCLK 8.5 + 5*tCLK ns ns Figure 6 Figure 7 ns Figure 6
Delay time, pre_conversion end (point A) to SYNC_O and SDO out of 3-state condition Delay time, pre_conversion end (point A) to BUS_BUSY high Delay time, conversion phase end to SYNC_O high Delay time, RD falling edge while CS low to SYNC_O high Pulse duration, RD low for device in no latency mode Delay time, CLK_O rising edge to data valid Delay time, BUS_BUSY low to SYNC_O high in daisy-chain mode indicating receiving device to output data Delay time, CLK_O to SDO and SYNC_O 3-state Propagation delay time, SYNC_I to SYNC_O in daisy-chain mode Delay time, RD rising edge to BUS_BUSY high for device with LAT_Y/N = 1 Delay time, point A indicating clear for bus 3-state release to BUSY falling edge CLK frequency (serial data rate) +VBD = 5 V +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V +VBD = 5 V +VBD = 3.3 V
ns ns ns ns ns
Figure 7 Figure 7 Figure 6 Figure 9 Figure 6, Figure 7 Figure 8, Figure 10 Figure 8, Figure 10 Figure 10 Figure 9
ns ns ns ns
ns MHz
Figure 7
6.2
Sample and Convert

The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal. Both signals are functionally identical. The following diagrams show control with CONVST. The rising edge of CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in the wait state. Figure 4 shows the case when the device is in the conversion phase at the rising edge of CONVST. In this case, the sample phase starts immediately at the end of the conversion phase, and there is no wait state.
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Timing
Figure 3. Sample and Convert With Wait (Less Than 2-MSPS Throughput)
Figure 4. Sample and Convert With No Wait or Back to Back (2-MSPS Throughput) The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART). A high level on the BUSY output indicates an ongoing conversion. The device conversion time is fixed. The falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing conversion. A data read after a conversion abort fetches invalid data. Valid data is only available after a sample phase and a conversion phase has completed. The timing diagram for control with CSTART is similar to Figure 3 and Figure 4. Table 1 shows the equivalent timing for control with CONVST and CSTART. Table 1. CONVST and CSTART Timing Control
TIMING FOR CONTROL WITH CONVST tw1 tw2 t1 t2 t3 TIMING FOR CONTROL WITH CSTART tw3 tw4 t5 t6 t7
6.3
Data Read Operation

The ADS8413 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a single device or multiple devices can be implemented with a daisy-chain or cascade configuration. The following sections discuss data read timing when a single device is used.
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Timing
6.3.1
Data Read for a Single Device (See Table 1 for Device Configuration) For a single device, the two possible read cycle starts are: a data read cycle start during a wait or sample phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change depending on MODE C/D selection. Figure 5 explains the data read cycle. The details of a read frame start with the two previous listed conditions and a read cycle end with MODE C/D selection are explained in Figure 6, Figure 7, and Figure 8, respectively.
See Figure 6 See Figures 7 and 8
RD
SYNC_O CLK_O 1F 1R 2R 18F 18R
SDO D15 BUS BUSY D14 D0
Figure 5. Data Read With CS Low and BYTE = 0 As shown in Figure 5, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge) if the BYTE input is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th rising edge (18R, or the second rising edge after a SYNC_O rising edge). CS high during a data read results in a 3-state SYNC_O and SDO condition. These signals remain in the 3-state condition until the start of the next data read cycle. 6.3.2 Data Read Cycle Start During Wait or Sample Phase As shown in Figure 6, the falling edge of RD, with CS low and when the device is in a wait or sample phase, triggers the start of a read cycle. The cycle starts when BUS_BUSY goes high and SYNC_O, SDO are released from the 3-state condition. SYNC_O is low at the start and rises to a high level td13 ns after the falling edge of RD. As shown in Figure 6, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read cycle are discussed in the previous section (see Figure 5).
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Timing
td9 RD
td13 td8 BUSY
BUS_BUSY 0R CLK_O 1F 1R 3R
SYNC_O td14 SDO_O MSB MSB - 1
Figure 6. Start of Data Read Cycle With RD and CS Low and Device in Wait or Sample Phase
6.3.3
Data Read Cycle Start at End of Conversion Phase (Read Without Latency, Back-to-Back) This mode is optimized for a data read immediately after the end of a conversion phase and ensures that the data read is complete before the sample end while running at 2 MSPS. Point A in Figure 7 indicates pre_conversion_end; it occurs td19 ns before the falling edge of BUSY or [(td2 + tcnv + td4) td19] ns after the falling edge of CONVST. A read cycle is initiated at point A if RD is issued before point A while CS is low. Alternately, RD and CS can be held low. At the start of the read cycle, BUS_BUSY rises to a high level and the LVDS outputs are released from the 3-state condition. The rising edge of SYNC_O, occurs td12 ns after the conversion end. As shown in Figure 7, the MSB is shifted on the 2nd rising edge of the clock (2R). Other details about the data read cycle are discussed in the previous section (see Figure 5).
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Timing
Conversion Phase A td19 Conversion End
RD_REQ (Int) td11 BUSY td10 BUS_BUSY O/P
td4
0R CLK_O td12 SYNC_O
1F
1R
2R
3R
td14 SDO_O MSB MSB 1
Figure 7. Start of Data Read Cycle With End of Conversion
6.3.4
Data Read Cycle End (With MODE C/D = 0) A data read cycle ends after all 16 bits have been serially latched out. Figure 8 shows the timing of the falling edge of BUS_BUSY and the rising edge of SYNC_O with respect to SDO. SYNC_O rises on the 16th rising edge of CLK_O. As shown in Figure 6 and Figure 7, the MSB is shifted out on the 2nd rising edge of CLK_O. Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST CS = 0
BUS_BUSY td15 SYNC_O
15R CLK_O
16R
17R
18R
td16 SDO LSB 1 LSB
Figure 8. Data Read Cycle End With MODE C/D = 0
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Timing
The next two rising edges of CLK_O are shown as 17R and 18R in Figure 8. On 17R, the LSB is latched out, and on 18R, SDO and SYNC-O go to a 3-state condition. Note that BUS_BUSY falls td15 ns before the rising edge of SYNC_O when MODE C/D = 0. Care must be taken not to allow LVDS bus usage by any other device until the end of the read cycle or (td15 + 2/fclk + td16) ns after the falling edge of BUS_BUSY.
6.4
Timing Diagrams for Daisy-Chain Operation

The conversion speed for n devices in the chain must be selected such that: 1/conversion speed > read startup delay + n (data frame duration) + td16 Read startup delay = 10 ns + (td19 td4) + td12 + 2/fCLK Data frame duration = 16/fCLK Note that it is unnecessary for all devices in the chain to sample the data simultaneously. But, all of the devices must operate with the same exact conversion speed.
nth CONV n + 1 Tracking n + 1 Conversion
CONVST #1
See Figure 6 for details CS tw5 RD #1 BUS_BUSY #n (Last device) BUS_BUSY #1 RD #2
SDO #1 SDI #2
16Bit Data nth conversion See Figure 12 for details
SYNC_O #1 SYNC_I #2 td18 BUS_BUSY #2 RD #3 SDO #2 SDI #3 #1 16Bits nth conversion #2 16Bits nth conversion
SYNC_O #2 SYNC_I #3
Figure 9. Data Read Operation for Devices in Daisy-Chain Mode
6.5
Data Read Operation

On power up, BUS_BUSY of all of the devices is low. The devices receive CONVST or CSTART to sample and start the conversion. The first device in the chain starts the data read cycle at the end of its conversion. BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start. Device 2 BUS_BUSY goes high on the rising edge of RD #1. This propagates until the last device in the
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Timing
chain. Device 2 receives CLK_I, SDI, and SYNC_I from device 1, and it passes all of these signals to the next device. Device 2 (and every subsequent device in the chain) passes the received signals to its output until it sees the falling edge of RD #1 (same as BUS_BUSY of the previous device). In daisy-chain mode, BUS_BUSY for any device falls when it has passed all of the previous device data followed by its own data. The falling edge of BUS_BUSY occurs before the rising edge of SYNC_O. This indicates to the receiving device that the previous data chain is over, and it is now the receiving device's turn to output the data. The device outputs the data from the last completed conversion. BUS_BUSY of the last device in the chain is fed back to RD of the first device (or device 1 RD tied to 0). This makes sure that RD of device 1 is low before its conversion is over. The chain continues with only one external signal (CONVST or CSTART) when CS is held low. Every device LVDS output goes to a 3-state condition once all data transfer through the device has been completed. CS going high during the data read cycle of any device places its SYNC_O and SDO in a 3-state condition. This halts the propagation of data through the chain. To reset this condition, it is necessary to assert CS high for all devices. The new read sequence starts only after CS for all devices is low before point A as shown in Figure 7. The high pulse on CS must be at least 20 ns wide. It is better to connect CS of all of the devices together to avoid undesired halting of the daisy chain.
CS = 0
BUS_BUSY #1 RD #2 td15 SYNC_O #1 SYNC_I #2 15R CLK_O #1 CLK_I #2 16R 17R td16 18R
SDO #1 SDO #2
LSB 1 #1
LSB #1
BUSY_BUS #2 = 1 17F 17R CLK_O #2 18R
tpd1 SYNC_O #2 #1 DATA LSB 1 #1
LSB #1
MSB
MSB 1
#2 DATA
Figure 10. Data Propagation From Device n to Device n+1 in Daisy-Chain Mode As shown in Figure 10, a propagation delay of tpd1 occurs from SYNC_I to SYNC_O or SDI to SDO. Note that the data frames of all devices in the chain appear seamless at the last device output. The rising edge of SYNC_O occurs at an interval of 16 clocks (or 8 clocks in BYTE mode); this can be used as data frame sync. The deserializer at the output of the last device can shift the data on every falling edge of the clock and it can latch the parallel 16-bit word on the second rising edge of CLK_O (shown as 18R) after every rising edge of SYNC_O.
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Board Design Aspects
7 7.1
Board Design Aspects Placement

Consider an application where four devices are operated in daisy-chain mode. There aretwo ways to do this layout. The chain can be in a straight line fashion (as in Figure 11) or in a circular fashion (as in Figure 12).
1 Device
st
2 Device
nd
3 Device
rd
4 Device
th
Receiver
Figure 11. Four Devices Placed in Straight Line Fashion
3 Device
rd
4 Device
th
Receiver
2 Device
nd
1 Device
st
Figure 12. Four Devices Placed in Circular Fashion Any one of the layouts can be chosen depending on the area and shape of the printed-circuit board.
7.2
Signal Integrity
The device offers high speed LVDS CLK_O (Clock Output), SDO (Serial Data Output) and SYNC_O (Frame Sync Output) signals which have a typical rise time of only 700 ps. According to LVDS standards, the receiver termination needs to be 100 (shunt resistance between +ve and ve terminal of each LVDS signals) to have proper voltage swing. To avoid reflection, the differential characteristic impedance needs to match with the 100- termination. So, CLK_O, SDO, and SYNC_O differential traces need to have 100- differential characteristic impedance.
7.3
Termination Strategy
For point-to-point connection, LVDS signals are terminated with a 100- resistor at the receiver end as shown in Figure 13.
ADC
100 W
ADC
Figure 13. LVDS Driver/ Receiver in Point-to-Point Connection The differential characteristic impedance of the line should be maintained close to 100 . This strategy is followed for signals which connect one ADC to another ADC. As an example, this is followed for the traces between CLK_O of the first device and CLK_I (Clock Input) of the second device. This method is not valid for the signals which connect the last device in the chain to two deserializers which are in cascade (as shown in Figure 14).
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ADC
SN65LVDS152
SN65LVDS152
Figure 14. CLK_O and SYNC_O Connection Between Last Device and the Deserializers One way to terminate this structure is to have two 100- resistor termination at both receiver ends (see Figure 15). But because LVDS is a current source, two parallel resistors drive the voltage swing to half. If your receiver has lower threshold than one half of LVDS differential swing and you have enough noise margin for your system, you can use this termination strategy.
ADC
100 W SN65LVDS152
100 W SN65LVDS152
Figure 15. Terminating at Both Receivers Another way to terminate is to put the termination at any one of the receiver ends. In this case, the signal is reflected from the receiver which is not terminated. Make sure that the trace length of the unterminated end from the common point is smaller than 0.6 inch (see Figure 16). This is valid for an FR4 printed-circuit board.
Smaller Than 0.6 inch
ADC
SN65LVDS152
100 W SN65LVDS152
Figure 16. Terminating at One Receiver One more way to terminate in this case is to terminate at the driver end. The signal gets reflected from the receiver ends once and gets absorbed at the driver end fully. Ensure that the trace length of the unterminated trace from the common point (see Figure 17, in this case point A to B, C to D, A to E, or C to F) is less than 0.6 inch.
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A ADC 100 W B
D SN65LVDS152 E
F SN65LVDS152
Figure 17. Terminating at Source End
7.4
Layout Guidelines
ADS8410/13 offers high-speed digital interface. Analog and digital layout should not be mixed up. Analog placement and routing should be separated from the digital placement and routing as far as possible. The black line in Figure 18 is a virtual boundary for the analog and digital placement. Analog circuitry (operational amplifiers and reference input) is on the left side of the boundary. The digital circuitry (deserializer, clock multiplier, and digital buffers) is on the right side of the boundary.
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Figure 18. Analog and Digital Circuitry Are Separated in the Layout With a Virtual Boundary Each device (ADS8410/13) is rotated appropriately and placed such that LVDS outputs from the previous device and LVDS inputs of the device connects in the shortest path. In Figure 19, the arrows indicate pin number 1 for each device. Note that a device is rotated by 90 degrees with respect to the previous device to make the LVDS lines short.
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Figure 19. Devices Are Rotated and Placed to Reduce LVDS Trace Length ADS8410/13 offers high-speed (200 Mbps) LVDS interface. Therefore, it is important to meet setup and hold time requirements for LVDS signals. To achieve this, the length of CLK_O to CLK_I, SDO to SDI, and SYNC_O to SYNC_I (Figure 20) should be equal. This is valid for LVDS signals between two devices and also the LVDS signals between last device and the deserializers. Any length mismatch should be less than 100 mils (1 mil = 1/1000 inch). Sometimes, traces are made serpentine in nature to match the length. Figure 20 shows routing of LVDS signals between device 1 and 2. Also note that LVDS pairs are routed differentially to make the differential characteristic impedance constant.
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System Block Diagram
CLK_I CLK_O
SDI SYNC_I
SDO
SYNC_O
Dev 2 Dev 1
Figure 20. LVDS Routing

Figure 21 and Figure 22 show how four devices in a daisy chain are tested. Figure 21 shows how first and second devices are connected. A pattern generator is used to generate necessary control signals and clock. A 25-MHz clock is generated from the pattern generator and is multiplied by a clock multiplier (CDCF5801) to get a 200-MHz LVDS clock. CMOS to LVDS drivers (SN75LVDS389) are used to convert from CMOS/ TTL to LVDS.
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DUT #2 CS BUS_BUSY CLK_O CONVST CSTART SDO SYNC_O CLK_I SDI SYNC_I RD
DUT#3
CMOS BUS_ BUSY BUSY LAT Y/N CLK I/E BYTE, MODE C/D NAP, PD CS, RD CONVST DUT #1
LVDS CLK_O SDO SYNC_O SDI SYNC_I CSTART CLK_I 200 MHz CLK Pattern Generator
CMOS to LVDS Driver
VDD/GND Through Jumper Settings
Clock multiplier (has PLL inside)
25 MHz CLK
Figure 21. First and Second Device in the Chain Figure 22 shows how third and forth devices are connected. Serial data from the forth device is converted to parallel by two cascaded SN65LVDS152
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De-Serialization
Last DUT #4 BUS_BUSY To capture card CLK_O SDO SYNC_O RD CS CLK_I SDI SYNC_I
D0-D15
Deserialiser
CMOS BUS_ BUSY BUSY CLK_O SDO
LVDS
Pattern Generator DUT #2
VDD/GND Through Jumper Settings
BUS_BUSY#2
SYNC_O LAT Y/N CLK I/E BYTE, MODE C/D NAP, PD RD CS, CONVST
CLK_I SDI SYNC_I CSTART
Diff Driver
DUT #3
Figure 22. Third and Forth Device in the Chain
De-Serialization
The interface is compatible with the TI deserializer SN65LVDS152. SN65LVDS152 is a 10-bit deserializer. Two such devices are cascaded to get 16-bit parallel data output. The following diagram shows the connection of the deserializer with the ADC (this is the last ADC in the chain). Figure 23 shows this connection with the necessary terminations.
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Limitation on Number of Devices in the Chain
DI+ DILCI+ LCICLK_O+ CLK_OSDO + SDOSYNC_O+ SYNC_OADS8410/13
MCIMCI+
COCO+
SN65LVDS152
DI+ DILCI+ LCICOCO+ MCIMCI+
100 W Resistor
SN65LVDS152
Figure 23. Last ADC in the Chain and the Deserializers
10
Limitation on Number of Devices in the Chain

Theoretically, the number of devices that can be in daisy chained are unlimited. If more than four devices are used, the sampling rate needs to be reduced. Seethe Timing Diagrams for Daisy Chain Operation section of the ADS8410/13 data sheet for the relation between sampling rate and the number of devices in a daisy chain. However, the duty cycle of the clock output (CLK_O) can be degraded to 40%60% with the internal clock mode operation or with the external clock mode operation (provided external input clock (CLK_I) duty cycle is 50%) at 200 MHz. CLK_O of device 1 is CLK_I of device 2. So, device 2 sees a clock with 40%60% duty cycle as the external input clock. CLK_O of device 2 is further degraded. Therefore, as the number of devices increases in a chain, the clock duty cycle of the last device can degrade further which may cause setup and hold-time violation. But typically, four devices can be operated in a daisy chain with a 200-MHz external or internal clock. If the clock frequency is reduced, more devices can be integrated in the chain.
11
Results
11.1 Clock Duty Cycle

One important parameter when multiple devices are daisy chained is the clock duty cycle. An external clock is used as an input to the first device, or the internal clock from the first device is used for the master clock. This clock then travels through four devices and finally comes out from the fourth device as CLK_O. SDO and SYNC_O are generated from the positive edge of CLK_O, but they are latched at the deserializer at the negative edge of CLK_O. Any degradation in the duty cycle shifts the negative edge of CLK_O with respect to the positive edge of CLK_O. This may violate setup and hold time. Careful design of transmitters and receivers of ADS8410/13 ensures that the duty cycle degradation is within the limit. Table 2 lists the measured duty cycle with both external and internal clock.
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Results
Table 2. Clock Duty Cycle

DUTY CYCLE INPUT CLOCK External clock Internal clock 49% CLK_O #1 56% 52% CLK_O #2 47% 54% CLK_O #3 58% 51% CLK_O #4 43% 54%
The following Figure 24 through Figure 27 show CLK_I and CLK_O for four devices in a daisy chain. Blue color denotes CLK_I, and pink color denotes CLK_O. An external clock of 49% duty cycle is used in these examples.
Figure 24. CLK_I and CLK_O of Device 1
21
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Results
22
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Results
11.2 Linearity Across Devices

Table 3 shows DNL and INL of ADS8413 versus the device number in the daisy chain. The data has been captured for four devices in the chain at 200-MHz external clock, and 2-MSPS throughput. Table 3. Linearity of Four Devices in the Chain
DEVICE 1 2 3 4 DNL MAX 0.88 0.87 0.88 0.79 MIN 0.68 0.77 0.70 0.73 INL MAX 1.13 1.59 1.14 1.36 MIN 1.62 1.15 1.30 1.21
11.3 SNR and THD Across Devices

Table 4 shows the ac performance of ADS8413 in the daisy chain. The data has been collected for four devices with the input-signal frequency of 20 kHz at a sampling rate of 2 MSPS and an external clock of 200 MHz. Table 4. SNR and THD of Four Devices in the Chain
DEVICE 1 2 3 SNR 91.07 90.54 91.38 THD 103.66 105.74 101.08
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Conclusion
Table 4. SNR and THD of Four Devices in the Chain (continued)

DEVICE 4 SNR 91.39 THD 101.12
11.4 Overdrive Test

The ADS8410/13 works in daisy-chain mode excellently even if one or more devices are overdriven with input voltage more than device power supply. This was tested with a power supply of 5 V. The inputs (IN+, and IN) were overdriven by 5.3 V (+0.3 V for IN in case of ADS8410) and 0.3V (absolute maximum rating). The overdriven device outputs SDO, SYNC_O, and CLK_O normally. The data from the overdriven device may not be correct because absolute input voltage range is lower than this (0.2 to Vref + 0.2). All other devices (without overdrive) function normally in the chain.
12
Conclusion
Daisy-chain mode offers a free-running clock which helps to synchronize digital circuitry easily. The free-running nature of the clock offers the flexibility to use a PLL in the digital system. This system can run with its own internal clock (clock is generated from the first device) or an external clock. The external clock should be a free-running clock. The full frame (conversion and acquisition) of the sampling time of the ADC is available for data transfer. This allows using four devices with a throughput of 2 MSPS. No performance degradation was seen with four devices in a daisy-chain configuration.
24
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Appendix A
Appendix A ADS8413EVM Daisy Chain Schematics, Layout, and Photograph A.1 Schematics
The daisy chain schematics are affixed to this page.
25
4
VCC3.3 JUMPERX3P
3 1 2
3
LAT Y/N_B
2
LAT Y/N_A CLK I/E_A MODE C/D
AVDD(REF)
LAT Y/N
BYTE
AVSS(REF)
REFM
REFM
CLK I/E
NAP
PD
24 23 22 21 20 19 18 17 16 15 14 13
INPA VCC3.3 JUMPERX3P

3 1 2
J75 GND CLK I/E_A INMA J76 GND CLK I/E_B
1 0ohms
R209
J199 J188
1 1
A
INP1
NAP
REFOUT NC AVDD
RD BUSY BVSS
J40
PD
DUT8
J2041 J2071 R307
AVSS INP INM AVSS(IN) AVDD(IN) AVDD(COMP) PBKG(DIG) CSTART+ CSTARTAVSS(COMP) DVSS DVDD PBKG(ANA)
BVDD SYNC_O+ SYNC_OSDO+ SDOSDI+(HIGH/LO) CLK_O+ SDI-(HIGH/LO) CLK_OCLK_I+ CLK_ILVSS LVDD
20ohms 1 0ohms
R204 R211
SYNC_I+(M/S)
3 1 2
A A A
CS1
J33
CONVST1
12 11 10 9 8 7 6 5 4 3 2 1
AVDD(REF)
LAT Y/N
AVSS(REF)
CLK I/E
24 23 22 21 20 19 18 17 16 15 14 13
37 38 39 40 41 42 43 44 45 46 47 48
VCC3.3
JUMPERX3P
3 1 2
MODE C/D
CONVST
REFIN LAT Y/N_A
10uF
C1 C3 C4 R1 + R2 0ohms 0.01uF C93

1% 0ohms 1%
1uF
BYTE
PD
CS
REFM
REFM
NAP
BUS_BUSY1 49.9ohms TP1 TP105 49.9ohms BUSY1
TP7 TP105 RD
REFIN REFOUT NC AVDD
BUS_BUSY RD BUSY BVSS
J41
R17 R18
A
TP2 TP105SYNC_O1+
AVSS(REF)
AVDD(REF)
LAT Y/N
REFM
REFM
INP1 INM1 VCC3.3 JUMPERX3P

3 1 2
BVDD
NAP
INP INM AVSS(IN) AVDD(IN) AVDD(COMP) PBKG(DIG)
J34
BYTE
VA VA
7X7 48RGZ SINGLE GND DUT10

A
SYNC_O+ SYNC_OSDO+ SDOCLK_O+
100ohms SYNC_O11%
SDI+(HIGH/LO)
SYNC_I+(M/S)
SDI-(HIGH/LO)
SYNC_I-(M/S)
CSTART+
CSTART-
AVSS(COMP) DVSS DVDD PBKG(ANA)
CLK_OCLK_I+ CLK_ILVSS LVDD
100ohms 1% VA CLK_O1+ 100ohms CLK_O11%
R29
SDO1+ SDO1-
R27
VCC3.3
JUMPERX3P
3 1 2
SDI+(HIGH/LO)
J35
PD
SYNC_I+(M/S)
PBKG(DIG)
CSTART+
CLK_I+
CLK_I-
1pF 100ohms 1%
VCC3.3
JUMPERX3P
3 1 2
J36
NAP
C330
100ohms 1pF 1%
R58
TP105 TP115 TP105 TP116
CLK_I+ SDI-
VA
13 14 15 16 17 18 19 20 21 22 23 24
TP105 TP30
A
C328 R61
VCC3.3 JUMPERX3P
3 1 2
1pF MODE C/D
100ohms 1%
TP105 TP117 TP105 TP118
SDI+ SYNC_I-
TP105 TP31
A
J30
TP105 TP8
A
C329 R57
1pF
100ohms 1%
TP105 TP121 TP105 TP122
SYNC_I+ CSTART1-
TP105 TP29
A
CSTART1+
0.0022uF
0.0039uF
C27 C24
A
0.0039uF
C28 C32
A
0.022uF
C31
A
0.001uF
VA 0.0039uF 0.022uF
VA
BVDD 0.001uF
C26 C23
0.001uF
A
C5
A
0.0022uF
VA
VA
VA
VA
C30 C25
0.0039uF
A
C7 C22
A
0.1uF this value has to be changed to 4.7u
A
EXAS INSTRUMENTS TSEMICONDUCTOR OPERATIONS
SCALE CODE IDENTITY NUMBER
SHEET @REV C N SIZE @EDGE_NUMBER REV 01 07
01295
H=4ND; V=4LA
DVSS
LVSS
DVDD
C335 R62
CSTART-
PBKG(ANA)
SDI-(HIGH/LO)
SYNC_I-(M/S)
TP105 TP113 TP105 TP114
CLK_I-
TP105 TP33
1 2 3 4 5 6 7 8 9 10 11 12
CS
PD
AVSS
BVDD
BYTE
DUT12
CLK I/E
CONVST
R28
MODE C/D
0F VA
C
REFM NC AVDD AVSS INP INM
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REFOUT
AVSS(IN) AVDD(IN) AVDD(COMP) AVSS(COMP)
25 26 27 28 29 30 31 32 33 34 35 36
25 26 27 28 29 30 31 32 33 34 35 36
SYNC_I-(M/S)
VCC3.3
JUMPERX3P
J197 J190
1 1
INM1 0ohms VA BYTE

A
BUS_BUSY RD BUSY BVSS BVDD SYNC_O+ SYNC_OSDO+ SDOCLK_O+ CLK_OLVDD
48PIN,QFP,OZTEK
DUT9
37 38 39 40 41 42 43 44 45 46 47 48
20ohms
R210
MODE C/D
CONVST
REFIN
BUS_BUSY
CS
12 11 10 9 8 7 6 5 4 3 2 1
J32
4
REF_5V 1 2 3 4
3
U10
NC NC VREF NC
NC +Vin EN GND
C86 C80
A
0.1uF 0.001uF
8 7 6 5
1Kohms
R60
1%
C85
1uF
A
VRE4141K
1Kohms
R67
+
REF_DC
OPV0.1uF
OPV+ 0.1uF
1Kohms 1%
A
R59
C91
A
10uF 1uF
A
C84 C89 0.1uF

A
C60
A
C59 C35
A
0F
0ohms
A
R43
49.9ohms OPV+ 7
V+
R23
8
C341 U4
6
Ccomp
2 REF_DC 3
+ V-
R82
0ohms DC
+
DIS
0F
AD8021AR
LOG REF
0ohms
A
R176 R186
49.9ohms OPV+ 7
V+
R173
8
C230 C228 C229 0.1uF

10uF 1uF
A A A
0F
R184
A
J60 1
A
0ohms
J59 1
49.9ohms DC OPV-
R175
C344
0F
OPV0.1uF
OPV+ 0.1uF
C346
A
C345
A
R185
J61 1 J66 1
0ohms
OPV0.1uF
OPV+ 0.1uF
C62
A
C61
A
OPV0.1uF
OPV+ 0.1uF
C342 C347
A
C348
A
0ohms
A
R181
49.9ohms OPV+ 7
V+
R172
8
OPV0.1uF
OPV+ 0.1uF
0ohms
A
R41
49.9ohms OPV+ 7
V+
R21
8
R182
A
0ohms
A
J57 1
49.9ohms 4 1 5 C343 DC 0F OPV-
R174
V-
0F
J67 1
LOG REF
J52 GND
Ccomp
C33
1 0ohms
R189
0ohms
R191
DIS
C64
C63
0ohms
R177
LOG REF
V-
OPV-
J53 GND
1 5
0ohms
R180
0F
Ccomp
1 0ohms
R190
0ohms
R192
DIS
C37
1 5
0ohms
2 3
U124
6 INMB
AD8021AR
2 3
U123
6
AD8021AR
INPB
R49
A
J24 1
A
LOG REF
J6 GND
+ V-
Ccomp
1 0ohms 0ohms
R47
0ohms
R34
DIS
0ohms
R42
B
REF_REFIN 0ohms
+
2 3
U6
6 INMA REF_5V 1 2 3 4
NC +Vin EN GND
AD8021AR
U7
NC NC VREF NC
J27 1
49.9ohms DC OPV-
R70
C38
0F
1 5
C46 C6
A
0.1uF 0.001uF
8 7 6 5
C45
1uF
A
VRE4141K
1Kohms
R66 R64
A
R75
REFIN
C92 C83 C90 0.1uF

10uF 1uF
A A A
R74
J25 1 J18 1
0.1uF
0.1uF
0ohms
0ohms
R73
OPV-
OPV+
1Kohms 1%
C87
A
C88 C81
A
C34
0F 0ohms
A
0F
R38 R39 R35
49.9ohms OPV+ 7
V+
R22
8
0ohms
A
R65
49.9ohms OPV+ 7
V+
R56
8
DIS
0ohms 1 0ohms
Ccomp
R50
A
J19 1
A
0ohms
J26 1
49.9ohms 4 1 5 C36 DC 0F OPV-
R69
LOG REF
J7 GND
V-
V-
C82
0F
LOG REF
1 5
Ccomp
R48
U5
6 INPA REF_REFIN
2 3
U9
6
0ohms
AD8021AR
AD8021AR
0ohms
R72
REFIN
A
CODE IDENTITY NUMBER
DIS

SCALE
OPV-
01295
H=4ND; V=4LA
4
TP105 TP49
A
3
SDO+
2
VCC3.3 CLK_I VCC3.3 100ohms 1%
TP105 TP124 TP105 TP123
C326
1pF
100ohms SDO- 1% SYNC_O+

A
R165
TP105 TP129 TP105 TP131 TP105 TP48

A
C340
SYNC_O100ohms 1pF VCC3.3 1%
R160
VCC3.3 VCC3.3
C9
A
C8 C11 C10
VCC3.3 COA
0.001uF 0.001uF 0.001uF 0.001uF
R63
CO+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
U3
DI+ DIGND LCI+ LCIGND CO_EN Vcc GND Vcc Vcc GND GND EN COCO+ Vcc LVI MCIMCI+ GND DCO DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC3.3 CLK_O+ CLK_OA
R162
C323
1pF
TP105 TP128 TP105 TP126
TP105 TP42
A A
R20 R19 R3 R4 R5 R6 R7 R8 R9 R10
49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 CLK_I
VCC3.3
VCC3.3
C17
A
C16 C19 C18 C21 C20
0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF
1 2 3 4 5 6 7 8 9 10 11 12
U1
VDDREF REFCLK VDDP GNDP GND LEADLAG GNDPA VDDPA VDDPD STOPB PWRDNB P0 P1 VDDO GNDO CLKOUT NC GNDO VDDO MULT0 MULT1 P2
1
24 23 22 21 20 19 18 17 16 15 14 13 VCC3.3 VCC3.3
A A
35.7ohms
R30
CLK_IB
DLYCTRL CLKOUTB
A VCC3.3
JUMPERX3P VCC3.3
3 1 2 A
J2 VCC3.3
JUMPERX3P VCC3.3 3 J4
1 2 A
CDCF5801DBQ
VCC3.3
U126
OE 19
A
100ohms
SN65LVDS152DA
JUMPERX3P
3 1 2
C365C357
1uF CLK_IA
20 Vcc 0.1uF GND 10
U127 R193
DIR 1 A1 2 A2 A3 A4 A5 A6 A7 A8 3 4 5 6 7 8 9
G3 3EN1[BA] 3EN2[AB] 1 2
18 B1 17 16 15 14 13 12 11 CSTART_IN3
J187
A 49.9ohms CSTART3
CO+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK_IB
U2
DI+ DIGND LCI+ LCIGND CO_EN Vcc GND Vcc Vcc GND GND EN COCO+ Vcc LVI MCIMCI+ GND DCO DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
COSYNC_O+
A
SYNC_O-
R161 C322 100ohms

1% 1pF VCC3.3 VCC3.3
A
VCC3.3
C13
A
C12 C15 C14
0.001uF 0.001uF 0.001uF 0.001uF
VCC3.3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC3.3
CLK_O+
R200 49.9ohms CS3 R198 49.9ohms CSTART2 R194 CS2 49.9ohms R197 49.9ohms CSTART1 R195 CS1 49.9ohms R199
RD 49.9ohms
A
R163 C339 R11 R12 R13 R14 R15 R16
B2 CS_IN3 B3 CSTART_IN2 B4 CS_IN2 B5 CSTART_IN1 B6 CS_IN1 B7 RD_IN B8
1pF 100ohms 1% CLK_OA
SN74AHC245DW
49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms 49.9ohms
D10 D11 D12 D13 D14 D15
VCC3.3
U127
OE 19
A
C366C358
1uF
20 Vcc 0.1uF GND 10
U126
A
DIR 1 A1 2 A2 A3 A4 A5 A6 A7 A8 3 4 5 6 7 8 9
49.9ohms CSTART4 CS4 49.9ohms
R196
G3 3EN1[BA] 3EN2[AB] 1 2
18 B1 17 16 15 14 13 12 11 B2 B3 B4 B5 B6 B7 B8 CSTART_IN4 CS_IN4
R201
SN65LVDS152DA
SN74AHC245DW
CSTART1+ 100ohms 1% SYNC_I+ 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 SN75LVDS389DBT CSTART1SYNC_I100ohms 1% SDI+ 100ohms SDI1%
R166
0.0039uF
0.0022uF
VCC3.3
C311C310C460
0.001uF
A A
VCC3.3 VCC3.3 CSTART1 SYNC_I SDI CLK_IA VCC3.3 CSTART2 CSTART3 CSTART4 VCC3.3
J220
0.0022uF
VCC3.3 0.0039uF
C79 C78 C462

0.001uF
A
0.0039uF
0.0022uF
VCC3.3
VCC3.3
A
J222
0.001uF
100ohms 1% CSTART4-
R299
R229
J221
C321C320 C461
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
U125
R167
1Kohms CONVST1
R215
JUMPERX3P
3 1 2
R168
CSTART1 J68
1Kohms CONVST4
R224
JUMPERX3P
3 1 2
CSTART1 J219 0
100ohms CLK_I1%
R169
CLK_I+
R214
CSTART4 0
CSTART4 J84
1Kohms
VCC3.3
100ohms CSTART21%
R171
CSTART2+
49.9ohms 1%
R296
R225
VCC3.3 49.9ohms 1% 1Kohms CONVST3 CSTART2 CSTART3 0
R297
1Kohms
100ohms CSTART31% CSTART4+
R170
CSTART3+
1Kohms CONVST2
R228
JUMPERX3P
3 1 2
R226
JUMPERX3P
3 1 2
CSTART2
J83
J85
CSTART3
A
CODE IDENTITY NUMBER
1Kohms
R227
1Kohms
VCC3.3
49.9ohms 1%
R295
VCC3.3
49.9ohms 1%
R298

SCALE
01295
H=4ND; V=4LA
P5 1 2 P2PIN MC 1,5/2-G-5,08 2
R53 CR1 LED3
348ohms
C53
700H
L2
1
+
VA
10uF
C56
A
10uF
C70
1uF
A
2
A
700H
L5
1
+
REF_5V
C54
A
10uF P4 1 2 P2PIN MC 1,5/2-G-5,08 BVDD
C69
1uF
A
D0 1 J5 D1 3 J5 D2 5 J5 D3 7 J5 D4 9 J5 D5 11 J5 D6 13 J5 D7 15 J5 D8 17 J5 D9 19 J5 D10 21 J5 D11 23 J5 D12 25 J5 D13 27 J5 D14 29 J5 D15 31 CLK_I SDI SYNC_I RD_IN 1 3 5 7 9 11 13 15 17 19 2 4 A 6 8 10 A 12 P8 14 16 18 A 20
J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 J5 33 J5 35 J5 37 J5 39
R55 CR2 LED5
348ohms
C55 C67
10uF 1uF
J5 J5 J5 J5 J5
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
A
P6 1 2 VCC3.3
TSS-110-02-G-D
R52 CR5 LED1
P2PIN MC 1,5/2-G-5,08
348ohms
C58 C73
10uF 1uF
CS_IN1 CSTART_IN1 CS_IN2 CSTART_IN2 CS_IN3 CSTART_IN3 CS_IN4 CSTART_IN4
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 P9 14 16 18 20
A
TSS-110-02-G-D
2.87Kohms
OPV+
1 2 3
MC 1,5/3-G-50
P7
C75
10uF
+
C76
1uF
R51
C74
LED2
CR4
10uF
C77
1uF
OPV-
A
01295
H=4ND; V=4LA
LAT Y/N_B CLK I/E_B MODE C/D NAP
PD VA
C
TP53 BUS_BUSY2 TP105 VCC3.3
3
BYTE CS2
A
CONVST2
AVDD(REF)
LAT Y/N
AVSS(REF)
CLK I/E
MODE C/D
CONVST
24 23 22 21 20 19 18 17 16 15 14 13
INPB J142 GND
20ohms 1 0ohms J200 J189
R277
37 38 39 40 41 42 43 44 45 46 47 48
REFIN INP2
10uF
C373C376 C379 R230 + R233 0.01uF 0ohms

1% 0ohms 1% 0F
A
1uF
BYTE
REFM
REFM
NAP
PD
CS
12 11 10 9 8 7 6 5 4 3 2 1
REFIN REFOUT NC AVDD AVSS INP INM AVSS(IN) AVDD(IN) AVDD(COMP) PBKG(DIG)
BUS_BUSY RD BUSY BVSS BVDD SYNC_O+ SYNC_OSDO+ SDOCLK_O+
49.9ohmsTP79 49.9ohms
R242 R240
A
TP105 BUSY2 TP77 TP105 SYNC_O2+ J180
R278
20ohms 1 0ohms
J2081 J211 1
INM2
DUT11
1 1
C424
1 2
BUS_BUSY1 4
VA
A
7X7 48RGZ SINGLE DUT13 GND
R276 R275
INP2 INM2 VA VA
BVDD
100ohms SYNC_O21%
R248
JUMPER4P,THRU
INMB J141 GND
SDI+(HIGH/LO)
SYNC_I+(M/S)
SDI-(HIGH/LO)
SYNC_I-(M/S)
J202 J192
1 1
A
R306
A
0ohms
CSTART+
CSTART-
AVSS(COMP) DVSS DVDD PBKG(ANA)
CLK_OCLK_I+ CLK_ILVSS LVDD
100ohms 1% VA
R250
SDO2+ SDO2CLK_O2+
B
A
100ohms CLK_O21%
A
25 26 27 28 29 30 31 32 33 34 35 36
R252
C441 R262
VA
TP105 TP109 TP105 TP110
CLK_O1-
TP105 TP57
1pF 100ohms 1%
C442 R263
0.0022uF 0.0039uF 0.0039uF 0.0022uF VA VA VA 0.022uF VA
TP105 TP108 TP105 TP107
CLK_O1+ SDO1-
TP105 TP56
A
C411C404
A
C410C394
A
C420
A
0.001uF
0.0039uF
A
C400 C406
1pF 100ohms 1% TP105 TP55

A
C437 R261
TP105 TP112 TP105 TP111
SDO1+ SYNC_O1-
TP105 TP59
A
1pF 100ohms 1%
VA 0.0039uF 0.022uF
VA
BVDD 0.001uF
C398C392
0.001uF
A
C382
A
C384C390
A
C443 R264
1pF
TP105 TP120 TP105 TP119
SYNC_O1+ CSTART2-
TP105 TP58
A
0.1uF this value has to be changed to 4.7u
100ohms 1%
CSTART2+
A
01295
H=4ND; V=4LA
D
LAT Y/N_B CLK I/E_B MODE C/D NAP
PD VA CS3 BYTE
A
CONVST3 BUS_BUSY3
TP61 TP105
AVDD(REF)
LAT Y/N
AVSS(REF)
CLK I/E
MODE C/D
CONVST
24 23 22 21 20 19 18 17 16 15 14 13
37 38 39 40 41 42 43 44 45 46 47 48
REFIN
10uF
C374C378C381 R231 + R234 0ohms 0.01uF C425

1% 0ohms 1%
1uF
12 11 10 9 8 7 6 5 4 3 2 1
BYTE
REFM
REFM
NAP
PD
VCC3.3 49.9ohms 49.9ohms TP105 TP78

3
CS
R244 R238
A
BUSY3 BVDD
TP75 TP105 SYNC_O3+
J181
1 2
BUS_BUSY2 4
DUT10
VA 0F
R269
INPA J145 GND 20ohms 1 0ohms
INP3 INM3
R268
SYNC_I+(M/S)
INMA J146 GND
20ohms 1 0ohms
R271
J2051 J2061
INM3
SYNC_I-(M/S)
J198 J191
1 1
INP3
VA VA

A
100ohms SYNC_O31% SDO3+
R254
JUMPER4P,THRU
100ohms SDO31% VA CLK_O3+ 100ohms CLK_O31% TP105 TP93 TP105 TP94 CLK_O2-
R256
J196 J194
R305
A A
0ohms
A A A
25 26 27 28 29 30 31 32 33 34 35 36
R270
R258
1 1
TP105 TP67
A
R251 C438
TP105 TP63
A
1pF 100ohms 1%
R249 C447
VA 0.0039uF VA 0.0039uF VA 0.022uF VA
TP105 TP85 TP105 TP86
CLK_O2+ SDO2-
VA
TP105 TP64
A
1pF 100ohms 1% 0.0022uF 0.0022uF
C413C405
A
C412C396
A
C419
A
0.001uF
C402C408
0.0039uF
A
R247 C446
TP105 TP89 TP105 TP90
SDO2+ SYNC_O2-
TP105 TP65
A
1pF 100ohms 1%
VA 0.0039uF 0.022uF
VA
BVDD 0.001uF
R265 C444
1pF 0.1uF this value has to be changed to 4.7u
TP105 TP99 TP105 TP100
SYNC_O2+ CSTART3-
TP105 TP62
A
C399C393
0.001uF
A
C383
A
C386C389
A
100ohms 1%
CSTART3+
A
01295
H=4ND; V=4LA
D
0.0022uF 0.0039uF
C415C407
A
0.0039uF
C414C397
A
0.022uF
C421
A
0.0022uF
VA
VA
VA 0.001uF
VA
LAT Y/N_B CLK I/E_B TP105 TP68

A
C403C409
0.0039uF
A
MODE C/D NAP
VA 0.0039uF 0.022uF
VA
BVDD 0.001uF
PD 0.1uF this value has to be changed to 4.7u VA CONVST4 12 11 10 9 8 7 6 5 4 3 2 1

A
C401C395
0.001uF
A
C385
A
C388C391
A
BYTE
CS4
AVDD(REF)
LAT Y/N
AVSS(REF)
CLK I/E
MODE C/D
CONVST
24 23 22 21 20 19 18 17 16 15 14 13
37 38 39 40 41 42 43 44 45 46 47 48
REFIN
10uF
C375C377C380 R232 + R235 0ohms 0.01uF C426

0F
A A
1uF
TP66 TP105 TP74 TP105 49.9ohms VCC3.3

3
BYTE
REFM
REFM
NAP
PD
1% 0ohms 1%
CS
R236
DUT13
VA INP4 INM4 INPB J144 GND 20ohms 1 0ohms J201 J193
49.9ohms BUSY4 TP76 TP105 R239 SYNC_O+ BVDD 100ohms 1% SYNC_OSDO+
J182
1 2
BUS_BUSY3 4
R259
JUMPER4P,THRU
R273
SYNC_I+(M/S)
R272
20ohms 1 0ohms
J2091 J2101
INM4
SYNC_I-(M/S)
1 1
INP4
VA VA

A
100ohms SDO1% VA CLK_O+ 100ohms CLK_O1% CLK_O3-
R266
INMB J143 GND
R280
J203 J195
1 1
A
R304
A
0ohms
A A
25 26 27 28 29 30 31 32 33 34 35 36
R274
R260
C440 R257
VA
1pF 100ohms 1%
TP105 TP83 TP105 TP84
TP105 TP70
A
CLK_O3+ SDO3-
C439 R255
1pF 100ohms 1%
TP105 TP87 TP105 TP88
TP105 TP71
A
SDO3+ SYNC_O3-
C448 R253
1pF 100ohms 1%
TP105 TP91 TP105 TP92
TP105 TP72
A
SYNC_O3+ CSTART4TP105 TP73 CSTART4+

A
C445 R246
1pF
100ohms 1%
TP105 TP98 TP105 TP97
A
01295
H=4ND; V=4LA
www.ti.com
Daisy Chain Board Layout
A.2
Daisy Chain Board Layout

The daisy chain board layout is affixed to this page.
26
GND GND GND GND GND
GND
GND
GND
1
GND GND GND
1
5
2 1
1
4 3
2 1
2 1
2 1
1
1 2 1 2 1 2 GND GND GND 2 1
1 2
GND
2 1
1 2 3
GND
6 7 8
2 1
2 1
2 1
2 1 2
1 2
1 2
2 2 1
2
1
1 2
2
1 1 1 1 1 1
1
1 2 1 2 1
1 1 2 1 2
1 2 2 1 1 2
1 2
1 2
1 2 1 2
3 2 1
1 2 1 2
1 2
1 2 1 2 1
1 2
1 2
1 2 1 2 1
1 2
4 3 2 1
4 3 2 1
4 3 2 1
3 2 1
2 1 2 2 1 1 2 1 2
2
1 2 2 1 1 2 1 2 1 2 2 1 2
6 7 8
20
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1
1 2
1 2
2 1
18 16 14 12 10 8
1
1 2 2 1 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2
5 6 7 8
5 6 7 8
5 6 7 8
6 7 8
GND
GND
2 2
GND
GND
GND
GND
1
GND
GND
1
1 2 2 1
1
GND GND GND GND
1
GND
1
GND GND
GND
1 1 1 1 1 1 1
6 4 2
1 1
1 1 2 3 4 5 6 7 8 9
2 1
1
2 1 2
2 1
2
1
10
2 1 2 1
1 2
1 2
1
2 1
2
1 2
1
2
2
20 19 18 17 16 15 14 13 12 11
1
2 1
40 38 36
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
1 1
1 1
1
2 1
2
GND
2 1
GND
1 2
1 2
1 2
1 1 1
2 2 1
1 1 1
2 1 1
1
1
1
34
1
1
2 2 1 1
1
1 2
1
32 30 28
1 2
1 2
1 2 1 1 1
2 1 2
1 2
1
2 1
1 1
2 2 1 2 1 2 1
1
2 1
26 24
1 2
22
1 2
1 1
1 1
1 1
1 1
2
1 1
20
1 2
1 2 3 4
1 2
8 7 6 5
18
1
1
1 3
1 1
4
1 2
1
16 14
12 10 8 6
2 2
1 1 2 1
3 4 1 2
4
2
5 6 7 8
4 3 2 1
1 1
1 2
1 2
1 1 1 1 1
1 1 1
1 1
2 1 2
1
1 2
2
1 2
1
1 2
1 1 2
2 1
1
1
2
1
2 1 2
1
1 2 1 2 1 2
2
13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1
1 1
1 2
1
1 2
1
1 2
2 1
1 1 1 2
1
2
2 1
2 1
1 1
GND
1 2
1 2
1 2
2 1
3
1 2
3
1 2
3
1 2
3
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 1
2 1
2
4 3 4 3 4 3
6 5 6 5 6 5
8 7 8 7 8 7
GND
2
1
10 9 10 9 10 9
12 11 12 11 12 11
14 13 14 13 14 13
16 15 16 15 16 15
18 17 18 17 18 17
20 19 20 19 20 19
3 1 1 1 1 1 1 3
2
1
2 1 1 1 1 1 1 1 2
1
GND
GND
2 1
2 1
2 1
2 1
GND
GND
1 GND GND
2 1 2 1 2 1 2 1
GND
GND
1
GND GND
1
GND GND GND
1
GND
1
GND GND
www.ti.com
Daisy Chain Board Photograph
A.3
Daisy Chain Board Photograph
27
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Using ADS8410/13 in Daisy-Chain Mode: Application Report

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Application Report

SLAA296 May 2006

Using ADS8410/13 in Daisy-Chain Mode

SLAA296 May 2006 Submit Documentation Feedback

Using ADS8410/13 in Daisy-Chain Mode

Description of the Device

Using ADS8410/13 in Daisy-Chain Mode

SLAA296 May 2006 Submit Documentation Feedback

Definition of Daisy Chain

Definition of Daisy Chain

Figure 1. Three Devices in Daisy Chain

SLAA296 May 2006 Submit Documentation Feedback

Using ADS8410/13 in Daisy-Chain Mode

VDD LAT Y/N CONVST CSZ

Device #1 SDI SDO

Device #2 SDI SDO CLK_O BUS_BUSY

Device #3 SDI SDO

Device #4 SDI SDO

SYNC_I SYNC_O CLK_I RD CLK_O BUS_BUSY

SYNC_I SYNC_O CLK_I RD

SYNC_I SYNC_O CLK_I RD CLK_O BUS_BUSY

SYNC_I SYNC_O CLK_I RD CLK_O BUS_BUSY

Separate CS , CONVST , CSTART

Figure 2. Four Devices in Daisy-Chain Mode

Timing Timing Requirements

Using ADS8410/13 in Daisy-Chain Mode

SLAA296 May 2006 Submit Documentation Feedback

Delay time, CSTART rising edge to sample start

Delay time, CSTART falling edge to conversion start +VBD = 5 V

7.5 15.5 16.5

Delay time, CSTART falling edge to busy high

Sample and Convert

SLAA296 May 2006 Submit Documentation Feedback

Using ADS8410/13 in Daisy-Chain Mode

Data Read Operation

Using ADS8410/13 in Daisy-Chain Mode

SLAA296 May 2006 Submit Documentation Feedback

SYNC_O CLK_O 1F 1R 2R 18F 18R

SDO D15 BUS BUSY D14 D0

SLAA296 May 2006 Submit Documentation Feedback

Using ADS8410/13 in Daisy-Chain Mode

td13 td8 BUSY

SYNC_O td14 SDO_O MSB MSB - 1

Using ADS8410/13 in Daisy-Chain Mode

SLAA296 May 2006 Submit Documentation Feedback

RD_REQ (Int) td11 BUSY td10 BUS_BUSY O/P

0R CLK_O td12 SYNC_O

td14 SDO_O MSB MSB 1

Figure 7. Start of Data Read Cycle With End of Conversion

BUS_BUSY td15 SYNC_O

td16 SDO LSB 1 LSB

Figure 8. Data Read Cycle End With MODE C/D = 0

SLAA296 May 2006 Submit Documentation Feedback

Using ADS8410/13 in Daisy-Chain Mode

Timing Diagrams for Daisy-Chain Operation

See Figure 6 for details CS tw5 RD #1 BUS_BUSY #n (Last device) BUS_BUSY #1 RD #2

16Bit Data nth conversion See Figure 12 for details

Figure 9. Data Read Operation for Devices in Daisy-Chain Mode

Data Read Operation