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Design and Simulation of UART Serial Communication Module Based On VHDL

The document describes a VHDL implementation of a UART serial communication module. It includes three key components: a baud rate generator that controls timing, a transmitter that converts parallel to serial data, and a receiver that converts serial to parallel data. The UART module was designed and simulated using Xilinx tools and is meant to integrate as a core component for data transmission in FPGAs and system on a chip designs.

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John Ramarao
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283 views

Design and Simulation of UART Serial Communication Module Based On VHDL

The document describes a VHDL implementation of a UART serial communication module. It includes three key components: a baud rate generator that controls timing, a transmitter that converts parallel to serial data, and a receiver that converts serial to parallel data. The UART module was designed and simulated using Xilinx tools and is meant to integrate as a core component for data transmission in FPGAs and system on a chip designs.

Uploaded by

John Ramarao
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Design and Simulation of UART Serial Communication Module Based on VHDL Abstract UART (Universal Asynchronous Receiver Transmitter)

is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Xilinx 12.1i are completely consistent with the UART protocol. Block diagram:

Fig. 1 UART simplified block diagram Baud-rate generator BRG The UART module includes a dedicated 16-bit baud rate generator with a prescaler. The UxBRG register controls the period of a free-running 16-bit timer:

the value of the UxBRG register for a specified baud rate is given by

UART transmitter The UART transmitter block diagram is shown in Fig. 2. The heart of the transmitter is the transmit shift register UxTSR where parallel data (9-bit word) are converted to serial data sequences. The shift register obtains its data from the transmit FIFO buffer, TxTXREG. The write-only UxTXREG register is loaded with data by the user software. The UxTXREG is not loaded until the STOP bit has been transmitted from the previous load. As soos as the STOP bit is transmitted, the UxTSR is loaded with new data from the UxTXREG register (if available).

Fig. 2 UART transmitter functional block diagram UART receiver The UART receiver functional block diagram is shown in Fig. 3 The heart of the receiver is the receive shift register UxRSR where a serial sequence is converted to a parallel word (9-bit word). After sampling the UxRX pin for the STOP bit, the received data in UxRSR are transferred to the receive FIFO buffer, if it is empty.

Fig. 3 UART receiver functional block diagram. The data on the UxRX pin are sampled three times by a majority detect circuit to determine if a high or a low level is present at the UxRX pin. Fig. 4 Connection of the UART module to the serial port of a PC via the RS-232 transceiver.

TOOLS REQUIRED:
Simulation: XILINX ISE 12.1 ISIM simulator. Synthesis: XILINX XST synthesis tool. The design is simulated using XILINX 12.1 simulator and device programming is done using XILINX 12.1 XC3S200 SPARTAN3 development board.

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