Programming FPGAs

Dipl.- Ing. Falk Salewski Lehrstuhl Informatik XI RWTH Aachen [email protected] 28.09.2005

Programmable logic basics

You can do a lot with just AND- and OR-gates! In the late 70s systems were built with Standard Discrete Logic (fixed function devices where connected together to implement a system) Idea to reduce space and increase flexibility:
- One chip with two programmable planes - Provide any combination of AND and OR gates, as well as sharing of AND terms across multiple ORs. - Umbrella term: PLDs

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PLD (CPLD & FPGA)

PLDs = Devices which can be re-programmed to implement any function within the devices resources
Field Programmable Gate Array

Complex Programmable Logic Device

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Spartan III
We will use a Spartan-3 XC3S200FT256 FPGA
Clock frequency up to 165MHz (we use 50MHz) Up to 173 user-defined I/O signals 1,2V core Multi-voltage I/O operation: 1,2 to 3,3V 4320 logic cell equivalents internal multipliers and multiplexer Configuration is stored in SRAM (volatile) Configuration can be stored in external Flash

More info: www.xilinx.com or http://direct.xilinx.com/bvdocs/userguides/ug130.pdf

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Spartan-III Architecture

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Spartan-III Architecture (2)

IOB:

Find more in the Spartan-3 data sheet!

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Programming the FPGA

Do we have to program the device on this low level? No! FPGAs can be programmed on a higher level with various Hardware describtion languages (HDL). The Translation to Gate Level is done by tools automatically The most famous HDL: - VHDL, Verilog, SystemC, The different FPGA vendors also offer the possibility to program in schematics. We will use VHDL + Schematic in our designs So you dont have to care about the underlying hardware too much

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VHDL crash course

Basic constructs:
- Entity: specifies inputs and outputs of each module - Architecture: specifies the structure or the behavior of a module - Process: can be used for describtion of the behaviour - Signal: can be understood as physical connections

Controll structures like in other higher programming languages are available.

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VHDL Example
A simple 4bit Timer

clk countervalue(3:0) reset

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VHDL Example (2)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Timer is Port ( clk : in std_logic; reset : in std_logic; countervalue : inout std_logic_vector(3 downto 0)); end Timer; architecture Behavioral of Timer is begin process (clk,reset) begin if reset='1' then countervalue <= "0000"; elsif rising_edge(clk) then countervalue <= countervalue + 1; end if; end process; end Behavioral; Folie 10

entity

architecture process

VHDL Entity
Defines I/O signals of the module:
in read only out write only inout write and read (later also buffer for bidirectional connection)

Possible values of used data type std_logic :

U uninitialized X undefined 0 forcing 0 1 forcing 1 Z high impedance W weak undefined L weak 0 H weak 1 - dont care

Signals can be grouped to vector: std_logic_vector(3 downto 0)

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VHDL Process
Can be used to describe behaviour
process (clk,reset) -- sensitivity list: changing of clk or reset starts process begin if reset='1' then countervalue <= "0000"; -- assign initial value elsif clk='1' and clk'event then -- if rising edge of clk signal then countervalue <= countervalue + 1; -- increment end if; end process;

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VHDL Architecture
architecture Behavioral of Example_Modul is begin process (clk,reset) begin end process; process (clk,reset,in1) begin end process; out <= in1 and in2; end Behavioral;

Process 1 Execution outside process: parallel inside process: sequential Process 2

Process 3

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VHDL sources
Free VHDL Online Tutorial: http://www.aldec.com/Downloads/ The Hamburg VHDL archive http://tech-www.informatik.uni-hamburg.de/vhdl/ VHDL Tutorial Uni Erlangen-Nrnberg http://www.vhdl-online.de/tutorial/ Online Support from the book VHDL Eine Einfhrung http://nirvana.informatik.uni-halle.de/Pearson/

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Starting with Project Navigator

File > New Project (!NO blanks in path allowed!) Project Name = Timer4bit

Press Weiter until the window closes

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Xilinx development environment

Add new module to project Check VHDL Syntax Implement Design Specify module

Create Programming File (later)

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Exercise 1
Implement a 4-bit Timer in VHDL Tips:
- No spaces allowed in path or names! - The following names are not allowed:
4bitTimer Timer-4bit

- The following names are allowed:

Timer_4bit Timer4

Next: Simulation
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Functional Simulation
To simulate a VHDL file, you have to create a testbench
(Project menu > New Source > Test Bench Waveform)

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Modelsim simulator
Click on Simulate Behavioral VHDL Model to start simulation

Simulate Post-Place&Route VHDL Model simulates the behavior of the actual hardware (last step before programming!)

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Exercise 1b
Test your design (counter) with the Simulator (Modelsim)

Next: Connecting to the outside world

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Xilinx development environment (2)

Assign Package Pins

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The 50MHz clock is connected to Pin T9

Assign Pins here

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Xilinx development environment (4)

Assignment Package Pins

Upload program to device

Generate Programming File

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Exercise 1c
Implement a 4bit Timer on the FPGA Use switch3 (BTN3) for reset and switch2 (BTN2) as clock Use 4 LEDs to display timer status Use one LED to display reset signal

What would you do to replace switch2 by a 1Hz clock? Design a clock devider (1/50 000 000)

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Schematic
It is possible to specify the behavior of modules in schematics (low level programming with basic blocks). Schematics are an easy way to connect different modules
- Add new source (choose schematic) - To get the schematic symbols of your modules described in VHDL click on Create Schematic Symbol for each module - You can now connect the modules on the schematic layer - You can use basic blocks like inverter, buffer or clock devider

In a last step the Schematic is tranlated to VHDL automatically

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I/O-marker name connect

Schematic (Example)

Modules from our project (to find them here click Create Schematic Symbol in Project Navigator for each modul)

Standard blocks

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Exercise 2
Import the timer in the schematic editor Use the system clock instead of switch2 now Add a clock devider in the schematic editor (~3Hz clock signal) Use Tools\Check Schematic to check for errors Assignment of package pins must be done again! The schematic editor is useful at the top level of the design

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Sequential and parallel structures

processA: process (clk,reset) variable state: std_logic_vector(1 downto 0); begin if reset = '1' then state := "00"; output <= "0000"; state:= "00"; elsif rising_edge(clk) then case state is when "00" => output <= "1111"; do_it <= '1'; when "01" => output <= "1010"; do_it <= '1'; when "10" => output <= "0101"; do_it <= '1'; when others => output <= "0000"; do_it <= '1'; end case; if done = '1' then state := state + 1; do_it <= '0'; end if; end if; end process; processB: process (clk,reset) variable output_state: std_logic_vector(1 downto 0); begin if reset = '1' then outvector <= "0000"; output_state := "00"; elsif rising_edge(clk) then if do_it = '1' then case output_state is when "00" => display(0) <= '1'; done <= '0'; when "01" => display(1) <= '1'; outvector <= output; when "10" => display(2) <= '1'; done <= '1'; when others => display <= "000"; done <= '0'; end case; output_state := output_state + 1; end if; end if; end process;

Example task: The cyclic sequence 0000,1111, 1010, 0101 should be realised at outvector. before outvector changes: display(0) = 1 while outvector changes: display(1) = 1 after outvector has changed: display(3) = 1 next cycle after outvector has changed: display1..3 = 0 here: reallization with two synchronized processes Alternative: one process (pros/cons?)
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Simulation results

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Functions and Procedures

Suitable for code often used Example function MIN (a, b : integer) return integer is begin if a < b then return a; else return b; end if; end function MIN; Not suitable for (clocked) sequential code!

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Exercise 3: Traffic light

Timer
External Signal

clock

State machine traffic light

reset

red(40%) => yellow(10%) => green(40%) => yellow(10%) => red If reset: blink yellow (~1Hz) for 4 seconds, then start cycle with red The whole cycle should take 3 - 5 seconds Connect the modules in the schematic editor The use of a clock devicer module could be useful
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Exercise 3: Traffic Light

You need: - Describtion development board
(CD Embhard\Data sheets\Spartan-3 Starter Kit)

- Describtion Interface board

(CD Embhard\Data sheets\Spartan-3 Starter Kit)

- Xilinx Project Navigator

(already installed, free download from the web possible)

- VHDL Help sheet

(CD Embhard\Programming Languages\VHDL)

Use the simulator for checking your modules before you download them!
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Exercise 3: Traffic Light

Add the following feature (pedestrian light): External Signal External Signal

S1 S2

WAIT

Wait1 Wait2

WAIT

As soon as S1 has been pressed Wait1 has to blink (~1Hz) until the traffic light is read. It has to be off until S1 is pressed again. As soon as S2 has been pressed Wait2 has to blink (~1Hz) until the traffic light is read. It has to be off until S2 is pressed again.

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Exercise 3: Traffic Light

Which parts of the example have you realised in parallel strucures and which parts in sequential structures? Pros and cons of parallel strucures? Pros and cons of sequential strucures? Find optimal combination!

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Bidirectional Connection
In the case of the microcontroller we could switch a PORT between input and output during operation. In this case we have to realize this functionality manually This can be done in two different ways:
- in schematic - in VHDL

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Bidirectional 8bit Port

AD: buffer std_logic_vector(7 downto 0);

write
AD

var2 var1 var2

write
AD

var2

var1

read

read

Read from Port AD

Write to Port AD

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Using 4x 7-segement block

Segmentdecoder Output 4x output (hex) displayOut(0) displayOut(1) displayOut(2) displayOut(3) Input2 (binary) displayOut(4) Input3 (binary) Input4 (binary) displayOut(5) displayOut(6) SegSelector(0) SegSelector(1)

50-1000Hz

FPGA Pin E14 G13 N15 P15 R16 F13 N16 D14 G14 F14 E13

Input1 (binary)

Tip: use 4x 7-segment block for displaying status of your state machine
More information and the VHDL code on CD

SegSelector(2) SegSelector(3)

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6V

Jumper: M0&M2: offen, Power M1: geschlossen supply for LEDs external connected boards Jumper: to FPGA closed

Programming cable to parallel port

Access to FPGA-Pins
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CAN board