518 Journal of Power Electronics, Vol. 10, No.

5, September 2010
JPE 10-5-9
Direct Digital Control of Single-Phase AC/DC
PWM Converter System
Young Chol Kim

, Lihua Jin

, Jinmok Lee

, and Jaeho Choi

College of Electrical & Computer Engineering, Chungbuk National University, Cheongju, Korea

Automation R&D Center, LS Industrial Systems, Geonggi, Korea

Abstract
This paper presents a new technique for directly designing a linear digital controller for a single-phase pulse width modulation
(PWM) converter systems, based on closed-loop identication. The design procedure consists of three steps. First, obtain a digital
current controller for the inner loop system by using the error space approach, so that the power factor of the supply is close to
one. The outer loop is composed of a voltage controller, a current control loop including a current controller, a PWM converter,
and a capacitor. Then, all the components, except the voltage controller, are identied by a discrete-time equivalent linear model,
using the closed-loop output error (CLOE) method. Based on this equivalent model, a proper digital voltage controller is then
directly designed. It is shown through PSim simulations and experimental results that the proposed method is useful for the
practical design of PWM converter controllers.
Key Words: direct digital control, AC/DC PWM converter, closed-loop identication, characteristic ratio assignment (CRA)
I. INTRODUCTION
PWM AC/DC converters have been widely used for appli-
cations such as PWM inverter fed induction motor drives and
interruptible power supply (UPS) systems. The main objectives
of a PWM AC/DC converter are to regulate the DC voltage
level while maintaining a sinusoidal AC current waveform and
a unity power factor.
For the control of voltage source converters, the current
controlled PWM techniques have been widely used due to
their advantages, such as the control of instantaneous cur-
rent waveforms and high accuracy, peak current protection,
extremely good dynamics, and compensation of effects due to
parameter changes and AC source voltage changes, etc. [1].
Current controlled PWM techniques can be divided into two
groups: linear and nonlinear. The linear controllers include
the ramp comparison current controller [2], the synchronous
vector controller [3], the state feedback controller [4], and the
predictive and dead-beat controllers [5], [6]. The hysteresis
controller [2], the pulse density modulation algorithm [7], and
the neural networks and fuzzy logic based controllers belong to
the nonlinear controller group [8], [9]. Each controller has its
advantages and limitations, but as the trend favors fully digital
control, the methods which allow digital implementation are
preferred, despite some sacrices in accuracy and dynamic
performance. In particular, for low switching frequency ap-
Manuscript received Mar. 25, 2010; revised Jul. 20, 2010

Corresponding Author: [email protected]

Tel: +82-43-261-2475, Chungbuk Natl University

Chungbuk National University, Korea

LS Industrial Systems, Korea

plications in large power systems, such as traction drives,
the digitally implemented cascaded inner/outer structure PI
controllers are recommended [10], [11].
In the cascaded structure of the DC output voltage and AC
input current controllers of a PWM converter are generally
constructed with double feedback loops, which consist of an
inner AC current feedback loop and an outer DC voltage
feedback loop. Each feedback loop is usually designed with
a PI controller. The reference waveform of the AC current is
generated by multiplying the error output of the DC voltage
controller as the amplitude of the AC current waveform with
the unit sinusoidal waveform in phase with the AC line
voltage. Then the AC current controller operates to follow the
reference current waveform not only to meet the sinusoidal
current waveform and unity power factor but also to regulate
the DC voltage. These kinds of current controlled PWM tech-
niques have advantages, such as the control of instantaneous
current waveforms and high accuracy, peak current protection,
extremely good dynamics, and compensation of effects due to
parameter changes and AC source voltage changes, etc. [1],
[11]. However the converter includes a switching component,
which has nonlinear characteristics, and both the inner loop
and the outer loop cannot be handled in a single framework.
It could be modeled in a single nonlinear system using a
power balance, but the small signal model is valid only
around specied operating points [12]. Otherwise, it could be
linearized by using input-output feedback, but the design of
the included PI controllers was not investigated [13].
This paper presents a new technique for designing direct
digital controllers so that they provide good transient re-
Direct Digital Control of Single-Phase AC/DC PWM Converter System 519
sponses for DC voltage regulation under practical severe load
change conditions. The inner current control loop can be
designed using the error-space approach [14] independently
of the outer voltage loop [15]. Then, the whole inner loop
system, including the current controller, can be replaced by an
equivalent transfer function. The inner loop system, from the
right end of the voltage controller to the capacitor, is identied
from the input-output data using the CLOE identication
algorithm presented in [16]. Based on identied linear model

G
o
(z), a voltage controller satisfying the desired time re-
sponse specications is designed, using the w-transform [17],
[18] and the characteristic ratio assignment (CRA) [19]. The
reference transfer function H

(w) that meets the prescribed

time response is preliminarily generated in the w-domain using
the CRA, then this is transformed into the z-domain as H

(z)
so that a controller is obtained directly in the z-domain by
solving the Diophantine equation. A similar approach has been
presented in [20]. However, the method in [20] can not be
referred to the fully direct digital control of a PWM converter
because the design of the inner loop controller is carried out
by an indirect method in the manner that a continuous-time
current controller is rst designed and then converted to a
digital approximation. In this paper, the fully direct digital
design of both the inner and the outer-loop controllers is
considered.
For verication of the proposed control algorithm, a pro-
totype of a 4.5kW single phase PWM converter is tested
considering the application of an urban light railway system.
Through the simulation and experimental results, it is shown
that the proposed method is useful for the practical design of
PWM converter controllers.
This paper is organized as follows. A single-phase AC/DC
PWM converter model is introduced in Section II. In Sec-
tion III, the direct digital controller design method is pre-
sented. The design procedures for the inner current control
and the outer voltage control for a PWM converter system
are presented in Section IV. In Section V, simulation and
experimental results will be followed, as a practical example.
Finally, some conclusions are given in Section VI.
II. PWM CONVERTER MODEL
The conguration of a power circuit for a single-phase
PWM converter model is shown in Fig. 1. Figure 2 shows
the double loop feedback control system, which consists of an
inner AC-current loop and an outer DC-voltage loop.
The current controller C
i
and the voltage controller C
v
are
used to force the input current to follow the referenced current
waveform and to regulate the output voltage even under the
condition of a sudden load change.
In general, the current controller is designed so that the
power factor at the supply terminal is close to one. That is,
it is required that the supply voltage v
s
and the current i
s
be in-phase as close as possible. This means that both the
current loop and the voltage loop cannot be handled in a
single framework because of the nonlinearity due to the 60Hz
modulator. This is the main reason that a simple controller
of the PID type for a PWM converter is difcult to obtain
analytically.
Fig. 1. Typical circuit for a PWM converter.
Fig. 2. Block diagram of the PWM converter control system.
In the next section, the design technique of a direct digital
controller is introduced, which will meet the given time
response specications in a single loop feedback system. This
approach will be used for the digital control problem of the
PWM converter.
III. DIRECT DIGITAL CONTROL WITH TIME RESPONSE
REQUIREMENTS
Consider the discrete-time feedback control system shown
in Fig. 3. A linear time invariant (LTI) plant and an R-S-T
type controller [16] are described by
B
_
z
1
_
A(z
1
)
=
b
1
z
1
+ b
2
z
2
+ + b
n
B
z
n
B
1 + a
1
z
1
+ a
2
z
2
+ + a
n
A
z
n
A
, (1)
S
_
q
1
_
u(k) = R
_
q
1
_
y (k) + T
_
q
1
_
r (k) (2)
where q denotes the shift operator dened by qy(k) := y(k +
1), and
S
_
z
1
_
= 1 + s
1
z
1
+ + s
n
S
z
n
S
,
R
_
z
1
_
= r
0
+ r
1
z
1
+ + r
n
R
z
n
R
, (3)
T
_
z
1
_
= t
0
+ t
1
z
1
+ + r
n
T
z
n
T
.
The closed-loop transfer function is given by
H
_
z
1
_
=
T
_
z
1
_
B
_
z
1
_
A(z
1
) S (z
1
) + B (z
1
) R(z
1
)
=
T
_
z
1
_
B
_
z
1
_
P (z
1
)
. (4)
The characteristic polynomial P
_
z
1
_
is
P
_
z
1
_
= A
_
z
1
_
S
_
z
1
_
+ B
_
z
1
_
R
_
z
1
_
= p
0
+ p
1
z
1
+ + p
n
z
n
. (5)
520 Journal of Power Electronics, Vol. 10, No. 5, September 2010
Fig. 3. Feedback system with R-S-T type controller.
Suppose that the design problem here is to nd a digital
controller R, S, T for the given discrete time response
specications, such as the maximum overshoot and the settling
time limitation.
Applying the model matching method to this problem, it
can be described by
H
_
z
1
_
=
T
_
z
1
_
B
_
z
1
_
P (z
1
)

T
_
z
1
_
B
_
z
1
_
P

(z
1
)
= H

_
z
1
_
. (6)
where H

_
z
1
_
and P

_
z
1
_
are the reference model and
the reference characteristic polynomial, respectively. To pro-
ceed with (6), it is necessary to nd a reference model
H

(z
1
) that satises the time response specications. In
[18], a simple technique for this problem has been proposed.
This method consists of three steps. Firstly, the prospective
closed-loop transfer function H(z
1
) is transformed into the
w-domain by the w-transform. The transformed function is
given by
H (w) =

B (w)
P (w)
=
t
0

n
i=0
b
i
(w + C)
i
(w C)
ni

n
j=0
p
j
(w + C)
j
(w C)
nj
(7)
where C =
2
T
s
.
Here, it is notable that

B(w) is a xed known polynomial
whose coefcients are functions of only B(z
1
) for a given
T(z
1
). The second step is to nd a reference polynomial
P

(w) so that the reference model H

(w) =

B(w)/P

(w)
meets the design specications. Such a reference model can
be easily found by means of the CRA, as presented in [18]. In
the third step, H

(z
1
) is obtained by transforming H

(w)
into the z-domain inversely. Then the controller, S(z
1
) and
R(z
1
) can be determined by solving the following algebraic
equation.
P

_
z
1
_
= A
_
z
1
_
S
_
z
1
_
+ B
_
z
1
_
R
_
z
1
_
= p

0
+ p

1
z
1
+ + p

n
z
n
. (8)
This polynomial equation has a unique solution with a
minimal degree (when A
_
z
1
_
and B
_
z
1
_
do not have
common factors) for n
P
n
A
+ n
B
1, n
R
= n
A
1,
and n
S
= n
B
1.
To achieve zero steady state error to a step reference input,
the overall system must be of Type 1. Then T(z
1
) can be
Fig. 4. Block diagram of the inner loop system.
obtained by
T
_
z
1
_
= t
0
=
P (1)
B (1)
= R(1) . (9)
IV. PWM CONVERTER CONTROL SYSTEM DESIGN
This section describes the design process for the double
loop controller. In the rst step, the inner current controller
is designed, based on the error space approach, independently
of the outer control loop. Subsequently, an equivalent linear
model of the inner loop system, which includes some nonlinear
components, is obtained. After selecting a temporary voltage
controller that makes the overall system stable, the CLOE
identication method is applied to identify the linearized
model from the input-output data. Once the model is identied,
a direct digital voltage controller is designed by using the w-
transform and the CRA method [18].
A. Inner Loop Design
The error-space feedback scheme is a well known state-
feedback method that allows a controller to perfectly track
a non-decaying input, and to reject non-decaying disturbances
such as sinusoidal inputs. Since this method solves the control
problem in the error space, it has robustness because the
error approaches zero against the variation of some parameters
provided that the system keeps stable.
The state equation of the inner loop system in Fig. 4 can
be expressed as
_
x(t) =
R
s
L
s
x(t)
1
L
s
[u(t) v
s
(t)] ,
y (t) = x(t)
(10)
where x(t) = i
s
(t) and u(t) = v
c
(t).
The discrete-time state equations of (10) with a sample time
T
s
are given by
_
x(k + 1) = x(k) + u(k),
y (k) = x(k)
(11)
where
_

_
= e

R
s
L
s
T
s
,
=
1
L
s
_
T
s
0
e

R
s
L
s
t
dt =
1
R
s
_
1 e

R
s
L
s
T
s
_
,
u(k) := [u(k) v
s
(k)] .
(12)
Let the reference input of the current controller be r (k) =
i

s
(k) = I
s
sin (
0
kT
s
). It follows that
(q) r (k) = 0 (13)
where
(q) = q
2
2 cos (
0
T
s
) q + 1. (14)
Direct Digital Control of Single-Phase AC/DC PWM Converter System 521
Letting = cos (
0
T
s
), then (14) is rewritten as
(q) = q
2
2q + 1. (15)
The tracking error is dened as
e (k) := r (k) y (k) = i

s
(k) i
s
(k) . (16)
From (13) and (16), the error is formulated in terms of the
plant state,
(q) e (k) = (q) y (k) = (q) x(k) . (17)
Now, a new state vector and a control input in the error
space are dened as
(k) := (q) x(k) , (18)
(k) := (q) u(k) . (19)
Then (17), (18), and (19) lead to
(q) e (k) = (k) , (20)
(k + 1) = (k) + (k) . (21)
In the derivation of (21), the relation (q) v
s
(k) = 0 is used
as long as v
s
(k) keeps the same frequency as i

s
(k). Equations
(20) and (21) show the overall system in error space. Rewriting
them in the state variable form, they can be described as
z (k + 1) = Fz (k) + G(k) (22)
where z (k) =
_
e (k) e (k + 1) (k)

T
and
F =
_
_
0 1 0
1 2 1
0 0
_
_
, G =
_
_
0
0

_
_
. (23)
It is obvious that {F, G} is controllable. Therefore, there
exists a controller that can assign closed-loop poles to any
desired location. Let the state feedback controller be
(k) = Kz (k) , (24)
where K := [k
1
k
2
k
3
].
From (18), (19) and (24), it is shown that
(q) u(k) + k
3
(q) x(k) = k
1
e (k) k
2
e (k + 1) . (25)
Then (25) can be rearranged as
[u(k) + k
3
x(k)] q
2
2 [u(k) + k
3
x(k)] q
+[u(k) + k
3
x(k)] = (k
1
+ k
2
q)e (k) . (26)
Let us dene
(k) := u(k) + k
3
x(k) . (27)
Using (27), (26) yields
(k) = [2 (k) k
2
e (k) +
1
(k)] q
1
(28)
where

1
(k) = [ (k) k
1
e (k)] q
1
. (29)
Let (k) =
2
(k), from (27), (28), and (29), the control
law is given by

1
(k + 1)

2
(k + 1)

0 1
1 2


1
(k)

2
(k)

k
1
k
2

e (k) , (30)
u(k) =
2
(k) k
3
x(k) . (31)
Fig. 5. Current controller for PWM converter.
A block diagram of the current controller law (30) and (31)
is shown in Fig. 5. The remaining problem is to determine the
controller gain vector K such that it satises the given time
response requirements.
The closed loop dynamics of the current control loop are
determined by combining (30) and (31) with (11) to yield

x(k + 1)

1
(k + 1)

2
(k + 1)

k
3
0
k
1
0 1
k
2
1 2

x(k)

1
(k)

2
(k)

0
k
1
k
2

r (k) +

0
0

v
s
(k) ,
y (k) =

1 0 0

x(k)

1
(k)

2
(k)

(32)
The closed-loop transfer function from r (k) to y (k) is
given by
T
i
(z) =
I
s
(z)
I

s
(z)
=
Y (z)
R(z)
=
(k
2
z + k
1
)
(z)
(33)
where
(z) = z
3
+ (k
3
2) z
2
+ (k
2
2k
3
+2 + 1) z + (k
1
+ k
3
) . (34)
Here, the current controller gain K is easily obtained
from (z)

(z) while the target polynomial

(z) can
be generated by the K-polynomial [18] using the CRA
approach. The denition of the K-polynomial is referred to
the AppendixVI-A.
Remark 1: The design objective of the current control
loop is to make the AC supply voltage and the source current
in phase. In order to accomplish this purpose, the internal
model control (IMC) approach shown in (13) to (24) has been
occupied. In this section, i

s
and v
s
in Fig. 2 have been assumed
to be sinusoidal waves of
0
[rad/sec]. For the cases where
these signals include several harmonics due to distortions and
sags, there may be some error because the IMC here is used
for tracking only one frequency,
0
[rad/sec].
B. Outer Loop Design
In the previous subsection, it was presented that the cur-
rent controller can be designed independently of the voltage
controller. As shown in Fig. 2, two nonlinear components
are included in the outer loop. Since the output voltage must
be kept constant, it is possible to characterize this nonlinear
system by a linear model,

G
0
_
z
1
_
, as shown in Fig. 6.
522 Journal of Power Electronics, Vol. 10, No. 5, September 2010
Fig. 6. An equivalent linearized model of the inner loop system.
Fig. 7. Closed-loop output error (CLOE) identication method
Because the identication should be carried out while the
switching components are in operation, the following closed-
loop identication scheme is utilized.
1) Closed-loop identication: The principles of the closed-
loop identication method are illustrated in Fig. 7.
Let the plant to be identied be

G
o
_
q
1
_
= q
d
B
_
q
1
_
A(q
1
)
= q
d
b
1
q
1
+ + b
n
B
q
n
B
1 + a
1
q
1
+ + a
n
A
q
n
A
. (35)
In Fig. 7, C
k
denotes the voltage controller and the hatted
letters indicate the identied model.
At this point, the controller C
k
is not known yet. Thus,
in order to carry out the closed loop identication, a simple
controller, for example, a proportional controller can be chosen
temporarily. It does no matter what C
k
is chosen provided
that it makes the closed loop system stable, so that the input
and output data of the closed loop operation can be acquired.
In this procedure, a small perturbed test signal should be
injected into either the r or u signal. A pseudo-random binary
sequences (PRBS), r
t
, is added to the reference DC input.
The PRBS is a good test input for identication. Then, the
controller output u
v
and the system output y
v
are measured
to estimate the parameters {A, B}.
Let us dene an unknown parameter vector,
(k) = [a
1
, , a
n
A
, b
1
, , b
n
B
]
T
, (36)
and the vector of the measured data,
(k) = [y
v
(k) , , y
v
(k n
A
+ 1) ,
u
v
(k d) , , u
v
(k d n
B
)]
T
. (37)
Fig. 8. Closed-loop system of the PWM converter.
Then the a priori predicted output is dened by
y
0
v
(k + 1) =

T
(k) (k) . (38)
And the estimated controller output is obtained as
u
v
(k) = C
k
[r (k) y (k)] . (39)
Furthermore, the a priori closed-loop prediction output error
is given by

0
CL
(k + 1) = y
v
(k + 1) y
0
v
(k + 1) , (40)
The parameter adaptation algorithm of the CLOE identi-
cation is given in the following recursive form [16].

0
CL
(k + 1) = y
v
(k + 1)

T
(k) (k)

(k + 1) =

(k) + F (k + 1) (k)
0
CL
(k + 1)
F (k + 1) =
1

F (k)
F(k)(k)
T
(k)F(k)

2
+
T
(k)F(k)(k)

(k) = (k)
Herein, the forgetting factors are given by 0 <
1
1,
0 <
2
2.
As a result, the identied equivalent model

G
0
is obtained.
2) Voltage Controller Design: Based on the identied
model

G
o
_
z
1
_
=

B(z
1
)

A(z
1
)
, a direct digital controller that
satises the transient response specications is designed.
A block diagram of a PWM converter feedback system is
shown in Fig. 8.
The main idea of the direct digital design in [18] is to
extend the continuous time CRA to the discrete time case.
The controller structure of the R-S-T type is considered and
it is assumed that the design objective is to directly nd a
digital controller of xed order that meets certain time and
frequency response requirements.
As explained in Section III, the prospective closed-loop
transfer function H
_
z
1
_
is transformed into the w-domain
by using the w-transformation. After regarding H(w) as a
function of the s-domain H(s), a reference transfer function
associated with a xed numerator

B (w) is composed by
using the CRA technique [21], so that it satises the design
specications. It is shown in [18] that the mapping error of
the w-transform between the s-and w-domains is less than
3% for |w| 0.6/T
s
and |s| 0.6/T
s
. In other words,
H(w) H(s) is concluded if a sampling time T
s
is selected
so that all the poles and zeros of H(w) lie in the region of
|w| 0.6/T
s
in left half plane of the w-domain. Once such
a reference model H

(w) =

B(w)/P

(w) is obtained, then

Direct Digital Control of Single-Phase AC/DC PWM Converter System 523
TABLE I
THE PARAMETERS OF THE MODEL
System parameters values
Input voltage (V
s
) 150V (peak), 60Hz
Output voltage (V
DC
) 200 300V
Switching frequency 540Hz
Sampling frequency 1080Hz
Resistor 0.08
Inductor (L
s
) 1mH
Capacitor (C
DC
) 6000F
Load (R
L
) 12/24
P

(w) is transformed into the z-domain using the inverse w-

transformation, which results in P

_
z
1
_
.
P

_
z
1
_
= 1 + p

1
z
1
+ + p

n
z
n
. (41)
Solving the following Diophantine equation with P

_
z
1
_
from above, the digital controller of (3) is determined.
P

_
z
1
_
=

A
_
z
1
_
S
_
z
1
_
+

B
_
z
1
_
R
_
z
1
_
. (42)
V. SIMULATION AND EXPERIMENTAL RESULTS
Both simulation and experimental demonstrations have been
carried out for a single-phase PWM converter model, the
parameters of which are given in Table I. This converter has
been designed as a laboratory model of a AC/DC converter
for using as a high power urban light railway application with
a low switching frequency which has a 8601040V AC input
and a 1600V DC output voltage.
The design specications are as follows:
(i) the maximum settling time of the current loop system
is 10msec,
(ii) the overshoot limitation of the DC output is less than
5%,
(iii) the minimum rising time and the maximum settling
time of the overall system are 20msec and 200msec,
respectively,
(iv) the stability margins are GM 10dB and PM
45deg.
As a simulation tool, the PSiM utility was used. Figure 9
shows the experimental setup of a converter system.
A. Design of the inner loop controller
As described in Section IV-A, in order to design the current
controller gain K using the CRA, it is necessary to make a
reference characteristic polynomial

(z) satisfying a settling

time of 10msec. According to the CRA method in [18], when

1
= 3 and = 3.2 10
3
are selected, such a reference
polynomial in the w-domain is obtained as follows:

(w) = w
3
+2.812510
3
w
2
+2.63710
6
w+8.2410
8
. (43)
The detailed derivation of (43) is referred to Appendix VI-B.
The inverse w-transformed polynomial

(z) is given by

(z) = z
3
1.184z
2
+ 0.4673z 0.00615. (44)
Solving the identity (z)

(z) from (34) and (44), the

current controller gain K is determined by
K = [k
1
k
2
k
3
] = [0.8480 0.8674 1.8196] . (45)
Fig. 9. Experimental setup of the PWM converter.
As a result of (44) and (45), the inner loop control system
has three poles at 0.3947, 0.3947 j3.59 10
6
and a
zero at 0.9776, respectively. It is easy to see from the Bode
plot that the bandwidth of the inner loop system is about
f
BW
= 309Hz. Generally, the sampling frequency can be
chosen by the rule [16], f
s
= (6 25) f
BW
, where f
s
and
f
BW
are the sample frequency and the closed loop system
bandwidth, respectively. Therefore, the sample frequency for
the inner loop system needs to be greater than 1, 854Hz.
However, the sample frequency given in this example is
1, 080Hz which is much lower than the recommended value.
This is a case where the direct digital control prefers to
the digitization approach [16]. This inner loop controller was
simulated using the PSiM toolbox. As shown in Fig. 10, the
controller makes the current i
s
and the supply voltage v
s
be
in phase. The total harmonic distortion (THD) of the current
i
s
obtained at the steady state by this controller was less than
0.45 %. Fig. 11 shows that the current controller accomplishes
perfect tracking within 10msec.
B. Design of the outer loop controller
Before going to design a voltage controller, an equivalent
model of the outer loop has to be identied. To do this,
a proportional voltage controller was temporarily selected.
Using the CLOE identication method described in Section
IV-B2, the linear equivalent model is obtained by

G
_
z
1
_
=
0.04227z
1
1 z
1
. (46)
524 Journal of Power Electronics, Vol. 10, No. 5, September 2010
Fig. 10. The simulation results of the v
s
and i
s
.
Fig. 11. Time responses of the i

s
and i
s
.
A PRBS test signal of 10V for identication was added
to the reference input r (where r = 200V DC), as shown in
Fig. 12-(a). Fig. 12-(b) shows the actual output data and the
estimated output, while the bottom curve shows the residual
which is the difference between the output of the real system
and that of the estimated model.
Fig. 13 shows the proles about how the identied param-
eters in the CLOE algorithm converge.
Since the equivalent model (46) is of the rst order, a RST
type PI controller is considered for an outer loop controller.
Similar to the design of the inner loop controller, the reference
characteristic polynomial P

(z) below is obtained, so that it

meets a settling time of 200msec and no overshoot.
P

(z) = z
2
1.9273z + 0.9286. (47)
By solving (42) with (47), the voltage controller is
R
_
z
1
_
= 1.7205 1.6893z
1
,
S
_
z
1
_
= 1 z
1
, (48)
T
_
z
1
_
= 0.0313.
The step and frequency responses of the closed-loop system
are shown in Figs. 14 and 15, respectively.
Fig. 12. Time response of the estimated output.
Fig. 13. Convergence of the identied parameters.
Fig. 14. Step response of the closed-loop system.
The overall system results in no overshoot, a rising time
of 84msec and a settling time of 145msec. Also, both the
Direct Digital Control of Single-Phase AC/DC PWM Converter System 525
Fig. 15. Bode diagram of the closed-loop system.
Fig. 16. Simulated and experimental input and output voltages.
gain and the phase margins for stability are 69.3dB and ,
respectively. From these results, it has been veried that the
time and stability performances are satisfactory.
Figure 16 shows both the simulation and experimental
results for the case where the reference voltage is changed
from 200V DC to 300V DC at t = 2sec. Both responses
coincide with each other and have almost no overshoot.
The time domain performance, subject to abrupt load
changes, was experimentally examined. When the load is
changed from no load to a half load ar t = 1.25sec, from
a half to full load at t = 2.3sec, and from full load to no load
at t = 3.3sec, the output voltage consistently remains the same
as the reference voltage, as shown in Fig. 17. In this case, the
maximum overshoot is less than 4.6%. Figure 18 shows the
experimental results of v
s
and i
s
which correspond to those
of Fig. 10. It is seen that these experimental curves are very
similar to the simulated ones.
VI. CONCLUSION
In this paper, a direct digital controller design method
for a single-phase AC/DC PWM converter system, using
Fig. 17. The output voltages with respect to the load changes.
Fig. 18. The experimental results of the v
s
and i
s
corresponding to
Fig. 10.
closed-loop identication, has been proposed. An error space
approach, with the CRA method, is applied for the current
control. To identify the linearized model for the outer loop sys-
tem, which includes an inner loop controller and a switching
circuit for the nonlinear component, the CLOE identication
method is adapted. Then, the w-transform and the CRA
method are used to design a direct digital controller for the
identied model. The converter controller is designed to meet
the specied time response performances, even though the
operational conditions are changed. The PSiM simulations and
experiments have been carried out to verify the performance
of the designed converter system. From the results, it is shown
that the new proposed method achieves good performance.
APPENDIX
A. Denition of the K-polynomial
Consider a real polynomial with positive coefcients,
(s) =
n
s
n
+ +
1
s +
0
, for
k
> 0. (49)
526 Journal of Power Electronics, Vol. 10, No. 5, September 2010
The characteristic ratios and the generalized time constant
[21] are dened as

1
:=

2
1

2
,
2
:=

2
2

3
, ,
n1
:=

2
n1

n2

n
, (50)
:=

1

0
. (51)
According to (50) and (51), the coefcient of (s) can be
represented in terms of
i
s, and as follows.

1
=
0
,
2
=

0

1
, ,
n
=

0

n1

n1
1
. (52)
In [21], it has been shown that is related to the speed of
the time response of the all pole system whose denominator is
(s), and the
i
s are closely related to damping and stability.
The K-polynomial is dened as a polynomial for which the
characteristic ratios obey the following formula:
_

1
2,

k
=
sin(
k
n
)+sin(

n
)
2 sin(
k
n
)

1
, for k = 2, n 1.
(53)
It is important to note that the K-polynomial is generated
by only two parameters
1
and for any
0
. For example, let
us make a K-polynomial,
k
(s), of degree n = 6 with
0
= 1
and = 1. If we choose
1
= 2.5 arbitrarily, then (53) results
in
[
1

2

5
] = [2.5 1.9717 1.875 1.9717 2.5]. (54)
Using (52), the following K-polynomial is obtained.

k
(s) = 1.058x10
5
s
6
+ 4.818x10
4
s
5
+8.780x10
3
s
4
+ 8.115x10
2
s
3
+ 0.4s
2
+ s + 1. (55)
B. Synthesis of the reference polynomial

(w): Derivation of
(43)
As mentioned in Section IV-A, a current controller gain
K that satises the maximum settling time and exhibits
good damping can be algebraically determined only if such a
reference polynomial

(z) is given. Thus, this problem boils

down to the problem of nding such a

(w) . In Section 3.1

of [18] and Section 6 of [19], the methods for synthesizing a
transfer function under the conditions of the transient response
requirements have been presented. Here, it will be shown how
(43) is obtained by using the CRA method. In this approach,
we rst choose a characteristic ratio,
1
, for the K-polynomial
of degree 3 such that the transfer function H
k
(s) =
0
/
k
(s)
has a satisfactory damping. It was shown in [19] that any
value of H
k
(s)s has a non-overshooting step response only if

1
> 2.836 in (53) holds when n = 3. Thus, we are supposed
to choose
1
= 3.0. Then the other characteristic ratio
2
becomes 3.0 from (53). Assuming that
f
= 0.01 and
0
= 1
for the rst trial, the corresponding K-polynomial is obtained
from (52) as follows;

k
(s,
f
= 0.01) = s
3
+900s
2
+2.710
5
s+2.710
7
. (56)
The step response of the transfer function, H
k
(s,
f
=
0.01) = 2.7 10
7
/
k
(s,
f
), is shown in Fig. 19. It has no
overshoot but the settling time of 1 % is 28[msec].
Fig. 19. Step responses of H
k
(s)s with two s.
It has been demonstrated in [18] and [19] that the speed of
the step response of a linear all pole system can be controlled
by adjusting the generalized time constant () only if all of
its characteristic ratios are unchanged. The smaller the value
of , the faster the settling time becomes while its maximum
overshoot holds the same. Suppose that H
k
(s,
f
) gives rise
to a settling time of t
sf
. According to the results in [18] and
[21], the value of
d
for H
k
(s,
d
) to have the desired settling
time, t
sd
, can be determined by

d
=
t
sd
t
f

f
. (57)
Since the desired settling time should be less than 10[msec],
we choose t
sd
= 9[msec]. The above equation results in the
following
d
.

d
=
9 10
3
28 10
3
(0.01) = 3.2 10
3
.
Using (52) associated with
1
,
2
, and
d
, the following K-
polynomial is obtained.

(s,
d
) = s
3
+2.812510
3
s
2
+2.63710
6
s+8.2410
8
. (58)
The step response of the transfer function, H
k
(s,
d
) =
8.2410
8
/

(s,
d
), is also shown in Fig. 19. It is evident that
H
k
(s,
d
) is non-overshooting and that it has a settling time
of 9[msec]. If the complex variable s in (58) is replaced by w,
(58) is identical to (43). Fig. 11 shows the reference input i

s
and the output i
s
of the closed loop transfer function in (33)
of which the denominator has been transformed by

(w).
So, we conrm that the resulting current controller exhibits
non-overshooting and a settling time of about 8.3[msec].
ACKNOWLEDGMENT
This work was supported in part by an Ministry of Knowl-
edge Economy, Korea, under the Information Technology
Research Center (ITRC) support program supervised by the
National IT Industry Promotion Agency (NIPA) (NIPA-2009-
(C1090-0904-0007)) and in part by a research grant from
Chungbuk National University in 2008.
Direct Digital Control of Single-Phase AC/DC PWM Converter System 527
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Young Chol Kim received his B.S. in Electrical En-
gineering from Korea University, Korea in 1981, and
his M.S. and the Ph.D. in Electrical Engineering from
Seoul National University, Korea in 1983 and 1987
respectively. Since March 1988, he has been with the
Colleage of Electrical & Computer Engineering, Chung-
buk National University, Korea, where he is currently
a professor. He was a Post-doctoral Fellow at Texas
A&M University in 1992 and a visiting research fellow
at COE-ISM, Tennessee State Univ./Vanderbilt Univ. in 2001. He has been the
chairman of the KIEE Control and Instrument Society since 2009. His research
interests include parametric robust control, low-order controller design, and
transient response control via characteristic ratio assignment.
Lihua Jin was born in Jilin, China in 1978. She received
her B.S. in Electronic Engineering from Yanbian Uni-
versity, China in June 1999, and her M.S. in Electronics
Engineering from Chungbuk National University, Korea
in August 2007. She is currently working towards her
Ph.D. in Electronics Engineering. Her research interests
include low-order controller design with time response
specications, model-free/non-parametric model design,
and system identication.
Jinmok Lee received his B.S., M.S., and Ph.D in Elec-
trical Engineering from Chungbuk National University
in Cheongju, Korea in 2002, 2004, and 2009, respec-
tively. Currently, he is working at the Automation R&D
Center of LS Industrial Systems as Research Engineer.
His research interests include inverter systems, digital
control and renewable energy systems. He is a member
of KIPE and KIEE.
Jaeho Choi received his B.S., M.S., and Ph.D in
Electrical Engineering from Seoul National University,
Seoul, Korea in 1979, 1981, and 1989, respectively.
From 1981 to 1983, he was with Jungkyoung Technical
College, Daejeon, Korea, as a Full-time Lecturer. Since
1983, he has been with the School of Electrical and
Computer Engineering, Chungbuk National University
in Cheongju, Korea, where he is currently a professor.
In 1993, 1998 and 2003, he was a visiting Professor at
the University of Toronto, Canada, for one each year and he was a Danfoss
Visiting Professor at Alborg University in Denmark in 2000. His research
interests include power electronics, power quality problems and solutions,
energy storage systems, as well as renewable energy and microgrid systems.
He is an active member of KIPE, KIEE, and IEEE, and currently the Editor-
in-Chief of JPE.