Advanced Topics in Logic Design Final Exam

Cairo University Faculty of Engineering
Department of Electronics and Electrical Communications Engineering
Advanced Topics in Logic Design

Fourth Year 2012/2013 - Term 1 Final Exam January 2013 2 Hours
Attempt ALL Questions

Question 1 Boolean Function Decomposition & Boolean SAT a. [2 marks] Write the general expression for the Shannon Function Decomposition of a Boolean function f of n Boolean variables x1, x2, ., xn about the splitting variable xi, where 1 i n, in terms of its positive and negative cofactors with respect to xi. b. [2 marks] Show that the Boolean function given in part (a) is independent of xi if its positive and negative cofactors with respect to xi are logically equivalent. c. [3 marks] Show that the Boolean function given in part (a) is negative unate with respect to xi if all minterms in its positive cofactor with respect to xi are also minterms of its negative cofactor with respect to xi, and the positive and negative cofactors with respect to xi are not logically equivalent. d. [3 marks] If the universal quantification of the Boolean function given in part (a) with respect to xi is found to be unsatisfiable, can there exist a product term in any SOP of the function that does not contain either the positive or negative literal of xi? Explain the reason, and give an example to illustrate the answer. e. [5 marks] Use Davis-Logemann-Loveland Depth-First Search Algorithm to solve the following SAT problem: (x1 + x3) (x2 + x3) (x1 + x4) (x2 + x4) (x1 + x3 + x4) (x1 + x2 + x4). Question 2 Boolean Matching a. [3 marks] Write an expression for the total number of mappings that can be considered when attempting to find a possible matching for a pair of Boolean functions in terms of the number of Boolean variables of the functions n. Can a pair of Boolean functions be matched if they have different number of variables? What are the drawbacks of the Canonical Boolean Matching algorithms based on truth tables and table lookup? b. [4 marks] Compute the Unateness and the Size of the Onset signatures of the pair of Boolean functions f = x1 x3 + x2 + x1x3 and g = y1y2 y3 + y1 y2y3. c. [3 marks] Find a possible matching for the two functions given in part (b) if it exists.
Page 1 /3
Question 3 Logic Optimization a. [4 marks] Explain how to check whether cube C in cover F of the Boolean function f is either redundant or irredundant. Illustrate that by checking whether the cube C = x1 x3 in the following cover F = {x1 x2, x2 x4, x3 x4, x1 x3, x2 x3} is redundant or irredundant. b. [6 marks] Illustrate how the Quine-McClosky procedure is applied to generate all prime cubes of the Boolean function f whose on-set is given by the cover F = {x1 x2 x4, x2 x3 x4} and dont care set is given by the cover D = {x1 x2, x2 x4}. Write the covering table of the function and show how it is used to generate the minimum-size cover. c. [5 marks] Illustrate how the minimum column cover is used to generate the complement of the unate Boolean function f = x1 x3 + x2 x4 + x1 x4 + x2 x3.
Question 4 ROBDD a. [2 marks] Explain the tradeoff between using canonical data structures such as truth tables and binary decision diagrams and non-canonical data structures such as covers to represent Boolean functions. b. [4 marks] Explain how the if-then-else (ITE) operator is used to build a reduced-ordered binary decision diagram representation of a Boolean function f. Illustrate that by sketching the ROBDD representation of a 2-input NOR Boolean function. c. [4 marks] Show that the ROBDD representation of an n-input XOR Boolean function has n levels and (2n-1) nodes. Illustrate how the onset of the 4-input XOR Boolean function is generated from its ROBDD representation.
Question 5 AIG a. [2 mark] Use De Morgans law to design an AIG with the minimum number of levels for a 4 -input OR gate. b. [4 marks] Construct an AIG representation with the minimum number of level for a 42 encoder. c. [4 marks] Show how construct an AIG representation for a 5-input majority encoder.
Question 6 Logic Difference & Incremental Synthesis a. [4 marks] Describe the main phases of the DeltaSyn incremental synthesis techniques used to minimize the logic difference between an original design and the desired design modified by Engineering Change Orders CEO.
Page 2 /3
b. [6 marks] Illustrate how the DeltaSyn technique is applied to minimize the logic difference between the desired output y and the original model y* whose schematics are given in the following Figure.
Page 3 /3

Advanced Topics in Logic Design Final Exam

Uploaded by

Copyright:

Available Formats

Advanced Topics in Logic Design Final Exam

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Advanced Topics in Logic Design Final Exam

Uploaded by

Copyright:

Available Formats

Cairo University Faculty of Engineering

Department of Electronics and Electrical Communications Engineering

Advanced Topics in Logic Design

Attempt ALL Questions

You might also like