Scribd Logo
Upload

Welcome to Scribd!

  • 65 views

    Lab 3

    Uploaded by

    drfaizal
    This document provides instructions for Lab 3, which involves designing and building multiplexer (MUX) and decoder circuits using logic gates. For the MUX pre-lab, students are asked to provide truth tables, logic equations, and schematic designs. For the decoder pre-lab, similar deliverables are requested including truth tables, logic equations, voltage tables, and schematic designs for a 2-to-4 decoder. The in-lab portions involve building the designed MUX and decoder circuits and demonstrating their functions to the teaching assistant.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Lab 3

    Uploaded by

    drfaizal
    65 views2 pages
    This document provides instructions for Lab 3, which involves designing and building multiplexer (MUX) and decoder circuits using logic gates. For the MUX pre-lab, students are asked to provide truth tables, logic equations, and schematic designs. For the decoder pre-lab, similar deliverables are requested including truth tables, logic equations, voltage tables, and schematic designs for a 2-to-4 decoder. The in-lab portions involve building the designed MUX and decoder circuits and demonstrating their functions to the teaching assistant.

    Original Description:

    lab

    Original Title

    Lab3

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides instructions for Lab 3, which involves designing and building multiplexer (MUX) and decoder circuits using logic gates. For the MUX pre-lab, students are asked to provide truth tables, logic equations, and schematic designs. For the decoder pre-lab, similar deliverables are requested including truth tables, logic equations, voltage tables, and schematic designs for a 2-to-4 decoder. The in-lab portions involve building the designed MUX and decoder circuits and demonstrating their functions to the teaching assistant.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    65 views2 pages

    Lab 3

    Uploaded by

    drfaizal
    This document provides instructions for Lab 3, which involves designing and building multiplexer (MUX) and decoder circuits using logic gates. For the MUX pre-lab, students are asked to provide truth tables, logic equations, and schematic designs. For the decoder pre-lab, similar deliverables are requested including truth tables, logic equations, voltage tables, and schematic designs for a 2-to-4 decoder. The in-lab portions involve building the designed MUX and decoder circuits and demonstrating their functions to the teaching assistant.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    University of Florida

    Department of Electrical & Computer Engineering

    EEL 3701 Fall 2012 Revision 0

    Dr. Eric M. Schwartz


    12-Sep-12

    Page 1/2

    LAB 3: MSI Circuits


    * (or a ), indicate that any value can replace it. If one * exists in a row of a truth table, the one row represents two rows; one with the * replaced by a 0 and the other with the * replaced by a 1. If there are two asterisks in a single row, that row is an abbreviation for four rows. Write the logic equation for this MUX. Draw a voltage table for this MUX. The figure shows that some of the D inputs and both of the S inputs are active-high; and some of the D inputs and the output are active-low. Draw a functional block diagram of the MUX; draw signal definitions (i.e., activation levels and signal names outside the MUX). Design a circuit for this MUX using logic gates available in the ICs listed above in the Materials section above. (It is usually easier to design first on paper.) There is no requirement, in this lab, to minimize the number of gates or chips; but of course a simpler design will be easier to build.) If you designed the circuit in part 4 on paper, now design it using Quartus and then simulate the complete mixed-logic circuit in Quartus. Add pin numbers and chip labels to the logic circuit diagram to make this a wiring diagram. Annotate the simulation. Each of the above items, including the truth tables, logic equations, voltage tables, circuit schematics (with chip and pin numbers), simulation results, and your Quartus simulation files should be part of the emailed lab document. As usual, all pre-lab material must be emailed prior to the start of your lab.

    OBJECTIVES The objective of this lab is to familiarize students with the structure, operation and application of multiplexers and decoders, two common MSI (medium scale integrated) devices. Students will design and build these devices using SSI (small-scale integrated) components. MATERIALS Prototyping board (bread board) Wires, Switches, LEDs, Resistor packs IC's: Any SSI (no MUX or Decoder) chips available in your lab kits NEW PRE-LAB RULES A single pdf document (for this lab, called Lab3_your_initials.pdf) of all design files (bdf or vhdl) and simulation files is required for this and all subsequent pre-labs. I suggest that you capture screen shots of each design and simulation (as they are generated) into a MS-Word (or equivalent) file and then save it as a pdf file. This file should also include any other required items including truth/voltage tables, or anything else specifically requested in the lab document. It is okay to scan and include files that are not specifically requested to be computer generated. Label included items with the associated lab part number, e.g., Part 2 #37. Two pdf files will be emailed: the pdf file described above and your Summary.pdf file. You should also attach the two Quartus archive files that you generate in the pre-lab sections. Part I. Multiplexer Design The multiplexer (MUX) is a device that acts as a multiposition switch. See Figure 1. A number of DATA inputs are applied to this device (D0-D3) and one of the inputs is switched to the output (Y) of the device. A binary number applied to the SELECT (S1 & S0) lines controls which input is passed to the output. For example, when S1=S0=0, D0 is logically connected to the output Y. When S1=0 & S0=1, D1 logically connected to Y and so forth for D2 & D3 to connect to Y. Notice that the inputs D0, D1, S1, and S0 are active-high, D2 and D3 are active-low, and the output, Y, is active-low. 2. 3.

    4.

    5.

    6.

    Part I. In-Lab Build your Pre-Lab's MUX solution in-lab or at home. (Historically, the most successful students build their circuits at home.) Demonstrate its function to your TA. You can demonstrate your circuits operation by connecting appropriate switch circuits to all six inputs and an active-low LED circuit to the output. Go through the different switch combinations with your TA. Part II. Decoder Design A decoder starts with a binary number (pattern) and then decodes it to an individual output signal. For example, in the 2:4 Decoder shown in Figure 2, a two-bit binary number (A1 concatenated with A0) is decoded such that only one of the 4 outputs goes true if the device is enabled; otherwise all outputs are false.

    Part I. Mux Pre-Lab 1. Draw a truth table for the 4-input multiplexer (6 inputs and 1 output) using wild cards as appropriate. Wild cards, usually designated with an

    University of Florida
    Department of Electrical & Computer Engineering

    EEL 3701 Fall 2012 Revision 0

    Dr. Eric M. Schwartz


    12-Sep-12

    Page 2/2

    LAB 3: MSI Circuits

    This 2:4 Decoder has active-low inputs, A1 and A0, and an active-high enable, E, that functions in the following manner. When the enable is false (low), all outputs are false. When the enable is true (high), an output will go true based on the binary pattern placed on A1 & A0 (described above). For example, if the enable is true, then when A1=A0=0 (both high), then only Y0 goes true (high), with Y1, Y2, and Y3 all false; when A1=0 (high) and A0=1 (low), then only Y1 goes true (low), with Y0, Y2, and Y3 all false; and so forth for the remaining two A1 and A0 combinations. Part II. Pre-Lab Requirements 1. Draw truth tables for the above decoder. 2. Create logic equations for each of the outputs. 3. Draw a voltage table for the above decoder. 4. Design a circuit to implement the design. Draw a functional block diagram of the Decoder; draw signal definitions (i.e., activation levels and signal names outside the Decoder 5. If you designed the circuit in part 4 on paper, now design it using Quartus and then simulate the complete mixed-logic circuits in Quartus. There is no requirement, in this lab, to minimize the number of gates or chips; but of course a simpler design will be easier to build.) Add pin numbers and chip labels to the circuit diagram to make this a wiring diagram. Annotate the simulation. 6. Each of the above items, including the truth tables, logic equations, voltage tables, circuit schematics (with chip and pin numbers), simulation results, and your Quartus simulation files should be part of the emailed lab document. As usual, all pre-lab material must be emailed prior to the start of your lab. 7. Email your archive file. Part II. In-Lab Construct your 2-to-4 decoder design in lab (or at home) and demonstrate its function to your TA. Use appropriate switch circuits for inputs and LED circuits for outputs.

    You might also like