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A Simple Design - Doulos

Comments are not part of the verilog design, but allow the user to make notes referring to the code, usually as an aid to understanding it. There are tw o types of comment in verilog, line comments and block comments; w e w ill look at line comments for now.

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Miguel Bruno
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81 views2 pages

A Simple Design - Doulos

Comments are not part of the verilog design, but allow the user to make notes referring to the code, usually as an aid to understanding it. There are tw o types of comment in verilog, line comments and block comments; w e w ill look at line comments for now.

Uploaded by

Miguel Bruno
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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27/12/12

A Simple Design

A Simple Design
A design is described in Verilog using the concept of a module. A module can be conceptualised as consisting of tw o parts, the port declarations and the module body. The port declarations represent the external interface to the module. The module body represents the internal description of the module its behaviour, its structure, or a mixture of both. Let's imagine w e w ant to describe an and-or-invert (AOI) gate in Verilog.

Verilog: an AOI gate module


/ /V e r i l o gc o d ef o rA N D O R I N V E R Tg a t e m o d u l eA O I( i n p u tA ,B ,C ,D ,o u t p u tF ) ; a s s i g nF=~ ( ( A&B )|( C&D ) ) ; e n d m o d u l e / /e n do fV e r i l o gc o d e OK, that's the code. Let's dissect it line by line...

Comments
/ /V e r i l o gc o d ef o rA N D O R I N V E R Tg a t e Like all programming languages, Verilog supports comments. There are tw o types of comment in Verilog, line comments and block comments; w e w ill look at line comments for now . Comments are not part of the Verilog design, but allow the user to make notes referring to the Verilog code, usually as an aid to understanding it. Here the comment is a header that tells us that the Verilog describes an AOI gate. It is no more than an aide de memoire in this case. A Verilog compiler w ill ignore this line of Verilog. Tw o forw ard slashes mark the start of a line comment, w hich is ignored by the Verilog compiler. A line comment can be on a separate line or at the end of a line of Verilog code, but in any case stops at the end of the line.

Module and Port declarations


m o d u l eA O I( i n p u tA ,B ,C ,D ,o u t p u tF ) ; The name of the module is just an arbitrary label invented by the user. It does not correspond to a name pre-defined in a Verilog component library. m o d u l eis a Verilog keyw ord. This line defines the start of a new Verilog module definition. All of the input and output ports of the module must appear in parentheses after the module name. The ordering of ports is not important for the module definition per se, although it is
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27/12/12

A Simple Design

conventional to specify input ports first. A port may correspond to a pin on an IC, an edge connector on a board, or any logical channel of communication w ith a block of hardw are. The port declarations include the names of the ports ( e.g., A , B), and the direction that information is allow ed to flow through the ports ( i n p u t , o u t p u tor i n o u t ).

Endmodule
e n d m o d u l e The module definition is terminated by the Verilog keyw ord e n d m o d u l e .

Functionality
Well, that's the interface to the module taken care of, but w hat about it's functionality? a s s i g nF=~ ( ( A&B )|( C&D ) ) ; In this module body, there is but one statement, and all the names referenced in this statement are in fact the ports of the design. Because all of the names used in the module body are declared in the module header and port declarations, there are no further declarations for internal elements required in the module body. a s s i g nis a Verilog keyw ord. It denotes a concurrent continuous assignment, w hich describes the functionality of the module. The concurrent assignment executes w henever one of the four ports A, B, C or D change value. The ~, & and | symbols represent the bit-w ise not, and and or operators respectively, w hich are built in to the Verilog language. That's it! That's all there is to describing the functionality of an AOI gate in Verilog. / /e n do fV e r i l o gc o d e Another Verilog comment, and that's the end of a Verilog description for an AOI gate.

Verilog 1995
The above example is w ritten using Verilog-2001 syntax. Many people continue to use the 1995 syntax, w hich is still allow ed in Verilog-2001. In Verilog-1995 the module header w ould look like this: m o d u l eA O I( A ,B ,C ,D ,F ) ; i n p u tA ,B ,C ,D ; o u t p u tF ; Note that the port names are listed after the module name, and declared as inputs and outputs in separate statements. The port declarations must repeat the names of the ports in the module header. Next Copyright 2005-2012 Doulos. All rights reserved.

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