CPE300: Digital System Architecture and Design

Fall 2011 MW 17:30-18:45 CBC C316 Control, Reset, Exceptions 10312011

http://www.egr.unlv.edu/~b1morris/cpe300/

Outline
Review Datapath/Control 2- and 3-Bus SRC Processor Design Machine Reset Machine Exceptions

Register Transfer Descriptions

Abstract RTN
Defines what not the how (Chapter 2)
Overall effect of instructions on programmer-visible registers

Implementation independent
Registers and operations

Concrete RTN
Detailed register transfer steps in datapath to produce overall effect
Dependent on implementation details

Steps correspond to processor clock pulses

1-Bus SRC Microarchitecture

5 classic components of computer
Memory, Input, Output CPU Control and Datapath

More Complete View of 1-Bus SRC Design

Add control signals and gate-level logic
1 6 Condition bit flip-flop

IR register logic and data paths 2

3 4 5 Shift counter register

Control Sequences
Register transfers are the concrete RTN Control sequence are the control signals that cause the RT
Step T0 T1 Concrete RTN MAPC: CPC+4; MDM[MA]: PCC Control Sequence PCout, MAin, Inc4, Cin Read, Cout, PCin, Wait

T2
T3

IRMD
instruction_execution

MDout, IRin

Wait prevents control sequence from advancing to step T2 until memory asserts Done

Control Steps, Control Signals, and Timing

Order control signals are written is irrelevant for a given time step
Step T0:
(Inc4, Cin, PCout, MAin) = (PCout, MAin, Inc4, Cin)

Timing distinction is made between gates and strobes

Gates early, strobes late in clock cycle

Memory read should start as early as possible to reduce wait time MA must have correct value before being used for a read

Clocking the Datapath

Register transfers result from information processing
Register transfer timing register to register

Level sensitive latch flipflops in example tR2valid is the period from begin of gate signal till inputs at R2 are valid tcomb is delay through combinational logic, such as ALU or cond logic

Signal Timing on the Datapath

Several delays occur in getting data from R1 to R2
Gate delay through the 3-state bus drivertg Worst case propagation delay on bustbp Delay through any logic, such as ALUtcomb Set up time for data to affect state of R2tsu

Data can be strobed into R2 after this time tR2valid = tg + tbp + tcomb + tsu Diagram shows strobe signal in the form for a latch. It must be high for a minimum timetw There is a hold time, th, for data after strobe ends

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Signal Timing and Minimum Clock Cycle

A total latch propagation delay is the sum Tl = tsu + tw + th
All above times are specified for latch th may be very small or zero

The minimum clock period is determined by finding longest path from flip-flop output to flipflop input
This is usually a path through the ALU Conditional signals add a little gate delay Minimum clock period is

tmin = tg + tbp + tcomb + tl

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Consequences of Flip-Flop Type

Flip-flop types (Appendix A.12)
Level-triggered (latch) state can change while clock is high Edge-triggered state changes only on a clock transition (highto-low or low-to-high) Master-slave breaks feedback from output/input of register allowing on a single state change per clock cycle
If this output can affect its input, an error can occur (feeback)

During the high part of a strobe a latch changes its output

This can influence even the kind of concrete RTs that can be written for a data path If the C register is implemented with latches, then C C + MD; is not legal If the C register is implemented with master-slave or edge triggered flip-flops, it is OK

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The Control Unit

Brain of a machine Datapath implementation led to control sequences to implement instructions Control unit will generate the control sequences The control units job is to generate the control signals in the proper sequence Things the control signals depend on
The time step Ti The instruction op code (for steps other than T0, T1, T2) Some few datapath signals like CON, n=0, etc. Some external signals: reset, interrupt, etc. (to be covered) Logic to enable control signal Timing of signals

The components of the control unit are: a time state generator, instruction decoder, and combinational logic to generate control signals

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Detailed Control Unit

Clock and control sequence Instruction decode

Exception signals

Control signals for datapath

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Control Signal Encoder Logic

Write equation describing control signal
Find all occurrences of control signal in entire set of control sequences Equation implemented by digital logic gates
Step T0 T1 T2 Step T3 T4 T5 T6 T7 Fetch Control Sequence PCout, MAin, Inc4, Cin Read, Cout, PCin, Wait MDout, IRin SHR Control Sequence c1out, Ld n=0(Grc, Rout, Ld) Grb, Rout, C=B, Cin n0(Cout, SHR, Cin, Decr, Goto6) Cout, Gra, Rin, End Step T3 T4 T5 ADD Control Sequence Grb, Rout, Ain Grc, Rout, ADD, Cin Cout, Gra, Rin, End Step T3 T4 T5 T6 T7 Step T3 T4 T5 ADDI Control Sequence Grb, Rout, Ain c2out, ADD, Cin Cout, Gra, Rin, End Step T3 T4 BR Control Sequence Grc, Rout, CONin Grb, Rout, CONPCin, End

ST Control Sequence Grb, BAout, Ain c2out, ADD, Cin Cout, MAin Gra, Rout, MDin, Write Wait, End

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Control Signal Examples

Step T0 T1 T2 Step T3 T4 T5 T6 T7 Fetch Control Sequence PCout, MAin, Inc4, Cin Read, Cout, PCin, Wait MDout, IRin SHR Control Sequence c1out, Ld n=0(Grc, Rout, Ld) Grb, Rout, C=B, Cin n0(Cout, SHR, Cin, Decr, Goto6) Cout, Gra, Rin, End Step T3 T4 T5 ADD Control Sequence Grb, Rout, Ain Grc, Rout, ADD, Cin Cout, Gra, Rin, End Step T3 T4 T5 T6 T7 Step T3 T4 T5 ADDI Control Sequence Grb, Rout, Ain c2out, ADD, Cin Cout, Gra, Rin, End Step T3 T4 BR Control Sequence Grc, Rout, CONin Grb, Rout, CONPCin, End

ST Control Sequence Grb, BAout, Ain c2out, ADD, Cin Cout, MAin Gra, Rout, MDin, Write Wait, End

Gra = T5(add + addi) + T6st +T7shr +

Use of datapath conditions

Grc = T4add + T4(n=0)shr +

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Branching in the Control Unit

Tri-state gates allow 6 to be applied to counter input Reset will synchronously reset counter to step T0 T0 Mck is the master clock oscillator signal T1
T2 . . .

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Clocking Logic
Generates Run signal Generate synchronized done signal SDone Generates R, W from Read, Write control Generates Enable which controls counter

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Completed 1-Bus Design

High level architecture block diagram Concrete RTN steps Hardware design of registers and data path logic Revision of concrete RTN steps where needed Control sequences Register clocking decisions Logic equations for control signals Time step generator design Clock run, stop, and synchronization logic

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Alternate Architectural Design

Require different RTN than 1-bus design More datapaths allow more things to be done in a single step 2-bus example that separates input and output of ALU on different buses
C register can be eliminated Control steps can be reduced by strobing ALU results directly into their destinations

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2-Bus SRC Microarchitecture

A bus carries data going into registers B bus carries data being gated out of registers ALU function C=B is used for all simple register transfers
R[a]R[b]

Allows increment transfers

R[n]R[m]+1

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2-Bus Control for ADD Instruction

add(:=op=12)R[ra]R[rb]+R[rc]:
Step T0 T1 T2 T3 T4 Concrete RTN MAPC; MDM[MA]: PCPC+4 IRMD; AR[rb] R[ra]=A+R[rc]; Control Sequence PCout, C=B, MAin, Read, Wait, PCout, INC4, PCin MDout, C=B, IRin Grb, Rout, C=B, Ain Grc, Rout, ADD, Sra, Rin, End

Note the appearance of Grc to gate the output of the register rc onto the B bus and Sra to select ra to receive data strobed from the A bus Two register select decoders will be needed Transparent latches will be required for MA at step T0

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2-Bus Performance
Speedup = = execution time =
is 1- or 2-bus
1 2

Assumptions
and dont change in going from 1 bus to 2 buses goes from 8 to 7 clocks (nave assumption)
1 2 8 7 8 7

Speedup =

= = 1.143 = 14.3%

What happens if clock also changes?

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3-Bus Design
A 3-bus architecture allows both operand inputs and the output of the ALU to be connected to buses
Shortens control sequences even further than 2bus design

Both the C output register and the A input register are eliminated Careful connection of register inputs and outputs can allow multiple RTs in a step

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3-Bus SRC Microarchitecture

A-bus is ALU operand 1 B-bus is ALU operand 2 C-bus is ALU output Note MA input connected to the B-bus Allows operations such as R[n]R[m]+R[k] to complete in one cycle. What are cost implications?

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3-Bus Control for ADD Instruction

add(:=op=12)R[ra]R[rb]+R[rc]:
Step T0 Concrete RTN MAPC: MDM[MA]: PCPC+4 IRMD; R[ra]=R[rb]+R[rc]; Control Sequence PCout, MABin, INC4, PCin, Read Wait MDout, C=B, Irin GArc, RAout, GBrb, RBout, ADD, Sra, Rin, End

T1 T2

Note the use of 3 register selection signals in step T2: GArc, GBrb, and Sra In step T0, PC moves to MA over bus B and goes through the ALU Inc4 operation to reach PC again by way of bus C
PC must be edge triggered or master-slave

Once more MA must be a transparent latch

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3-Bus Performance
Speedup = = execution time =
is 1- or 2-bus
1 3

Assumptions
and dont change in going from 1 bus to 3 buses goes from 8 to 4 clocks (nave assumption) increases by 10%

Speedup =

1 3

8 41.1

8 4.4

= 1. 818 = 81.8%

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Machine Reset
Reset sets program counter to a fixed value
May be a hardwired value Contents of a memory cell whose address is hardwired

The control step counter is reset Pending exceptions are prevented, so initialization code is not interrupted It may set condition codes (if any) to known state It may clear some processor state registers A soft reset makes minimal changes
PC, T (T-step counter)

A hard reset initializes more processor state

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SRC Reset Capability

Both hard and soft reset specified Strt signal will do a hard reset
Effective only when machine is stopped Resets the PC to zero Resets all 32 general registers to zero

Soft Rst signal is effective when the machine is running

Resets PC to zero Restarts instruction fetch Clears the Reset signal

Actions on reset are described in instruction_interpretation

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Abstract RTN for SRC Reset and Start

Processor State
Strt Rst ;start signal ;external reset signal

instruction_interpretation := ( RunStrt(Run1: PC, R[0..31]0); RunRst(IRM[PC]: PCPC+4; instruction_execution): RunRst(Rst0: PC0); instruction_interpretation):

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Resets in the Middle of Instruction Execution The abstract RTN implies that reset takes effect after the current instruction is done To describe reset during an instruction, we must go from abstract to concrete RTN Why might we want to reset in the middle of an instruction?
Long instructions

How would we reset in the middle of an instruction?

Check for Rst at each control time step

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Concrete RTN and Control with Reset

Step T0 T1 T2 Concrete RTN Rst(MAPC: CPC+4): Rst(Rst0:PC0: T0); Rst(MDM[MA]: PCC): Rst(Rst0:PC0: T0); Rst(IRMD): Rst(Rst0:PC0: T0); Rst(AR[rb]): Rst(Rst0:PC0: T0); Rst(CA+R[rc]): Rst(Rst0:PC0: T0); Rst(R[ra]C): Rst(Rst0:PC0: T0); Control Sequence Rst(PCout, MAin, Inc4, Cin) Rst(ClrPC, ClrR, Goto0); Rst(Read, Cout, PCin, Wait) Rst(ClrPC, ClrR, Goto0); Rst(MDout, IRin) Rst(ClrPC, ClrR, Goto0); Rst(Grb, Rout, Ain) Rst(ClrPC, ClrR, Goto0); Rst(Grc, Rout, ADD, Cin) Rst(ClrPC, ClrR, Goto0); Rst(Cout, Gra, Rin, End) Rst(ClrPC, ClrR, Goto0);

T3 T4 T5

Same RTN/control as before but must check Rst ClrPC clears the program counter to all zeros ClrR clears the one bit Reset flip-flop
Reset actions are the same for every step of every instruction control signals are independent of time step or opcode

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Machine Exceptions
An exception is an event that causes a change in the program specified flow of control
Internal are usually synchronous (overflow) External often asynchronous (keyboard)

Often called interrupts

Normal program execution is interrupted

No standard naming conventions

Exception for general term Interrupt for an exception caused by an external event, such as an I/O device condition

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Hardware/Software Exception Response

The system must control the type of exceptions it will process at any given time The state of the running program is saved when an allowed exception occurs Control is transferred to the correct software routine, or handler for this exception This exception, and others of less or equal importance are disallowed during the handler The state of the interrupted program is restored at the end of execution of the handler

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Hardware Support of Exceptions

To determine relative importance, a priority number is associated with every exception Hardware must save and change the PC
Required for program execution

Hardware must disable the current exception

Could interrupt the handler before it can start

Address of the handler is called the exception vector and is a hardware function of the exception type Exceptions must access a save area for PC and other hardware saved items
Choices are special registers or a hardware stack

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Instruction Support of Exceptions

An instruction executed at the end of the handler must reverse the state changes done by hardware when the exception occurred There must be instructions to control what exceptions are allowed
The simplest of these enable or disable all exceptions

If processor state is stored in special registers on an exception, instructions are needed to save and restore these registers

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Types of Exceptions
System reset Exceptions associated with memory access
Machine check memory failure Data access memory not available Instruction access instruction not available (similar to data access) Alignment improperly aligned access Illegal instruction instruction not in IS Unimplemented instruction legal but not in IS Privileged instructions instruction not available Arithmetic errors

Program exceptions

Miscellaneous hardware exceptions (e.g. watchdog) Trace and debugging exceptions Non-maskable exceptions (NMI) very bad cases External exceptionsinterrupts

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SRC Exception Processing

The exception mechanism for SRC handles external interrupts There are no priorities
Only a simple enable and disable mechanism

The PC and information about the source of the interrupt are stored in special registers
Any other state saving is done by software

The interrupt source supplies 8 bits that are used to generate the interrupt vector It also supplies a 16 bit code carrying information about the cause of the interrupt

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SRC Interrupt Processor State

From Dev. To Dev. Internal to CPU to CPU From Dev. From Dev Internal
Bits Ivect<31..0>

Processor interrupt mechanism

ireq: ;interrupt request signal iack: ;interrupt acknowledge signal IE: ;one bit interrupt enable flag IPC<31..0>: ;storage for PC saved upon interrupt II<15..0>: ;info. on source of last interrupt Isrc_info<15..0>: ;information from interrupt source Isrc_vect<7..0>: ;type code from interrupt source Ivect<31..0>:= 20@0#Isrc_vect<7..0>#4@0:

31 0

12 11 Isrc_vect<7..0>

4 3 0000

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SRC Instruction Interpretation with Interrupts

instruction_interpretation := (RunStrtRun1: Run(ireqIE)(IRM[PC]: PCPC+4; instruction_execution): Run(ireqIE)(IPCPC<31..0>: II<15..0>Isrc_info<15..0>: iack1: IE0: PCIvect<31..0>; iack0); instruction_interpretation);

If interrupts are enabled, PC and interrupt info. are stored in IPC and II, respectively
With multiple requests, external priority circuit (discussed in later chapter) determines which vector & info. are returned

Interrupts are disabled The acknowledge signal is pulsed

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SRC Instruction to Support Interrupts

Return from interrupt
rfi(:=op=29)(PCIPC: IE1):

Two RT actions must occur together

Cannot be accomplished with branch and ee instruction combination

Save and restore interrupt state

svi(:=op=16)(R[ra]<15..0>II<15..0>: R[rb]IPC<31..0>); rvi(:=op=17)(II<15..0> R[ra]<15..0> : IPC<31..0> R[rb]):

Enable/disable interrupt system

een(:=op=10)(IE1) edn(:=op=11)(IE0)

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Concrete RTN with Interrupt

Step T0

Concrete RTN
(ireqIE) (ireqIE)(MAPC: CPC+4): (ireqIE) (ireqIE)(IPCPC: IIIsrc_info: IE0: PC20@#Isrc_vect<7..0>#00: iack1; iack0; End);

T1 T2 T3

MDM[MA]: PCC; IRMD; instruction_execution

PC could be transferred to IPC over the bus II and IPC probably have separate inputs for the externally supplied values Iack is pulsed, described as 1; 0, which is easier as a control signal than in RTN

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Exceptions During Instruction Execution

Some exceptions occur in the middle of instructions
Some CISCs have very long instructions (string move) Some exception conditions prevent instruction completion (uninstalled memory)

CPU must make special provision for restarting

Partially completed actions must be reversed so the instruction can be re-executed after exception handling Information about the internal CPU state must be saved so that the instruction can resume where it left off

We will see that this problem is acute with pipeline designsalways in middle of instructions.

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Recap of Design Process

Informal description Formal RTN description Block diagram architecture Concrete RTN steps Hardware design of blocks Control sequences Control unit and timing Chapter 4 SRC Chapter 2

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Chapter 4 Summary
Chapter 4 has done a non pipelined data path, and a hardwired controller design for SRC The concepts of data path block diagrams, concrete RTN, control sequences, control logic equations, step counter control, and clocking have been introduced The effect of different data path architectures on the concrete RTN was briefly explored We have begun to make simple, quantitative estimates of the impact of hardware design on performance Hard and soft resets were designed A simple exception mechanism was supplied for SRC