Systemverilog RTL Tutorial: New Operators
Systemverilog RTL Tutorial: New Operators
http://www.doulos.com/knowhow/sysverilog/tutorial/rtl/
New Operators
SystemVerilog adds a number of new operators, mostly borrowed from C. These include increment (++) and decrement (--), and assignment operators (+=, -=, ...). The wild equality operators (=== and !==) act like the comparisons in a casex statement, with X and Z values meaning dont care.
Labelling
In Verilog, you may label begin and fork statements: begin : a_label In SystemVerilog the label may be repeated at the end: end : a_label This is useful for documenting the code. The label at the end must be the same as the one at the beginning. Modules, tasks and functions may also have their names repeated at the end: module MyModule ... ... endmodule : MyModule In SystemVerilog any procedural statement may be labelled: loop : for (int i=0; ... This is especially useful for loops, because they can then be disabled. Despite enhancing named blocks in this way, one reason for using them is removed: in SystemVerilog variables may be declared in unnamed blocks!
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15-03-2013 06:04
RTL
http://www.doulos.com/knowhow/sysverilog/tutorial/rtl/
sometimes wire. In fact reg and logic are completely interchangeable, but logic is a more appropriate name. There are some restrictions, though. You are not allowed to assign the same variable from more than one continuous assignment or output port connection. This is because there is no resolution for variables like there is for nets in the case of multiple drivers. Also, if you assign a variable in one of these way, you may not assign the same variable using procedural assignments.
Synthesis Idioms
Verilog is very widely used for RTL synthesis, even though it wasnt designed as a synthesis language. It is very easy to write Verilog code that simulates correctly, and yet produces an incorrect design.For example, it is easy unintentionally to infer transparent latches. One of the ways in which SystemVerilog addresses this is through the introduction of new always keywords: always_comb, always_latch and always_ff. always_comb is used to describe combinational logic. It implicitly creates a complete sensitivity list by looking at the variables and nets that are read in the process, just like always @* in Verilog-2001. always_comb if (sel) f = x; else f = y; n addition to creating a complete sensitivity list automatically, it recursively looks into function bodies and inserts any other necessary signals into the sensitivity list. It also is defined to enforce at least some of the rules for combinational logic, and it can be used as a hint (particularly by synthesis tools) to apply more rigorous synthesis style checks.Finally, always_comb adds new semantics: it implicitly puts its sensitivity list at the end of the process, so that it is evaluated just once at time zero and therefore all its outputs take up appropriate values before simulation time starts to progress. always_latch and always_ff are used for infering transparent latches and flip-flops respectively. Here is an example of always_ff:
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15-03-2013 06:04
RTL
http://www.doulos.com/knowhow/sysverilog/tutorial/rtl/
always_ff @(posedge clock iff reset == 0 or posedge reset) if (reset) q <= 0; else if (enable) q++; The advantage of using all these new styles of always is that the synthesis tool can check the design intent.
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15-03-2013 06:04