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    Flipflops

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    Chaitanya Baratam
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    Flipflops

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    Chaitanya Baratam
    34 views4 pages
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    flipflops

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    flipflops description

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    34 views4 pages

    Flipflops

    Uploaded by

    Chaitanya Baratam
    flipflops description

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Cross-coupled NOR gates

    R
    remember,

    EECS150 - Digital Design Lecture 28 More Flip-flops


    May 1, 2003 John Wawrzynek

    If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch:

    00 01 10 11

    NOR 1 0 0 0

    If either R or S becomes =1 then state may change:

    0 R

    Q 0 1 Q' 1 0

    S 0 1 0

    Spring 2003 EECS150 Lec28-FFs Page 1 Spring 2003 EECS150 Lec28-FFs

    What happens if R or S or both become = 1?


    Page 2

    Asynchronous State Transition Diagram


    SR=00 SR=01 SR=00 SR=10 SR=01 SR=11 SR=11 SR=10

    Nand-gate based SR latch

    QQ' 01

    QQ' 10

    SR Latch:
    SR 00 01 10 11

    SR=01

    QQ' 00
    SR=00

    SR=10

    Q hold 0 1 indeterminate
    Same behavior as cross-coupled NORs with invertered inputs.

    S is set input R is reset input

    QQ=00 is often called a forbidden state


    Spring 2003 EECS150 Lec28-FFs Page 3 Spring 2003 EECS150 Lec28-FFs Page 4

    Level-sensitive SR Latch

    D-latch

    Compare to transistor version:


    The input C works as an enable signal, latch only changes output when C is high. usually connected to clock. Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.
    Spring 2003 EECS150 Lec28-FFs Page 5 Spring 2003 EECS150 Lec28-FFs Page 6

    Flip-flops

    J-K FF
    Add logic to eliminate indeterminate action of RS FF. New action is toggle J = jam clk K = kill
    J K Q

    JK 00 00 01 01 10 10 11 11

    Q(t) Q(t+) 0 0 hold 1 1 0 0 reset 1 0 0 1 set 1 1 0 1 toggle 1 0

    Spring 2003

    EECS150 Lec28-FFs

    Page 7

    Spring 2003

    EECS150 Lec28-FFs

    Page 8

    J-K Flip-flop from D-FF

    Toggle Flip-flop from D-FF

    Spring 2003

    EECS150 Lec28-FFs

    Page 9

    Spring 2003

    EECS150 Lec28-FFs

    Page 10

    Storage Element Taxonomy


    synchronous level-sensitive edge-triggered D-type JK-type RS-type n.a. latch flip-flop n.a. n.a. latch asynchronous

    Design Example with RS FF


    With D-type FF state elements, new state is computed based on inputs & present state bits - reloaded each cycle. With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits. Example: bit-serial adder (LSB first)
    n-bit shift registers

    A B
    reset FF FA c s

    With D-FF for carry


    n-bit shift register

    natural form possible form


    Spring 2003 EECS150 Lec28-FFs Page 11 Spring 2003

    R
    Page 12

    EECS150 Lec28-FFs

    Bit-serial adder with RS FF


    RS FF stores the carry: a b ci ci+1 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 s 0 Carry kill ab 1 1 a 0 1 b 0 0 Carry generate ab 1

    S Q R

    Spring 2003

    EECS150 Lec28-FFs

    Page 13

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