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Module 2: Digital Logic

Commentary
Topics
I. Combinational Circuits II. Sequential Circuits III. Finite State Machines

I. Combinational Circuits
A. Boolean Algebra
In module 1, we learned how a computer performs binary arithmetic operations. Computers also perform logical operations using Boolean algebra. You have probably used Boolean logic to perform Web searches in which you ask for all occurrences of a particular sequence of words. You might, for example, have asked for apple AND pecan, strawberry OR peach, lemon but NOT meringue, and so forth. AND, OR, and NOT are Boolean operators. Boolean algebra is an important tool that helps facilitate the analysis and design of digital circuits. Boolean functions, also called Boolean equations, are expressions that mathematically represent a digital circuit. Boolean expressions are formed by connecting Boolean variables using the Boolean operators NOT, OR, and AND. Boolean functions allow a computer to complete a task given specified input values and to produce an output value dependent upon those input values. Boolean algebra operates with two truth values. In logic, mathematics, and computer programming, the truth values are written TRUE and FALSE, or T and F. In electrical engineering, it is customary to denote these truth values by 1 and 0, respectively. We will use the electrical engineering convention in this course, but you should be equally comfortable with all the notations. Some of the basic operators of Boolean algebra are listed below: The NOT operator, also referred to as inversion: If A is a variable with a value of 0 or 1, then A' is read "NOT A" and has the value of 1 or 0, respectively. In other words, A' has the opposite value of A. A' is also referred to as the complement of A. We can write the NOT operator with the following symbols: _ A or A'

The behavior of the NOT operator is summarized in the following table: Table 2.1 The NOT Operator A
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A' 1
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0 1 The AND operator:

1 0

The AND operator can be written in any of the following ways: A.B A.B AB AB The Boolean expression: A . B' . C means A AND NOT B AND C The behavior of the AND operator is described in the table below: Table 2.2 The AND Operator A 0 0 1 1 B 0 1 0 1 A. B 0 0 0 1

The OR operator: The OR operator can be written in any of the following ways: A+B AB Because "+" could mean either addition or the logical OR function, you must infer the meaning from the context in which the "+" is used whenever you see it. For example, when used as a logical operator, A + B' + C means A OR NOT B OR C The behavior of the OR operator is described in the table below: Table 2.3 The OR Operator A
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A+B
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0 0 1 1

0 1 0 1

0 1 1 1

In evaluating complex Boolean expressions, the operator precedence is the same as it is in major programming languages such as C++ and Java. Specifically, you would: 1. 2. 3. 4. perform computations in parentheses before any other computations perform the NOT operations perform the AND operations perform the OR operations

For example, you would evaluate the expression M = A + B'(A(C + D)) by following the five steps below: 1. 2. 3. 4. 5. compute compute compute compute compute the the the the the value value value value value in the inner parentheses (C OR D) in the outer parentheses (A AND (C + D)) B' B' AND (A(C + D)) A OR B'(A(C + D))

In the truth table below, the four leftmost columns are all possible combinations of A, B, C, and D, and the five rightmost columns represent the results of the five steps. Table 2.4 Truth Table for A + B'(A(C + D)) A B C D Step 1 Step 2 Step 3 Step 4 Step 5 (C + D) (A(C + D) B' B'(A(C+D)) A + B'(A(C+D))

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

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0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

The AND, OR, and NOT operators obey the identities listed in table 2.5. Table 2.5 Basic Laws Relating to Boolean Functions (In these laws, the NOT function is represented by an apostrophe.) Identity Laws a +0 =a a 0 =0

Idempotent Laws

a +1 =1

a 1 =a

Complement Laws

a + a' = 1

a a' = 0

Commutative Laws

a +b =b +a

a b =b a

Associative Laws

a + (b + c) = (a + b) + c

a (b c) = (a b) c

Distributive Laws

a (b + c) = a b + a c

a + b c = (a + b) (a + c)

DeMorgan's Law

(a + b)' = a' b'

(a b)' = a' + b'

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Double-Negative Law

(a')' = a

Using these laws, we can manipulate Boolean functions in the same way that we can manipulate ordinary algebraic equations. You will not be required to memorize these laws, but they will be helpful in working with Boolean functions. Boolean algebra is used to: express algebraically a relationship between binary variables (a truth table) express algebraically the input-output relationship of a logical diagram find a simpler circuit for a function We will be using Boolean functions and some of the basic laws throughout this module. Truth-Table and Minterms Truth-table analysis is a method for analyzing complex Boolean expressions. A truth table for a Boolean expression presents a systematic listing of all the possible combinations of values of the variables on the left, and the corresponding computed values of the Boolean expression on the right. Each of the possible combinations of values of the input variables in the truth table is called a minterm. Consider a three-variable function where A, B, and C are the inputs and the output is M: M = A'B'C' + A'B'C + A'BC' + AB'C' Note: despite the complexity of the Boolean function in the example above, the value of M will always be equal to either 1 or 0, based on the values of the input variables. We can create the three-variable truth table for M by following the steps below: 1. List in the leftmost column the numbers from 0 to 2N-1, where N is the number of variables. These numbers are the decimal equivalents of the minterms. 2. Provide an input column for each variable, and fill in each row of the input columns with the binary representation of the minterm row number. 3. Compute the output values for each minterm by substituting the input values for each minterm into the expression. For example, when A = 0 (thus, A' = 1), B = 0 (thus, B' = 1), and C = 0 (thus, C' = 1), the value of M is 1, as shown below: M = 111 + 110 + 101 + 011 = 1 + 0 + 0 + 0 = 1 and when A = 1 (thus, A' = 0), B = 1 (thus, B' = 0), and C = 0 (thus, C' = 1), the value of M is 0, as shown below: M = 001 + 000 + 011 + 101 = 0 + 0 + 0 + 0 = 0 Try to do the calculations for the other six minterms, and check your results against the truth table below. Table 2.6 Three-Variable Truth Table for
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M = A'B'C' + A'B'C + A'BC' + AB'C' Minterm Inputs Output

A B C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

There are several interesting points about table 2.6: The minterms run sequentially from 0 to 7, which is the standard way that the truth tables are set up. The rightmost input column alternates 0s and 1s; the second column to the left alternates 0s and 1s in groups of two; and the third column to the left alternates 0s and 1s in groups of four. (If a fourth column existed, it would alternate sets of 0s and 1s in groups of 8, and a fifth column would alternate in groups of 16.) By noting this arrangement, we can create a consistent set of inputs for any truth table by simply following the pattern. In section C of this module, we will build the circuit represented by the equation and truth table above.

B. Karnaugh Maps
The Karnaugh map is a graphical representation of truth tables useful in simplifying a Boolean function, and is often abbreviated simply as K-map. It is a tool that makes it easy to simplify expressions that involve a small number of variables (six or fewer).

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The underlying assumption of Karnaugh-map simplification is that adjacent squares represent minterms that differ by only one bit. These groups of adjacent squares can be represented by fewer variables. For example, ABC + ABC' can be represented by: AB, which is equal to AB(C + C') An equation with fewer variables can be implemented with fewer gates. Thus, ABC + ABC' requires one OR gate, two AND gates, and a NOT gate, whereas AB can be implemented with one AND gate. Four- and three-variable K-maps are shown in tables 2.7 and 2.8 below. Each minterm cell from these K-maps contains the following information in order to relate the K-map to the truth table: algebraic values of the minterma combination of the row and column headings. For example, AB'C'D is in the AB' row and the C'D column. binary input equivalent of the mintermsthe input values for the row of the truth table that is equivalent to the minterm cell in the K-map. For example, the 0001 cell is used for the output from the truth table row with those inputs. Note that a noncomplemented input variable is represented by a 1 (A and D in the AB'C'D minterm cell), and a complemented input variable is represented by a 0 (B' and C' in the AB'C'D minterm cell). decimal equivalent of the mintermsthe decimal value of the binary input. For example, K-map cell AB'C'D with a binary input value of 1001 has a decimal equivalent of 9. Table 2.7 Four-Variable K-Map All Possible Combinations of Values of C and D

C'D' 00

C'D 01

CD 11

CD' 10

All Possible Combinations A'B' of Values of A and B 00

A'B'C'D' 0000 0

A'B'C'D 0001 1

A'B'CD 0011 3

A'B'CD' 0010 2

A'B 01

A'BC'D' 0100 4

A'BC'D 0101 5

A'BCD 0111 7

A'BCD' 0110 6

AB 11

ABC'D' 1100 12

ABC'D 1101 13

ABCD 1111 15

ABCD' 1110 14

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AB' 10

AB'C'D' 1000 8

AB'C'D 1001 9

AB'CD 1011 11

AB'CD' 1010 10

If you examine the four-variable Karnaugh map layout above, you will see the following symmetries: All cells in the bottom two rows contain A. All cells in the top two rows contain A'. All cells in the middle two rows contain B. All cells in the top row and bottom row contain B', and thus, the rows are considered adjacent rows. All cells in the right two columns contain C. All cells in the left two columns contain C'. All cells in the middle two columns contain D. All cells in the rightmost and leftmost columns contain D', and thus, the columns are considered adjacent columns. Table 2.8 Three-Variable K-Map All Possible Combinations of Values of B and C

B'C' 00

B'C 01

BC 11

BC' 10

All Possible A' Values of A 0

A'B'C' 000 0

A'B'C 001 1

A'BC 011 3

A'BC' 010 2

A 1

AB'C' 100 4

AB'C 101 5

ABC 111 7

ABC' 110 6

The three-variable K-map is a simpler version of the four-variable K-map. If you examine the three-variable K-map layout above, you will see the following symmetries: All cells in the bottom row contain A. All cells in the top row contain A'. All cells in the right two columns contain B. All cells in the left two columns contain B'. All cells in the middle two columns contain C. All cells in the rightmost and leftmost columns contain C', and thus, the columns are considered adjacent columns. The underlying assumption of K-map simplification is that adjacent cells represent minterms that differ by only one bit. These groups of adjacent cells can be clustered into groups that can be represented by fewer variables. Any cluster of two cells leads to the elimination of one variable. Any cluster of four cells leads to the elimination of two variables.
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Any cluster of eight cells leads to the elimination of three variables. All clusters that can be formed are called prime implicants. To derive the simplest function, prime-implicant clusters in which all cells are included in another prime implicant are dropped. The remaining prime implicants, which then include all the cells with a 1, are called essential prime implicants. Using the binary minterm identifications from table 2.8, consider the circled minterms 010 and 110, which are adjacent cells in the three-variable K-map shown in table 2.9. Table 2.9 K-Map with a Two-Cell Prime Implicant

These terms, A'BC' and ABC', yield BC' when clustered together. We obtain BC' because both minterms are in the rightmost column of the K-map shown in table 2.9. The K-maps shown in tables 2.10 and 2.11 give examples of four-cell and eight-cell prime implicants. In the K-map in table 2.10 (with a four-cell implicant), the circled cluster is in the top two rows, which represent A', and the middle two columns, which represent D; thus, the prime implicant is A'D. Table 2.10 K-Map with a Four-Cell Prime Implicant

In the K-map with an eight-cell implicant, in table 2.11 below, the circled cluster is in the bottom two rows, which represent A. Table 2.11 K-Map with an Eight-Cell Prime Implicant

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In the K-map below for the function B'D', the four corners are a valid grouping because the top row and bottom row represent B', and the rightmost and leftmost columns represent D' for a prime implicant of B'D'. Table 2.12 K-Map for the Function B'D'

Don't Cares The truth tables that we have looked at so far have output values of 1 or 0. The 1 tells us that the minterm is included in the solution to the Boolean expression. The 0 tells us that the minterm is not included in the solution to the Boolean expression. Another condition known as "don't care," and represented by an X, is allowed. "Don't care" conditions occur when one can guarantee that certain input combinations will not occur. For example, if the input is a binary-coded decimal (BCD) digit with possible values of 0000 to 1001, inputs from 1010 through 1111 (decimal 10 to 15) will not occur. For such inputs, we can specify any convenient output. Procedure to Simplify Expressions Using K-Maps We can use the following procedure to simplify a logic expression using K-maps: 1. Write a 1 , 0, or X in each minterm cell of the K-map based on the truth-table values. 2. Create clusters of adjacent minterm cells of two, four, or eight 1s on the map. You may count all occurrences of X as 1s if doing so will help form larger clusters. No cluster may contain a 0, and the clusters may overlap. 3. Determine prime implement clusters and eliminate those in which all 1s are covered by another prime implement cluster. The remaining prime implement clusters are the essential prime implement clusters that cover all 1s in the K-map. For example, in table 2.13 below, there are three prime implicants:

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A'C' = A'B'C'D' + A'B'C'D + A'BC'D' + A'BC'D, using an X to complete the cluster circled in blue highlight BCD = A'BCD + ABCD, using the 1s circled in red highlight A'BD = A'BC'D + A'BCD, using the 1s circled in green highlight and two essential prime implicants: A'C' BCD Note: A'BD is not used as an essential prime implicant because both of its 1s are included in other prime implicants. Also, the X at AB'CD' is not used because it does not help simplify the function. 4. Logically OR the variable expressions that remain to form the simplified minterm expression. The K-map below demonstrates this procedure. For this simplification, it is not important that you understand why the 1s, 0s, and Xs are there; you just need to know how to create the clusters to simplify the K-map. Table 2.13 K-Map Simplification

C. Basic Combinational Logic

Logic Gates We will now discuss combinational logic, starting with the most basic combinatorial components, simple logic gates. These gates directly correspond to simple Boolean functions and are the fundamental building blocks from which the entire computer is built. There are three basic gates: AND, OR, and NOT. Three additional gatesNAND, NOR, and XOR are simple combinations of the three basic gates. Because these six gates are the primary gates used in digital computers, we will look at them closely in figure 2.1 below. Note that NAND is the negation of ANDreflected both in the name and the graphic symbol. NAND stands for "Not AND." Look carefully at the symbol for the NAND gate. You should recognize that this symbol actually consists of the symbol for the AND gate followed by an inverter symbol, which explains the working of the NAND gateit is an AND followed by a NOT. Likewise, the NOR is the negation of OR, reflected both in the name and the graphic symbol. NOR stands for "NOT OR." Its symbol consists of the symbol for the OR gate followed by an inverter symbol.
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The XOR gate is also known as the EXCLUSIVE-OR gate or the EXOR gate. The six gates have varying numbers of inputs, shown to the left of the gates in the figure 2.1 diagrams, but they all have a single output shown to the right of the gates. The NOT gate is the only gate with a single input. The other five gates have a minimum of two inputs. Examine how each of these gates works in the interactive examples of figure 2.1 below. Figure 2.1 The Six Major Logic Gates

The NOT gate, or inverter, provides an output state opposite to that of its input state. Click here to see how a NOT gate works.

The OR gate provides an output of 1 if any of the inputs are equal to 1. Click here to see how an OR gate works.

The NOR gate provides an output of 1 if and only if both of the inputs are equal to 0. It is the exact opposite of the OR gate and is represented by an OR gate with a circle at the output. Click here to see how a NOR gate works.

The AND gate provides an output of 1 if and only if all of the inputs are equal to 1. Another way of looking at it is that any 0 input will force a 0 output. This latter approach will be useful when tracking signals through a circuit. Click here to see how an AND gate works.

The NAND gate provides an output of 1 if any of the inputs are equal to 0. It is the exact opposite of the AND gate and is represented by an AND gate with a circle at the output. That circle is an inverter. Click here to see how a NAND gate works.

The XOR, or EXCLUSIVE-OR, gate provides an output of 1 if and only if an odd number of the inputs are equal to 1. It is represented by an OR gate with a second line to the left of the line where the inputs enter the gate. Click here to see how an XOR gate works.

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Truth tables for the NOT, AND, and OR gates are the same as the truth tables for those logical operators in tables 2.1, 2.2, and 2.3. The outputs are always displayed in the rightmost column in those tables. Truth tables for the NAND, NOR, and EXOR gates are shown below in tables 2.14, 2.15, and 2.16, respectively. These truth tables will be useful when we do circuit tracing later in the module. Table 2.14 Truth Table for the NAND Gate Inputs A 0 0 1 1 B 0 1 0 1 Output (AB)' 1 1 1 0

Table 2.15 Truth Table for the NOR Gate Inputs Output

(A + B)' 1 0 0 0

0 0 1 1

0 1 0 1

Table 2.16 Truth Table for the XOR Gate Inputs A 0 0 1 1 B 0 1 0 1 Output AB 0 1 1 0

Although the six gates and their characteristics embody a lot of information, many of the characteristics are related. Once you understand the operation of the gates, you will find that remembering the information is relatively easy. Translating a Boolean Expression into a Simple Circuit

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We have now learned enough to use the Boolean functions and the truth tables above to build a simple circuit that performs that function. The circuit will use three of the six gates that we described above. The procedure we will use is a simple approach for designing a circuit that creates the specified Boolean function. The function that we will create is given below: M = A'B'C' + A'B'C + A'BC' + AB'C' This function is read, with parenthesis added for clarity, as: (NOT A AND NOT B AND NOT C) OR (NOT A AND NOT B AND C) OR (NOT A AND B AND NOT C) OR (A AND NOT B AND NOT C) Therefore, the "+"s in the function are read as ORs. The order of computation that we stated in section 1-A of this module was NOT, then AND, then OR. If we start with the output, however, we can work backwards (OR, then AND, then NOT) to build the circuit by following these three steps: 1. First, we draw an OR gate with four inputs: Figure 2.2 Logic Diagram: OR Gate with Four Inputs

2. Next, we draw four AND gates to implement the four AND operations: Figure 2.3 Logic Diagram: OR and AND Gates

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3. Finally, we add inverters when a complemented input is required, then tie together all the A, B, and C inputs. Note: At this point, we come upon a complication caused by circuit lines crossing one another. The solution is to use the rule that when interconnected lines cross, they are connected by a dot. If lines crossing each other are not connected by a dot, they are assumed to carry different signals. Figure 2.4 Complete Logic Diagram

We can prove that this circuit works by substituting the values A = 1, B = 0, and C = 0 into the circuit. This is called circuit tracing. Circuit tracing is a technique used to show how a set of inputs is translated into an output. It is performed by assigning input values at the first set
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of gates, then calculating the output from those gates, which become the input to the next set of gates. When the circuit is completed, you can see how the signal has moved through the circuit to form an output. The truth table predicts that the output will be 1. You can use the interactive diagram below to try out the input set A = 1, B = 0, and C = 0 that we recommended in the above paragraph, and any other set of inputs from the truth table. Figure 2.5 Circuit Tracing Description: A, B, and C represent the inputs to the gates. When you select values for each of the three data inputs and click on the "Try It" button, you will see the resulting path highlighted. Experiment with this interactive circuit tracer to see how the circuits and resulting outputs change. (Note that a dotted line represents a negated input.) Try several sets of inputs to prove that the circuit matches the equation. A= 0 B= 0 Try It C= 0

Alternative Approaches for Creating Circuits The circuit that we created above is in the sum-of-products (SOP) form, also known as disjunctive normal form (DNF), because it was built with AND gates inputting to an OR gate for the circuit output. This circuit can also be built by substituting a NAND gate for each of the AND and OR gates. Another approach is to use the M = 0 minterms in the truth table to create a product-of-sums (POS) solution. A POS circuit could be built with OR gates inputting to an AND gate for the circuit output. This circuit could also be built by substituting NOR gates for each of the OR and AND gates. To create a POS circuit for the truth table in section 1-A, do the following:
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Write an equation for M' (M prime) using all of the 0 outputs from the last truth table in section I-A: M' = A'BC + AB'C + ABC' + ABC Use DeMorgan's Laws to convert M' to M: M = (A + B' + C')(A' + B + C')(A' + B' + C)(A' + B' + C') Note: In doing this conversion, the ANDs become ORs and vice-versa, and the complemented variables become uncomplemented, and vice-versa. Create the POS circuit using the following steps: 1. 2. 3. 4. draw an AND gate with four inputs, one for each set of parentheses draw four OR gates to implement the inputs for the AND gate add inverters as required for the OR operations provide the three inputs to either inverters or the OR gates as required

We can prove that this equation is equal to the original M equation by creating the POS truth table below and by showing that its output is equal to the output of the SOP truth table created in section I-A. Table 2.17 Comparing POS and SOP Outputs Inputs Intermediate Values Outputs

A B C (A+B'+C') (A'+B+C') (A'+B'+C) (A'+B'+C') POS SOP

0 0 0 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

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The 0's and X's in the truth table are also 0's and X's in the K-map. X's in the K-map may be considered to be either 1's or 0's in both the SOP and POS solutions. It should also be noted that either the SOP circuit or the POS circuit could be the simpler circuit, i.e., the circuit with the fewest components.

D. Some Important Combinational Circuit Building Blocks

In this section, we discuss multiplexers, decoders, half adders, and full adders, all of which are combinational circuits that provide important building blocks for building larger circuits such as the central processing unit (CPU) and memory. Multiplexers This is the first of several sections describing more complex digital components. These components are commonly used in system design. The most important facts about multiplexers (often abbreviated as MUXs) are: A simple MUX will always have one output and two sets of inputs. One set of inputs comprises "inputs," and the other comprises "selects." A MUX with 2n inputs will have n selects. The MUX functions as a "rotary switch," connecting the single input line selected by the "selects" to the outputi.e., the output of the MUX will be identical to the input line that is specified by the selects. A MUX is said to "select" one of its inputs. The MUX may include an enable input that must be activated for the MUX to work. If the enable input is not activated, the output of the MUX is always 0. Experiment with the interactive version of the 4-to-1 line multiplexer below. By entering different values for S0 and S1 and clicking on the Try it button, you can see how the selected input appears at the output, Y. Figure 2.6 4-to-1 Line Multiplexer If If If If S1 S1 S1 S1 = 0 and = 0 and = 1 and = 1 and S0 S0 S0 S0 = 0, = 1, = 0, = 1, then Y then Y then Y then Y = I0. = I1. = I2. = I3.

S1 = 0 Try It

S0 = 0

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MUXs are used: in constructing buses (a bus is a connection mechanism) whenever a single terminal must obtain one out of several possible inputs (the words to multiplex have become synonymous with the process of using a single wire to carry many signals) Decoders The most important facts about decoders that you should remember are: A decoder with n inputs will have 2n outputs. The size of a decoder is determined by specifying either the number of inputs or the number of outputs. At a given time, if the decoder is enabled, only one output of the decoder will be 1, whereas all other outputs will be 0. The output equal to 1 will correspond to the binary number represented by the input. For example, if the four inputs are 1101, then output number 13 (binary 1101 = decimal 13) will be 1, whereas all others will be 0. It is important that there be no ambiguity about which input represents the most significant bit (MSB). We will usually rely on subscripts: a subscript of 0 (e.g., I0) will usually denote the least significant bit (LSB), whereas the largest subscript will denote the MSB. The decoder may include an enable input. If the decoder is not enabled, all outputs will be 0, regardless of the inputs, which therefore become don't cares. Below is an interactive version of a 3-to-8 line decoder (without the enable line). When you select values for each of the three data inputs and click on the Try It button, you will see the resulting path highlighted. Experiment with this interactive version of the decoder by giving different values to A2, A1, and A0. (Note that a dotted line represents a negated input.) Figure 2.7 A 3-to-8 Line Decoder A2 = 0 Try It
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A1 = 0

A0 = 0

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Decoders are used to: implement combinational circuits form the addressing circuitry of read-only and random access memories (described in module 3) control the chip enables of other integrated circuits during the process of building bigger circuits from smaller ones Half-Adders and Full-Adders Two other combinational circuits used in digital computers are the half-adder and the fulladder. The half-adder, used to add two inputs, provides a sum output and a carry output. The half-adder gets its name from the fact that it does only part of the addition taskit does not consider the carry from the previous column. A second half-adder is required to handle the carry from the previous column. A full-adder is constructed from two half-adders that are connected. A half-adder can be described using the truth table below. The inputs are A and B, and the outputs are the sum and the carry to the next bit (known as the carry-out.) Table 2.18 Truth Table for a Half-Adder Circuit A B CarryOut Sum

1
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The outputs are the result of adding the inputs. It is interesting to note that the sum output is identical to the output of an XOR gate, and the carry-out output is identical to the output of an AND gate. Thus, we can draw the half-adder as shown below: Figure 2.8 Circuit Diagram for a Half-Adder

The half-adder may also be represented by the block diagram shown below: Figure 2.9 Block Diagram for a Half-Adder

To perform a full additionadding two bits plus the carry from the previous bit (carry-in)a full-adder is required. The block diagram for a full-adder is shown below: Figure 2.10 Block Diagram for a Full-Adder

The half-adders and full-adders shown above are one-bit adders. For a computer with n-bit words, there would be n of the adders required to add two n-bit words.

E. Arithmetic Logic Unit (ALU)

The next circuit we will investigate is an ALU, a computational unit that can perform any one of several types of arithmetic or logical computations. The type of computation performed is specified by the control circuitry of the computer through a binary input to the decoder section of the ALU. The decoder then activates the appropriate circuitry inside the ALU. We will study the one-bit ALU shown below. A set of n one-bit ALUs would be used to process
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n-bit words in the computer. Our ALU has:

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n-bit words in the computer. Our ALU has: two data inputs, A and B, on the left side of the ALU a carry-in input from the prior bit on the left side of the ALU two selector inputs, I0 and I1, on the bottom of the ALU that go to the decoder portion of the ALU a carry-out output on the right side a data output on the right side Figure 2.11 A One-Bit ALU

Our ALU has four functions: A AND B A OR B NOT B A plus B plus carry-in In practice, ALUs may have 8, 16, or 32 functions. Using the figure above, let's look at the overall operation of the ALU and then look at each of the four functions in detail. The ALU Decoder The decoder section includes Gates 3, 4, 5, and 6 and their associated inverters (NOT gates). The four functions and the decoder section inputs/outputs for each function are shown in the table below: Table 2.19
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ALU Decoder Inputs and Outputs Inputs Function I1 I0 Gate 3 Gate 4 Gate 5 Gate 6 Decoder Outputs

AB (AND)

A + B (OR)

B' (NOT)

A plus B plus carry-in from the prior bit

ALU Output Gate 13 always has the output of the ALU, and Gate 11 has the carry-out if there is an addition performed. Gate 13 is an OR gate that always has three 0 inputs for the inactive sections of the ALU and one input for the activated sectionthe section that has a 1 input from the decoder section. ALU Operation To provide the desired result, the ALU decoder section activates the appropriate intermediate gate. This intermediate gate allows the computational gate's result to flow through to the output gates. The flow for each type of computation is shown below: Table 2.20 Activated Gates in the ALU Function Decoder Computational Intermediate Gate Gate Gate Output Gates

AB (AND)

Gate 3

Gate 1

Gate 7

Gate 13

A + B (OR)

Gate 4

Gate 2

Gate 8

Gate 13

B' (NOT)

Gate 5

Inverter

Gate 9

Gate 13

A plus B

Gate 6

Gate 10 and half-adders

Gate 12

Gate 13 and Gate 11

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1 and 2

(carry-out)

Having seen the role of the various gates in the ALU, let's look at the table below to see a set of inputs and the resulting outputs. You should be able to use the interactive version of the ALU above to verify the results. Table 2.21 Typical ALU Inputs and Outputs Inputs Outputs

I1

I0

Carry-in

Carryout

Output

The combination of inputs shown above is only a sample of the 32 (25) possibilities. It is easy to see the results of the logical operations; seeing the results of the addition is more difficult. A simple way to determine the output for addition is to add A, B, and the carry-in, and then to express the result as a two-bit binary number with the carry-out as the MSB. Thus, for the case shown in on the last line of the table above: A + B + carry-in = 1 + 0 + 1 = decimal 2 or binary 10

II. Sequential Circuits

A. Flip-Flops
Combinational circuits will change their output every time an input is changed. Sequential circuits, on the other hand, use a special kind of circuit called a flip-flop to keep values from changing until a specific set of actions occur to change them. Flip-flops are thus the building blocks of sequential circuits, which are, in essence, one-bit memories. The outputs of the sequential circuit and the values that will be stored in the flip-flops both are functions of: inputs to the circuit the old value of the flip-flops All but the simplest sequential circuits involve the presence of a clock, which is simply a periodic rectangular waveform (between the 0 and 1 levels). A typical clock signal is shown
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below: Figure 2.12 Clock Signal

The clock is what provides the sense of sequencethat is, the notion of one thing happening after another, in sequential circuits. Clocks are usually generated using special oscillator circuits. RS Latch The simplest flip-flop, a Reset-Set (RS) Latch, consists of a pair of NOR gates with feedback, as shown below. A similar flip-flop, the SR Latch, consists of a pair of NAND gates with feedback. We will use the RS Latch in this course. An RS latch or an SR latch is at the heart of each of the more complex kinds of flip-flops. Figure 2.13 RS Latch

It is important that you understand the following terminology commonly used with flip-flops: The state of a flip-flop is the current value being stored, which is the value of its output, designated as Q. If Q = 1, the flip-flop is said to be in a 1 (or set) state. If Q = 0, the flip-flop is said to be in a 0 (or reset) state. Flip-flops traditionally have two outputsthe current output value Q, and a complemented output Q'. Flip-flops in a circuit are usually given alphabetic names (A, B, C1, and so on). The Q output of the flip-flop with name A is also usually labeled just A (instead of QA ). That is, the name of the flip-flop is also given to its Q output. You may want to study the NOR truth table presented in section I-C of this module before continuing with the discussion of how a flip-flop works. The interactive diagram below steps you through the operation of an RS latch. In the diagram, Q0 is used to show no change in the state from the prior state. Figure 2.14 Operation of an RS Latch
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The last four RS latch truth tables in the RS latch interactive diagram above are the same except that different rows were highlighted. From these truth tables, we can create an RS latch excitation table that describes the inputs required to move from the present state, Q(t), to the desired next state, Q(t + 1). Excitation tables are used during the design of sequential circuits to find the flip-flop input conditions that will achieve the desired output. The table below is the excitation table for an RS latch. Table 2.22 Excitation Table for an RS Latch Desired Outputs Latch Inputs

Q(t)

Q(t+1)

Note the two Xs, which indicate don't cares. In those cases, the result is the same whether the input is a 0 or a 1. There are two problems with the RS latch: 1. The output when R = S = 1 is undefined. 2. No method exists to control when the state changes, because there is no clock pulse.
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JK Flip-Flop There are two types of JK flip-flops: the basic JK flip-flop and the master-slave JK flip-flop. The basic JK flip-flop improves on the RS latch by adding a clock pulse input and two AND gates to control the inputs to the RS latch. The master-slave JK flip-flop further improves on the RS latch by defining the output when J = K = 1. For simplicity, we will demonstrate the operation of a JK flip-flop using the following four items: 1. the circuit diagram of figure 2.15, to show the main components of a basic JK flip-flop, including: an RS latch with NOR gates 1 and 2 a clock input to generate a pulse for control of the flip-flop timing AND gates 3 and 4 to inhibit the operation of the flip-flop when the clock pulse is not present 2. the block diagram of figure 2.16, showing J, K, and clock inputs, and Q and Q' outputs. 3. the master-slave JK flip-flop truth table in table 2.23 with J, K, and clock inputs, and Q output. (The Q' output is not shown because it is simply the complement of Q.) Most textbooks use this truth table for the JK flip-flop. 4. the master-slave JK flip-flop excitation table in table 2.24. Most textbooks use this excitation table for the JK flip-flop. Figure 2.15 JK Flip-Flop Circuit Diagram

Figure 2.16 JK Flip-Flop Block Diagram

Table 2.23 Master-Slave JK Flip-Flop Truth Table Pass your mouse over the buttons in the right column to see the explanations for the JK flip-flop truth table. Inputs
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Clock

Q0

Explanation

Q0

Explanation

Explanation

Explanation

Q0'

Explanation

The undesirable feature of the basic JK flip-flop is that when J = K = clock = 1, the outputs Q and Q' are both 0, which we do not want to happen. Worse yet, if the clock changes from 1 to 0 while J = K = 1, both Q and Q' will become 1. Because these are connected to the inputs of NOR gates 2 and 1 respectively, Q and Q' will become 0. The circuit will oscillate erratically, and may or may not eventually settle down into one of its two stable states. This behavior is not acceptable. The solution to this problem is found in the design of the master-slave JK flip-flop. A masterslave JK flip-flop consists of two basic JK flip-flops, with the outputs of the first (master) connected to the inputs of the second (slave), and with some other connections. The operation of the resulting circuit is complex, but the end result is that if J = K = 1, the arrival of a clock pulse causes the output to reverse its state. The excitation table for a master-slave JK flip-flop is shown in table 2.24 below: Table 2.24 Excitation Table for a Master-Slave JK Flip-Flop Desired Outputs Flip-Flop Inputs

Q(t)

Q(t+1)

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The D Flip-Flop The D, or data, flip-flop modifies the basic JK flip-flop by inserting an inverter between the J and K inputs. (Thus, the pathological condition J = K = 1 cannot occur.) The following additional inputs can be provided: LD (load data)loads data when LD = 1 and the clock pulse = 1 SETsets the output to 1 CLR (clear)clears, or resets, the output to 0 We demonstrate the operation of a D flip-flop using the following four items: 1. the circuit diagram of figure 2-17, to show the main components of the D flip-flop, including: an RS latch with NOR gates 1 and 2 a clock input to generate a pulse for control of the flip-flop timing AND gates 3 and 4 to inhibit the operation of the flip-flop when the clock pulse is not present An inverter (NOT gate) to guarantee that the J and K inputs do not have the same values 2. the block diagram of figure 2-18, showing the D and clock inputs, and Q and Q' outputs. 3. the D flip-flop truth table in table 2.25 with D and clock inputs, and Q output. (The Q' output is not shown since it is simply the complement of Q.) 4. the D flip-flop excitation table in table 2.26. Figure 2.17 D Flip-Flop Circuit Diagram

Figure 2.18 D Flip-Flop Block Diagram

Table 2.25 D Flip-Flop Truth Table

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Pass your mouse over the buttons in the right column to see the explanations for the D flip-flop truth table. Inputs Output

Clock

Q0

Explanation

Explanation

Explanation

The excitation table for a D flip-flop is shown below: Table 2.26 Excitation Table for a D Flip-Flop Desired Outputs Flip-Flop Input

Q(t)

Q(t+1)

T Flip-Flops The T, or toggle, flip-flop consists of a master-slave JK flip-flop in which both J and K are connected to the T input. if the T input is 0, the state doesn't change, and if the T input and clock pulse are both 1, the output is the complement of the previous state. We demonstrate the operation of a T flip-flop using the following four items: 1. the circuit diagram of figure 2-19, to show the main components of the T flip-flop, including: an RS latch with NOR gates 1 and 2
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a clock input to generate a pulse for control of the flip-flop timing AND gates 3 and 4 to inhibit the operation of the flip-flop when the clock pulse is not present The J and K inputs tied together so that they have the same values 2. the block diagram of figure 2-20, showing the T and clock inputs, and Q and Q' outputs 3. the T flip-flop truth table of table 2.27 with T and clock inputs, and Q output. (The Q' output is not shown because it is simply the complement of Q.) 4. the T flip-flop excitation table of table 2.28 Figure 2.19 T Flip-Flop Circuit Diagram

Figure 2.20 T Flip-Flop Block Diagram

Table 2.27 T Flip-Flop Truth Table Pass your mouse over the buttons in the right column to see the explanations for the T flip-flop truth table. Inputs Output

Clock

Q Explanation

Q0

Q0

Explanation

Q0'

Explanation

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The excitation table for a T flip-flop is shown below: Table 2.28 Excitation Table for a T Flip-Flop Desired Outputs Flip-Flop Input

Q(t)

Q(t+1)

Note the noncombinational behavior of flip-flops. For example, with a JK flip-flop having J = K = 0 as its inputs, either a 1 or a 0 could be the output, depending on whether the current state is 1 or 0. The output does not depend only on the inputs. You may have noticed that in the basic JK flip-flop and the D flip-flop, if the values of the inputs change while the clock is 1, the outputs of the flip-flop change with the inputs. This is called level-triggered behavior. With additional circuitry, it is possible to design edgetriggered flip-flops. Edge-triggered flip-flops sample the inputs on the positive (rising) edge or the negative (falling) edge of the clock. Using edge-triggered flip-flops is one solution to the problem of unstable oscillations that would result if flip-flop outputs are fed back to inputs. All the flip-flops we will encounter in our course are edge-triggered flip-flops. Positive-edge-triggered flip-flops are denoted by a triangle next to the clock input. A circle next to the triangle indicates that the flip-flop is negative-edge-triggered. We will use positive-edge-triggered flip-flops throughout these modules. The RS, D, T, and JK flip-flop inputs are all called synchronous inputs because the flip-flops use the input values that exist at the (positive) edge of the clock to determine the next state (as specified by the excitation table). The values of these inputs at other points along the clock cycle do not matter. Many flip-flops also have asynchronous preset (pr) and clear (clr) terminals that immediately force the output of the flip-flop to 1 or 0, respectively (even if there is no clock edge at that instant). These controls are often used to ensure that flip-flops have desired values when the circuit is first powered up.

B. Equations for a General Sequential Circuit

Consider the sequential circuit below. We can use the circuit-tracing techniques learned earlier in this module to determine the output of each of the seven gates in the circuit and to
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determine the equations for DA , DB , and z that define the circuit. The interactive diagram below demonstrates how to trace the signals Figure 2.21 A Sequential Circuit With Two Inputs and Two Flip-Flops

From the last step above, we see that the equations for the circuit are: DA = Ax + A'y DB = By + B'x z =x+y

C. Some Important Sequential Circuit Building Blocks

This section discusses counters, registers, and programmable logic devices. All are sequential circuits that provide important building blocks for building larger circuits, such as the central processing unit (CPU) and memory. Counters This section is the first of several dealing with more complex sequential components. A counter is a sequential circuit with no external inputs, whose state diagram consists of simple numerically sequential transitions between states (values), as shown below: Figure 2.22 A Counter

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On successive positive edges of the clock, this counter will cycle through the states 0, 1, 2, ..., n1, 0, 1, 2, ... and so forth, for some value of n. These types of counters are often referred to as divide-by-n counters because the possible remainders, when a number is divided by n, are 0, 1, ..., n1. We will need m flip-flops to have a counter with 2m different states. If, for example, we have three flip-flops (to represent a count with states from 0 to 7), we can identify the flip-flops by A, B, and C, as we noted in the last section. On a diagram we can represent the states by bits in a circle. Thus, we would show state 3 in figure 2.22 above as a circle with 011 inside to represent the state A = 0, B = 1, and C = 1. Figure 2.23 State 3 of Counter

It is frequently desirable for the count to begin at some preset value. As we shall later see, there is an important CPU register called the program counter that is simply an up-counter that can be parallel loaded (all the bits are loaded in parallel). Counters can go up or down. We will build a 2-bit counter as a finite state machine in section III. Registers A major use of flip-flops in the computer is to provide the memory function in registers. Flipflops can store and process single bits of information. Registers contain several interconnected flip-flops and provide the ability to store and manipulate entire words. Registers may be built using any kind of flip-flop, though D-type flip-flops are used most often. Figure 2.24 shows a 4-bit register constructed from D-type flip-flops. Figure 2.24 A 4-Bit Register Using D Flip-Flops

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Programmable Logic Devices Programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) are real-world applications that can be used to realize sequential circuits. These devices are individual chips that contain a large number of combinatorial and sequential components. They can be programmed to implement combinatorial and/or sequential circuits. A large PLD or FPGA can be programmed to implement several circuits simultaneously, or one complex circuit, or even something as complex as a very simple microprocessor.

III. Finite State Machines

A. Introduction
In this section, we begin our examination of the most important kind of sequential circuit: the finite state machine. Finite state machines are so named because the sequential logic that implements them can be in only a fixed number of possible states. The counter of the previous section is a rather simple finite state machine. Its outputs and states are identical, and there is no choice of the sequence in which states are visited. A finite state machine is a tool to model the desired behavior of a sequential system. The designer first develops a finite state model of the system behavior, and then designs a circuit to implement this model. More generally, the outputs and next state of a finite state machine are combinational logic functions of their inputs and present state. The choice of the next state can depend on the value of an input, leading to more complex behavior than that of counters. Finite state machines are critical for realizing the control and decision-making logic in digital systems.

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Two convenient mechanisms for specifying the behavior of sequential circuits are the state diagram and the state table (also known as the state transition table). The state diagram graphically shows: all of the allowable states of the sequential circuit as circles (as in figure 2.23 in the prior section) the transitions between the states as directional lines between circles any inputs that control the transitions as comments on the transition lines The state table is a reformulation of the state diagram. In this table, we enter the state transitions of the state diagram and add the input values from the flip-flop excitation tables that are required for the selected flip-flops. The basic steps for designing finite state machines are: 1. Understand the problem and create the finite state machine specifications (what you want the circuit to do). 2. Create a state diagram from the system specifications. 3. Create a state table from the state diagram and the flip-flop truth excitation table. 4. Create Karnaugh maps from the flip-flop columns of the state table. 5. Derive the circuit equations from the Karnaugh maps. 6. Create the circuit from the circuit equations.

B. Finite State Machine Specifications

Perhaps the most difficult problem the novice hardware designer faces is that of mapping an imprecise behavioral specification of a finite state machine into a more precise description (for example, a state diagram). In this section, we will illustrate this process by examining a detailed case study of a two-bit binary counter. Problem Specification The task is to create a 2-bit binary counter using T flip-flops that can count in binary when a control input is set to 1. When the control input U equals 1, the counter steps through the binary sequence 00, 01, 10, 11, and repeats. When U equals 0, the counter does not change. Understanding the Specification Start by ensuring you understand the interaction of the control input and the counter's sequence. Let's label the control input as signal U and the outputs as flip-flops A and B. To check our understanding, let's write the counter sequence as the U input varies, as shown in the following table: Table 2.29 Counter Sequence with Control Inputs Current State (A B) Control Input (U) Next State (A B)

00
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00
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00

01

01

01

01

10

10

10

10

11

11

11

11

00

C. The State Diagram and the State Table

State Diagram Because all four possible states can be reached by some count sequence, you can start by tabulating the four states in a state diagram. First, draw a circle as shown below for each possible state, and put the state values for A and B in the circles. The possible states are AB = 00, 01, 10, and 11. Figure 2.25 Counter States

Complete the counter state diagram by connecting the states with a transition line containing the appropriate control input and an arrow indicating the direction of the transition. If there is no state change, the line should loop back to the same state. Figure 2.26 Counter State Diagram

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State Table We demonstrate below, in three steps, how to create a state table for the 2-bit binary counter. Step 1. We begin by filling in all possible combinations of flip-flop states (representing the present state of the flip-flops) and control inputs. In our case, there are eight combinationsfour possible states times two possible control input values. These should be arranged in order so that their binary value goes from 0 to 7 for the eight possible combinations. These combinations are highlighted in table 2.30a. Table 2.30a Creating a State TableStep 1 Present State Q(t) Control Input Next State Q(t+1) Flip-Flop Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 U 0 1 0 1 0 1 0 1 A B TA TB

Step 2.

Fill in the desired next states from the state diagram. These states are highlighted in table 2.30b below. Table 2.30b Creating a State TableStep 2

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Present State Q(t) Control Input Next State Q(t+1) Flip-Flop Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 U 0 1 0 1 0 1 0 1 A 0 0 0 1 1 1 1 0 B 0 1 1 0 0 1 1 0 TA TB

Step 3.

Input the present state and next state of the A flip-flop to the T flip-flop excitation table to compute the T A inputs. The yellow highlights of Table 2.30c indicate the present state, next state, and flip-flop inputs for flip-flop A. The green highlights do the same for the B flip-flop. Table 2.30c Creating a State TableStep 3

Present State Q(t) Control Input Next State Q(t+1) Flip-Flop Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 U 0 1 0 1 0 1 0 1 A 0 0 0 1 1 1 1 0 B 0 1 1 0 0 1 1 0 TA 0 0 0 1 0 0 0 1 TB 0 1 0 1 0 1 0 1

D. Creating Karnaugh Maps, Circuit Equations, and the Circuit

Next, we create a Karnaugh map for each of the flip-flops. For our design case, use the T A column of the state table for the A flip-flop and the T B column of the state table for the B flip-flop. Because this case is concerned with only A, B, and U, we will use a three-variable Kmap. The sequence of the state table rows makes it easier to go directly from the state table to the K-map. The small numbers at the bottom of each K-map cell represent the Present State and Control Input rows of the State Table.
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Table 2.31 K-Map for Counter Flip-Flop TA A\BU A' A B'U' 0

000

B'U 0
001

BU 1
011

BU' 0
010

0
100

0
101

1
111

0
110

Table 2.32 K-Map for Counter Flip-Flop TB A\BU A' A B'U' 0

000

B'U 1
001

BU 1
011

BU' 0
010

0
100

1
101

1
111

0
110

Next, we create the circuit equations from the Karnuagh maps. In our design case, there is one equation for A and one for B. T A = BU TB = U From the circuit equations, we can create the circuit. The circuit for our design case is shown below: Figure 2.27 Circuit for Two-Bit Binary Counter

E. Additional Practical Considerations

You have already seen how to describe finite state machines in terms of state diagrams and tables. It can be difficult, however, to describe complex finite state machines in this way. Recently, hardware designers have shifted toward using alternate representations of finite machine behavior that look more like software descriptions. Some examples are algorithmic
t ychousa12. um uc. edu/ C I S310/ 0609/ M odul s/ M 2- M odul _2/ S3- C m ent ar y. ht m l M e e om

state machine (ASM) notation and hardware description languages (HDLs). ASMs are similar to

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state machine (ASM) notation and hardware description languages (HDLs). ASMs are similar to program flowcharts, but they have a more rigorous concept of timing. HDLs look much like modern programming languages, but they explicitly support computations that can occur in parallel. You may wonder what is wrong with state diagrams. The problem is that they do not adequately capture the notion of an algorithm (a well-defined sequence of steps that produce a desired sequence of actions based on input data). State diagrams are weak at capturing the structure behind complex sequencing. The representations discussed previously do a better job of making this sequencing structure explicit. It is important to be able to convert state diagrams to sequential circuit implementations correctly. Assigning values to states is crucial in designing a finite state machine. A good assignment can significantly reduce the digital logic needed to implement the state machine, whereas a bad assignment introduces unnecessary complexity that provides no benefit in the final product. A well-designed state machine must recover effectively from being placed in an unused state. Asynchronous designs of finite state machines are possible; such designs would consist entirely of combinatorial logic. Asynchronous designs may be faster than synchronous designs, but may have other problems, such as timing and termination issues. Return to top of page
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