Digital Logic And Computer Organization UNIT IV 4.

0) Introduction
The functionality of a computer and the execution of an instruction set is controlled by the control unit. This chapter deals with the simple computer architecture and describes in detail two alternative ways in which its control section may be organized.

4.1) Objectives
In this chapter you will learn about: Introduction The Basic Concepts Hard-Wired Control Unit Micro-programmed Control Unit Microinstruction

4.2) Content
4.2.1. The Fundamental Concepts All traditional digital computers have two principal functional parts: the data path section in which processing occurs and the control section which is responsible for decoding instructions and leaving the correct sequence of control signals to make the processing happen in the data path. Basically there are two types of control units: hardwired controllers and micro-programmed controllers. In order to differentiate the functionality of the computers, a block diagram of its data path sections is shown in Figure 6.1. A single 12-bit-wide bus provides for exchange of information between pairs of registers within the data path section. The registers and the 256 X 12 bit RAM memory are controlled by 16 control signals. Most of the registers have Load (L) and Enabled (E) signals. An active L signal to a register causes the contents of the bus to be clocked into that register on the next rising pulse from the system clock. An active E signal enables the tristate outputs of the register, thereby making its contents available to the bus. Therefore, a register transfer from, for example, register A to register B would require active EA and LB control signals.

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Figure 6.1: A Simple Basic Computer. The Arithmetic-Logic-Unit (ALU), a circuit that is capable of adding or subtracting the 12-bit numbers contained in its two input registers, does processing of data: the accumulator (ACC) and register B. The operation performed by the ALU is selected by the Add (A) or Subtract (S) control signals. The accumulator also contains a single flipflop that is set whenever its contents are negative (i.e., whenever the leading bit is set-meaning a negative 2's complement number). The value of this "negative flag" provides input to the controller/sequencer and permits implementation of conditional branching instructions. The machine's RAM memory is accessed by first placing the 8-bit address in the Memory Address Register (MAR). An active Read (R) control signal to the RAM will then cause the selected word from the RAM to appear in the Memory Data Register (MDR). An active Write (W) signal, on the other hand, will cause the word contained in the MDR to be stored in the RAM at the address specified by the MAR. Since there are no input or output ports in this simple computer, all I/O is memory mapped. In other words, several memory locations are reserved for input/output devices. Memory reads from any of those locations will cause data from the corresponding input device to appear in the MDR; memory writes to them will cause data in the MDR to be sent to the corresponding output device. A word stored in any given memory location may be data to be manipulated by the computer or a coded instruction that specifies an action to be taken. The data path section also contains a Program Counter (PC) whose function it is to point to the address in RAM of the next instruction to be executed. The Increment Program

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Counter (IP) control signal causes the contents of the PC to increase by one. Since, instructions on this machine are one word long, this provides a simple mechanism for sequential instruction execution. In addition there is an Instruction Register (IR) which holds the instruction that is about to be execute and provides its opcode to the controller/sequencer.

4.2.2. The Computer's Instruction Set

An instruction on the computer consists of one 12-bit word. The leading four bits form the operation code (opcode) which specifies the action to be taken and the remaining 8 bits, when used, indicate the memory address of one of the instruction's operands. For those instructions that have two operands, the other operand is always contained within the accumulator. Table 6.1 gives eight instructions that form the instruction set chosen for the machine. Also shown in the table is the sequence of control signals necessary for execution of each of the instructions in the machine's instruction set and for fetching the next instruction.
Instruction Control Mnemonic LDA (Load A) STA (Store A) ADD (Add B to A) SUB (Sub B from A) MBA (Move A to B) JMP (Jump to Address) JN (Jump if Negative) HLT Fetch Execution Action A (Mem) Register Transfer MAR IR MDR M (MAR) A MDR MAR IR MDR A M(MAR) MDR 1. A ALU (Add) 1. A ALU (Sub) 1. B A 1. PC IR PC IR If NF set MAR PC MDR M (MAR) IR MDR Active Signals EI, LM R DE, LA EI, LM EA, LD W A, EU, LA S, EU, LA EA, LB EI, LP NF: EI, LP

(Mem) A

AA+B AAB BA PC Mem PC Mem If Negative Flag is Set Stop Clock IR Next Instruction

EP, LM R ED, LI, IP

Table 6.1. An Instruction Set For The Basic Computer In each case the register transfers required for execution of each step are shown. For example, in the case of the LDA (load accumulator) instruction, the first step consists of

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copying the address of the operand, contained in the least significant 8 bits of the instruction register, to the memory address register. Thus the EI (enable IR) and LM (load MAR) control signals are active. The next step is to read the operand from memory into the memory data register. An active R (memory read) signal performs that task. The last step required to execute the LDA instruction is to copy the contents of the memory data register to the accumulator. Active ED (enable MDR) and LA (load accumulator) do the trick. 4.2.3. Hard-Wired Control Unit Input to the controller consists of the 4-bit opcode of the instruction currently contained in the Instruction Register and the negative flag from the accumulator. The controller's output is a set of 16 control signals that go out to the various registers and to the memory of the computer, in addition to a HLT signal that is activated whenever the leading bit of the op-code is one. The controller is composed of the following functional units: A ring counter, an instruction decoder and a control matrix. Figure 6.2 is a block diagram showing the internal organization of a hard-wired control unit for the simple computer.

Figure 6.2: Block Diagram of Basic Computers Hard-wired Control Unit The ring counter provides a sequence of six consecutive active signals that cycle continuously. Synchronized by the system clock, the ring counter first activates its T0 line, then its T1 line and so forth. After T5 is active, the sequence begins again with T0. Figure 6.3 shows how the ring counter might be organized internally.

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Figure 6.3: Internal Organization of the ring counter The instruction decoder takes its four-bit input from the op-code field of the instruction register and activates one and only one of its 8 output lines. Each line corresponds to one of the instructions in the computer's instruction set. Figure 6.4 shows the internal organization of this decoder.

Figure 6.4: Hard-wired instruction decoder The most important part of the hard-wired controller is the control matrix. It receives input from the ring counter and the instruction decoder and provides the proper sequence of control signals. Figure 6.5 is a diagram of how the control matrix for the simple machine might be wired. The machine's instruction set (Table 6.1) helps to understand the control matrix.

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Figure 6.5: Hard-Wired Control Matrix Table 6. 2 shows, which control signals, must be active at each ring counter pulse for each of the instructions in the computer's instruction set and for the instruction fetch operation. The table shows the instructions in the left-hand column, which in the circuit will be shown as the output lines from the decoder. The various control signals are placed horizontally along the top of the table. Entries into the table consist of the moments (ring counter pulses T0, T1, T2, T3, T4 or T5) at which each control signal must be active in order to have the instruction executed.
Control Signal: IP LP EP LM R W LD ED LI EI LA EA A S EU LB Instruction: ---------------------------------------------------------------------------------------------"Fetch" T2 T0 T0 T1 T2 T2 LDA T3 T4 T5 T3 T5 STA T3 T5 T4 T3 T4 MBA T3 T3 ADD SUB JMP JN T3 T3 T3 T3*NF T3 T3*NF T3 T3 T3 T3

Table 6.2. Times Matrix at which Each Control Signal Must Be Active in Order to Execute the Hard-wired Basic Computer's Instructions For example, the Fetch operation has the EP and LM control signals active at ring count T0 and ED, LI and IP active at ring count T2. Therefore the first row (Fetch) of Table 2 has T0 entered below EP and LM, T1 below R and T2 below IP, ED and LI.

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Once Table 2 has been prepared, the logic required for each control signal is easily obtained by performing an AND operation is performed between any active ring counter (Ti) signals that were entered into the signal's column and the corresponding instruction contained in the far left-hand column. If a column has more than one entry, the output of the ANDs are ORed together to produce the final control signal. For example, the LM column has the following entries: T0 (Fetch), T3 associated with the LDA instruction and T3 associated with the STA instruction. Therefore, the logic for this signal is: LM = T0 + T3*LDA + T3*STA This means that control signal LM will be activated whenever any of the following conditions is satisfied: (1) ring pulse T0 (first step of an instruction fetch) is active or (2) an LDA instruction is in the IR and the ring counter is issuing pulse 3 or (3) and STA instruction is in the IR and the ring counter is issuing pulse 3. The entries in the JN (Jump Negative) row of this table require some further explanation. The LP and EI signals are active during T3 for this instruction if and only if the accumulator's negative flag has been set. Therefore the entries that appear above these signals for the JN instruction are T3*NF, meaning that the state of the negative flag must be ANDed in for the LP and EI control signals. Figure 6.6 gives the logical equations required for each of the control signals used on the machine. These equations have been read from Table 6.2, as explained above. The circuit diagram of the control matrix (Figure 6.5) is constructed directly from these equations. IP = T2 W = T5*STA LP = T3*JMP + T3*NF*JN LD = T4*STA LA = T5*LDA + T3*ADD + T3*SUB EA = T4*STA + T3*MBA EP = T0 S = T3*SUB A = T3*ADD LI = T2 LM = T0 + T3*LDA + T3*STA ED = T2 + T5*LDA R = T1 + T4*LDA EU = T3*ADD+T3*SUB EI = T3*LDA + T3*STA + T3*JMP + T3*NF*JN LB = T3*MBA Figure 6.6: The logical equations required for each of the hardwired control signals on the basic computer.

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It should be noticed that the HLT line from the instruction decoder does not enter the control matrix, Instead this signal goes directly to circuitry (not shown) that will stop the clock and thus terminate execution. 4.2.4. Micro-programmed Control Micro-programmed control for control units was first proposed in the early 1950s but was not possible at that time because of the lack of available technology. It was first implemented for the IBM 360 mainframes and was then used in many future computers once semiconductor ROMs became available. The idea behind micro-programmed control is to have the micro-operations pre-stored in a part of the control unit and to translate from instructions to micro-instructions as part of the decode process. While this requires an additional step over hardwired control units, it allows for a more cheaply defined control unit and more flexibility to alter microinstructions in an instruction set than having to create new logic in the hardwired control unit. It is also easier to define the micro-operations because of the use of microprogramming languages. Micro-programmed Control use sequences of instructions to control complex operations called micro-programming or firmware. Todays large microprocessor has many instructions and associated register-level hardware and has many control points to be manipulated. This results in control memory that contains a large number of words co-responding to the number of instructions to be executed and has a wide word width. Micro-program Word Length is based on 3 factors: Maximum number of simultaneous micro-operations supported The way control information is represented or encoded The way in which the next micro-instruction address is specified Microinstructions A microinstruction is a set of micro-operations that occurs at the same time. For instance, all events at time t1 make up a single microinstruction rather than being several microoperations. One microinstruction will be one line in a micro-program. To carry out a machine instruction or a part of the fetch-execute cycle, a micro-program is executed, consisting of one or more microinstructions. In a micro-programmed control unit, all of the micro-programs are stored in one area called the control memory, which is firmware (software permanently stored in hardware) The hardwired control unit is hardware whereas the micro-programmed control unit is firmware, which is more flexible and easier to program Control Memory Each micro-program consists of one or more micro-instructions, each stored in a separate entry of the control memory. The control memory itself is firmware, a program stored in ROM, that is placed inside of the control unit.

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...
Jump to Indirect or Execute

Fetch cycle routine

...
Jump to Execute Indirect Cycle routine Interrupt cycle routine Execute cycle begin AND routine

...
Jump to Fetch Jump to Op code routine

...
Jump to Fetch or Interrupt

...
Jump to Fetch or Interrupt ADD routine

Figure 6.7: The Control Memory Each micro-program ends with a branch to the Fetch, Interrupt, Indirect or Execute micro-program. Microinstruction Types Each microinstruction specifies single (or few) micro-operations to be performed (vertical micro-programming) and many different micro-operations to be performed in parallel (horizontal micro-programming). The features of Vertical Microprogramming are: Width is narrow n control signals encoded into log2 n bits Limited ability to express parallelism Considerable encoding of control information requires external memory word decoder to identify the exact control line being manipulated
Function Codes

Micro-Instruction Adress Jump Condition

instruction Address

Figure 6.8: Vertical Micro-programming The features of Horizontal Micro-programming are: Wide memory word High degree of parallel operations possible Little encoding of control information

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Internal CPU Control Signals

Micro-instruction Address

System Bus Control Signals

Jump Condition

Figure 6.9: Horizontal Micro-programming The Tasks done By Microprogrammed Control Unit are: Microinstruction sequencing Microinstruction execution Micro-programmed Control Unit has the Decoder that determines type of operation stored in IR. It loads control address register with the op codes micro-program starting location and loops on the following: Sequencer causes read of control memory content using address in control address register Item in control memory moved to control buffer register Contents of Control Buffer Register generate control signals and next address information Sequencer moves next address to control address register Next instruction (add 1 to current) Jump to new routine Jump to new machine routine The two concerns with grouping micro-operations into microinstructions are: Minimizing the size of the control memory Generating the next microinstruction address Determined by IR (new op code, branch to new micro-program) Next sequential entry in this micro-program Branch based on jump condition Microinstruction Addresses The Microinstruction Addresses has the sequencing techniques that have the following: Two address fields one is the next instruction, one is the branch destination. A multiplexer using the jump condition logic makes the choice. Single address field where the choice is made of whether to use the value in the address field (a branch) or increment the current address by one. Variable format two formats selected by a single microinstruction bit that denotes whether the next instruction should be used or a branch is to be taken.

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Once the microinstruction has been fetched from the control memory, it must be executed to Send control signals to CPU components Send control signals to components outside the CPU (over bus, such as memory read or write) Determine next microinstruction address If microinstructions are vertical rather than horizontal, they must first be decoded. Sometimes, these are referred to as packed vs. unpacked, hard vs soft micro-programmed or direct vs. indirect encoding. Horizontal microinstructions have lengths typically between 40 and 100 bits while vertical microinstructions have lengths typically between 16 and 40 bits and are expanded into the greater length by a decoder. Microinstruction Encoding Even horizontal microinstructions have some degree of encoding to reduce control memory width and to simplify the task of micro-programming. An instruction is generally separated into a set of fields where a control line is controlled by only a single field of the entire instruction. Encoding Design This process involves the organizing of the format of the microinstruction into independent fields and defining each field so that alternative actions within that field are mutually exclusive (that is, there is a single action performed in each field). Encoding may be done by organizing fields on the various functions performed in the machine or by having one field per resource. Another option is direct vs. indirect encoding, in indirect, one field determines the interpretation of another field. For instance, an ALU might have 8 arithmetic operations and 8 shift operations, we could use a single bit of the microinstruction to determine whether the microinstruction is arithmetic or shift and 3 bits for the actual operation type As seen earlier, the controller causes instructions to be executed by issuing a specific set of control signals at each beat of the system clock. Each set of control signals issued causes one basic operation (micro-operation), such as a register transfer, to occur within the data path section of the computer. In the case of a hard-wired control unit the control matrix is responsible for sending out the required sequence of signals. An alternative way of generating the control signals is that of micro-programmed control. In order to understand this method it is convenient to think of sets of control signals that cause specific micro-operations to occur as being "microinstructions" that could be stored in a memory. Each bit of a microinstruction might correspond to one control signal. If the bit is set it means that the control signal will be active; if cleared the signal will be inactive. Sequences of microinstructions could be stored in an internal "control" memory. Fetching the proper sequence of microinstructions from the control memory and sending them out to the data path section of the computer could then cause execution of a machine language instruction. A sequence of microinstructions that implements an Page 122

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instruction on the external computer is known as a micro-routine. The instruction set of the computer is thus determined by the set of micro-routines, the "microprogram," stored in the controller's memory. The control unit of a microprogram-controlled computer is essentially a computer within a computer. Figure 6.10 shows a block diagram of a micro-programmed control unit that may be used to implement the instruction set of the computer, described above. The heart of the controller is the control ROM memory in which 24-bit long microinstructions are stored. Each is composed of two main fields: a 16-bit wide control signal field and an 8-bit wide next-address field. Each bit in the control signal field corresponds to one of the control signals discussed above. The next-address field contains bits that determine the address of the next microinstruction to be fetched from the control ROM.

Op-code field from Instruction Register 4 Error! Bookmark not defined. Negative Flag

Address Rom 5 10 or 11 01 Multiplexer 00

Microcounter

Incrementer

Control Rom

Microinstruction Register Control Signals HLT CD

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Figure 6.10: A Micro-programmed Control Unit The following section explains the details of how these bits work shortly. Words selected from the control ROM feed the microinstruction register. This 24-bit wide register is analogous to the outer machine's instruction register. Specifically, the leading 16 bits (the control-signal field) of the microinstruction register are connected to the control-signal lines that go to the various components of the external machine's data path section. Addresses provided to the control ROM come from a micro-counter register, which is analogous to the external machine's program counter. The micro-counter, in turn, receives its input from a multiplexer which selects from : (1) the output of an address ROM, (2) a current-address incrementer or (3) the address stored in the next-address field of the current microinstruction. The logic that selects one of these three alternatives will be explained shortly. The controller's address ROM is fed by the outer computer's instruction register. The address ROM maps the op-code of the instruction currently contained in the op-code field of the instruction register to the starting address of the corresponding microroutine in the control ROM. Address zero of the address ROM contains the control-ROM address of the fetch routine; each other addresses in the address-ROM corresponds to one of the opcodes of the computer's instruction set. Table 6.3 shows the contents of the address ROM for the instruction set of the simple computer.

Instruction Mnemonic

Address-ROM Contents (Control-ROM MicroRoutine Start Address) ---------------------------------------------------------------------------------------------"Fetch" LDA STA ADD SUB MBA JMP JN Available for New Instructions 0 1 2 3 4 5 6 7 8-E 00 03 06 09 0A 0B 0C 0D 10-1E

Address-ROM Address (Instruction Op-Code)

Table 6.3: The Basic Computer's Address ROM To see how the address ROM works, let us assume that an ADD instruction has been fetched into the outer computer's instruction register. Since the op-code of the ADD instruction is 3, the number stored at location 3 of the address ROM (a 9) is the starting Page 124

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address in the control ROM of the microroutine that implements the ADD instruction. Details of a microinstruction's next address field are shown in Figure 6.8.

Figure 6.11: Next address field of the microinstrcution The CD is the condition bit, MAP causes the address of the next microinstruction to be obtained from the ROM, HLT stops the clock and CRJA is the control ROM jump address field. The 5-bit CRJA (Control ROM Jump Address) sub-field holds a microinstruction address. Thus, the address of the next microinstruction may be obtained from the current microinstruction. This permits branching to other sections within the microprogram. The combination of the MAP bit, the CD (condition) bit and the negative flag from the accumulator of the external machine provide input to the logic that feeds the select lines of the multiplexer and thereby determine how the address of the next microinstruction will be obtained. If the MAP bit is one, the logic attached to the multiplexer's select lines produces a 10 which selects the address ROM. Therefore, the address of the micro-routine corresponding to the instruction in the outer machine's instruction register will be channeled to the control ROM. It should be clear that the MAP bit must be set in the last microinstruction of the "fetch" micro-routine, since it is at that moment that the newlyfetched instruction to be executed is required. If the MAP bit is zero and the CD bit is zero, (unconditional branch), the multiplexer logic produces a 01, which selects the CRJA field of the current instruction. Therefore, the next instruction will come from the address contained in the current instruction's nextaddress field. With MAP=0 and CD=1 (conditional branch), the logic that feeds the multiplexer will produce either a 00 or a 01, depending on the value of the negative flag. If the flag is set, it is a 01, which selects the jump address contained in the current microinstruction. If the negative flag is cleared, the select lines to the multiplexer receive a 00, which causes the incrementer to be selected. The next microinstruction will come from the next address in sequence. It should be noticed that with this scheme, if no branching is done, the CRJA field should contain the address of the next microinstruction and the CD bit should be cleared. This will cause "branch to the next microinstruction" to occur. The one exception to this rule is the case of the last microinstruction within a micro-routine. It would be then required to branch back to the "fetch" micro-routine. Since this routine starts at control-ROM location 00000, that address should be contained in the CRJA field and CD should be 0. The HLT bit is used to terminate execution. If it is set, the clock that synchronizes activities within the entire machine is stopped.

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A rising clock edge and the microinstruction register trigger the micro-counter by a falling edge. Thus, on each positive edge, the micro-counter receives the address of the microinstruction and presents it to the control ROM, which has until the next negative edge to output the addressed control word to the microinstruction register. Since all operation in the data path section are positive-edge triggered, there is adequate time for the signals specified in the control word contained in the microinstruction register to go out to all sections of the external machine. The sequence of latching the address of microinstruction i+1 into the micro-counter while microinstruction i executes (positive edge) and then presenting the control word of microinstruction i+1 to the microinstruction register (negative edge) continues until a set HLT bit stops the clock. Hardwired vs. Micro-programmed Computers It should be mentioned that most computers today are micro-programmed. The reason is basically one of flexibility. Once the control unit of a hard-wired computer is designed and built, it is virtually impossible to alter its architecture and instruction set. In the case of a micro-programmed computer, however, simply altering the micro-program stored in its control memory can change the computers instruction set. In fact, taking the basic computer as an example, it is noticeable, that its four-bit op-code permits up to 16 instructions. Therefore, seven more instructions could be added to the instruction set by simply expanding its micro-program. To do this with the hard-wired version of the computer would require a complete redesign of the controller circuit hardware. Another advantage to using micro-programmed control is the fact that the task of designing the computer in the first place is simplified. The process of specifying the architecture and instruction set is now one of software (micro-programming) as opposed to hardware design. Nevertheless, for certain applications hard-wired computers are still used. If speed is a consideration, hard-wiring may be required since it is faster to have the hardware issue the required control signals than to have a "program" do it.

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4.3) Revision Points

Hardwired Control Speed Fast Control functions Implemented in hardware Flexibility Not flexible, to accommodate new system specification or new instructions Ability to handle large / Some what difficult complex instruction sets Ability to support Very difficult (unless operating systems and anticipated during design) diagnostic features Design process Somewhat complicated Applications Mostly RISC microprocessors Instructionset Size Usually under 100 instructions ROM size -------Chip area efficiency Uses least area Attribute Microprogrammed Control Slow Implemented in software More flexible, to accommodate new system specification or new instructions redesign is required Easier Easy Orderly and systematic Mainframes, some microprocessors Usually over 100 instructions 2 K to 10 K by 20-400 bit microinstructions Uses more area

No. 1. 2.

Horizontal organisation Long formats Ability to express a high degree of parallelism

Vertical organisation Short formats Limited ability to express parallel microoperations

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3. 4. Little encoding of the control information Useful when higher operating speed is desired Considerable encoding of the control information Slower operating speed

Applications: Horizontal organisation : Best suited while for high operating speed and the machine structure allows parallel usage of a number of resources. Vertical organisation: Best suited when usage of parallel architecture is not available to handle execution of microinstructions, and lower speed is acceptable.

4.4) Intext Questions

1. 2. 3. 4. Write short notes on the basic computer and its functions. What is the overall function of a processors control unit? What basic tasks does a control unit perform? Briefly explain what is meant by a hardwired implementation of a control unit.

4.5) Summary
All traditional digital computers have two principal functional parts: the data path section and the control section. Basically there are two types of control units: hard-wired controllers and microprogrammed controllers. Processing of data is done by the Arithmetic-Logic-Unit (ALU).The machine's RAM memory is accessed by first placing the 8-bit address in the Memory Address Register (MAR). The data path section also contains a Program Counter (PC) whose function it is to point to the address in RAM of the next instruction to be executed. The Increment Program Counter (IP) control signal causes the contents of the PC to increase by one. An Instruction Register (IR) holds the instruction that is about to be execute and provides its opcode to the controller/sequencer. The controller is composed of the functional units: - A ring counter, an instruction decoder and a control matrix. A sequence of microinstructions that implements an instruction on the external computer is known as a micro-routine

4.6) Terminal Exercises

1. Explain in detail the operations of a computers instructions set. 2. Explain in detail the microprogrammed control unit. Page 128

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3. Explain the differences between Hard-wired and micro-programmed computers. 4. Define microinstruction 5. Compare horizontal and vertical organisation. Give their advantages, disadvantages and their applications.

4.7) Supplementary Materials

Computer Organization & Architecture, William Stallings, Pearson Education

4.8) Assignments
Write the sequence of control steps required to perform the operation Add r1, (r2) for a single bus processor. This instruction adds the contents of Register R1 and the contents of the memory location specified by Register R2 and store the result in the register R1.

4.9) Reference Books

Computer Architecture, A quantitative Approach, third edition, John L. Hennessy, David A. Patterson.

4.10) Learning Activities

Write the sequence of control steps required to perform the operation Mul R1, R2 for a single bus processor. This instruction multiplies the contents of the registers R1 and R2 and stores the result in R2. Higher order bits in the product, if any are discarded.

4.11) Keywords
Control bus, Control path, Hardwired implementation, Micro-programmed control Control unit, Control signal, Microinstructions, Horizontal format, Vertical format.

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