HUMBOLDT-UNIVERSITT ZU BERLIN

INSTITUT FR INFORMATIK

COMPUTER ARCHITECTURE
Lecture 11

ALU (2) - Integer Arithmetic

Sommersemester 2001 Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca

CA - XI - ALU(2) - 1

ALU ARITHMETIC-LOGIC UNIT

Arithmetic Units Classification Number representations Hardware/software continuum and vertical migration Integer Arithmetic Addition/subtraction Multiplication Booth's Algorithm Bit Pair Algorithm Division Floating-point arithmetic Addition/subtraction Multiplication/division Logic functions
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ADDITION/SUBTRACTION OF POSITIVE AND NEGATIVE NUMBERS

- Sign & Magnitude (awkward +,-) - 1's complement (better). Requires a correct cycle

S t +1 = S t + C n

- 2's complement is awkward externally, but is the best hardware representation for addition and subtraction

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a) 2's Complement Addition (1) Modulo Arithmetic Positive Numbers Negative Numbers 2's complement In general 2's complement 7 + 4 = 11 -7 + (-4) = -11 (9 + 12) = 21 which is -11 in signed decimal notation (X + Y) mod 2n (9+12) mod 16 = 5 which is also 11 in decimal no change

Add 2's complement using adder as in the figure. 2 n 1 <N < + 2 n 1 Ignore carry-out bit and you have a correct answer. (2) Numbers outside the expected range cause an arithmetic overflow. b) Subtraction Subtraction is the same as performing addition of a complement. 7-4=3 is equivalent 7+12=19 in 2's complement which is 3 after ignoring the carry.
CA - XI - ALU(2) - 4

OVERFLOW
cn = 1, X + Y 2n Overflow is only possible when both operands have the same sign. Overflow occurs when the sign of S does not agree with the signs of X and Y, i.e., when the signs of X and Y are the same.

Overflow = xn-1yn-1sn-1 + xn-1yn-1sn-1

Detection method is to set a flag (V). Interrupts are sometimes allowed to occur on arithmetic overflow.

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MULTIPLICATION
"PAPER AND PENCIL METHOD"
1 x 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 0 1 Partial Product 0 (PP0) PP 1 PP 2 PP 3 q3 0 p7 p6 p5 p4 p3 q2 0 1 0 1 0 0 1 1 1 0 1 1 (13) Multiplicand M (11) Multiplier Q

1 1 1 0

(143) Product P Multiplicand m3 0 m2 0 m1 0 p0 p1 p2 q1 0 Multiplier m0 q0 0

PP4 = product

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TYPICAL CELL OF MULTIPLICATION ARRAY IMPLEMENTATION

Bit of incoming partial product (PPi)

m

j
q

Carry-out

A Sum

Carry-in

Bit of out going partial product [ PP(i+1) ]

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REGISTER CONFIGURATION FOR SEQUENTIAL CIRCUIT BINARY MULTIPLIER

A register (initially 0) SHIFT RIGHT

Multiplier Q C
an-1 a0 qn-1 q0 1 ADD 0 NO ADD

n-bit adder

ADD/NO ADD

Control sequencer

mn-1

m0

Multiplicand M
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MULTIPLICATION EXAMPLE
M 1 1 0 1 0 C 0 0 1 0 0 0 1 0 0 0 0 0 A 1 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 1 Q 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

Initial configuration

Add Shift Add Shift No Add Shift Add Shift

First cycle Second cycle Third cycle

Fourth cycle

Product PP0 is in A after the first ADD

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FLOWCHART FOR 2'S-COMPLEMENT MULTIPLICATION

Start A0 COUNT 0 V0 M multiplicand Q multiplier Yes Q(7) = 0? A COUNT COUNT+1 A(0) A(1:n-1),Q No A+M A(0) A,Q(0:n - 2)

0 1

R ... ...

A(0) Q(7)

M(0) 0

Q(7)

OUTBUS OUTBUS

A Q(0:n-1)

No

COUNT = 7? Stop Yes

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BLOCK DIAGRAM OF 2'S-COMPLEMENT FIXED-POINT MULTIPLIER

Accumulator A A(0) C0 C2 C 10 V Overflow flip-flop C6 OUTBUS INBUS C3 C10 C4 C5 C1 Multiplier Q Multiplicand M

8-bit parallel adder

C8 8 8 C0 C1 CK COUNT 6 C 10 C 11 COUNT
CA - XI - ALU(2) - 11

Q(7)

C1

C9

Data bus

START END CLOCK

Control unit

Internal control signals

PDP-11 REGISTER ARRANGEMENT FOR SOFTWARE MULTIPLY

MULTIPLIER Q R1 2 C 1 R0 SHIFT LEFT A register (initially 0)

C C Ri MSB Long Shift Left R0 LSB Ri:R0

0

ASL R0 ROL RI

R2 MULTIPLICAND M

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SOFTWARE MULTIPLICATION
CLR R0 Clear register R0 MOV #-16.,R3 Set register R3 to -16 use as cycle counter mloop: ASL R0 ASL (Arithmetic Shift Left) instruction shifts contents of R0 (low-order half of partial product) left one bit. MSB of R0 is shifted into C bit. LSB of R0 is set to 0 ROL (Rotate Left) instruction rotates contents of R1 and the C bit by one bit position. Old contents of C is moved into LSB of R1, old contents of MSB of R1 is moved into C. The combination of ASL and ROL have thus shifted the (R1, R0) pair left one bit position, placing the old MSB of R1 into C. BCC ADD noadd R2,R0 The multiplier bit to be checked (first qn-1, then qn-, etc.) is now in C, and the instruction BCC causes a branch around the add operation if C is 0. If C=1, multiplicand in R2 is added into the low-order end of the partial product in R0. Any carry-out that goes into C must be added to the high-order half of the partial product. This is done by the ADC which adds contents of C to the LSB position of R1. Note that this process will never damage the unused portion of the multiplier in R1 because the very first time that (R1, R0) is shifted left, a = is placed in the LSB position of R1, creating enough space for any later encroachment by the partial product. Counter is incremented and BNE (Branch if Not Equal to 0) instruction does branch back to mloop as long 16 cycles are not completed.
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ROL R1

ADC R1

Labels

noadd: INC R3 BNE mloop HALT

SIGNED OPERAND MULTIPLICATION

1. Positive Multiplier, Negative Multiplicand(M)
Extend the sign bit 1..."1" to the left just as we assume we extend the "0" sign bit. Proceed to execute the multiply algorithm as for a positive number.

2. Negative Multiplier, Positive Multiplicand(M)

Complement both the Multiplier and Multiplicand and proceed to multiply with sign extension.

3. Negative Multiplier, Negative Multiplicand (M)

Complement both the multiplier and multiplicand and proceed to multiply. Note: this is the same procedure as when the multiplier is detected to be negative.

CA - XI - ALU(2) - 14

BOOTHS ALGORITHM
1. Booth's algorithm is a powerful direct algorithm to perform signed-number multiplication. The algorithm is based on the fact that any binary number can be represented by the sum and difference of other binary numbers. Using a signed binary notation we can represent a multiplier in a unique scheme with the possibility of fewer add cycles for a given multiplier. 2.a. Examples of the scheme are shown (a positive Multiplier and a negative Multiplier). The first example shows how zero's may be skipped over for faster implementation. b. Figure illustrates how the Booth recordings are accomplished and next figure illustrates the transition recording table. c. Also a flow chart and a table show, respectively, the use of the algorithm for multiplication of 2's complement numbers. d. The speed of the algorithm depends upon the bit savings if any that the Booth algorithm will generate. Figure illustrates the worst, normal and good case for a 16 bit number. e. The algorithm accomplishes the following Uniform treatment of positive and negative numbers. Achieves efficiency in the number of summands in some cases (data dependent). 3. It would be desirable to use the Booth technique in some way that removed some of the data dependence.

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BOOTHS REPRESENTATION (1)

Any binary number can be represented by the sum or difference of other binary numbers. For example, 3010 (00111102) can be represented by 3210 (01000002) minus 210 (00000102). See the example below. 0 1 0 0 0 0 0 (32) 0 0 0 0 0 1 0 (2) 0 0 1 1 1 1 0 (30) 0 +1 0 0 0 -1 0 booth Using a signed binary notation 3010 can be represented as (0 + 1 0 0 0 - 1 0). Note that in scheme transitions determine multipliers. 0 <---- 1 *(1) Multiplier 1 <---- 0 *(-1) Multiplier Repetitions *(0) Multiplier Scan Right to Left
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1 0 0 1 1 (-13) x 0 1 0 1 1 (+11) 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 (-143) Sign extension of negative multiplicand 0 1 0 1 1 0 1 (+45) 0 0 +1 +1 +1 +1 0 (+30) 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 (+1350) 0 1 0 1 1 0 1 0 +1 0 0 0 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 1 (2's compl. of multiplicand) 0 .......................................................................... 0 0 ....................................................................0 0 ............................................................0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 Normal and Booth multiplication schemes.
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BOOTHS REPRESENTATION (2)

Multiplier Bit i Bit i-1

Version of multiplicand selected by bit i 0 0 0xM 0 1 +1 x M 1 0 -1 x M 1 1 0xM Booth multiplier recoding table.

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BOOTHS REPRESENTATION (3)

0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 +1 -1 +1 0 -1 0 +1 0 0 -1 +1 -1 +1 0 1 0 0
Booth recoding of multiplier.

0 1 1 0 1 1 1 0 1 0

(+13) (- 6)

0 1 1 0 1 0 -1+1 -1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 0 (-78)

Sign extension

1 1 1 0 1 1 0 0 1 0

Booth multiplication with a negative multiplier

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BIT-PAIR
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 +1-1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 bad 0 -1 0 0 +1 -1 +1 0 -1 +1 0 0 0 -1 0 0 normal 0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1 good Booth-recorded multipliers Sign extension Implied 0 to right of LSB 1 1 1 0 1 0 0 0 0 -1 +1 -1 0 0 -1 -2 Example of bit pair recording derived from Booth recording Multipl. bit-pair Multiplier bit on the right Multiplicand selected at Spi i+1 i i-1 0 0 0 0xM 0 0 1 +1 x M 0 1 0 +1 x M 0 1 1 +2 x M 1 0 0 -2 x M 1 0 1 -1 x M 1 1 0 -1 x M 1 1 1 0xM Table of multiplicand selection decisions

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Booths Algorithm - a Flowchart

Start A (0:n-1) 0 Q(0:n) 0 0 COUNT M multiplikant

Q(0:n-1)

multiplier

Q(n-1) = 0 and Q(n) = 1? COUNT COUNT + 1 A A(0) A(0) A(1:n-1),Q(0:n) A(0:n-1),Q(0:n-1) Yes A+M

No

Q(n-1) = 1 and Q(n) = 0? Yes A A M

No

No

COUNT = n - 1? Yes OUTBUS A

OUTBUS

Q(0:n-2)

Stop CA - XI - ALU(2) - 21

M 0.010

A 0.010 0.010 1.110 1.111 1.111 0.010 0.001 0.000 0.010 1.110

Q 10110

Comments

Subtract M 1.110 01011 10101 10101 11010 11010 Shift A,Q No addition nor subtraction Shift A,Q Add M Shift A,Q Subtract M

--- Product P -------- Example of 2s-complement multiplication using Booth's algorithm.

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Theoretical Lower Bounds (Fastest Times) For Addition And Multiplication

R N T Denotes each logic element fan-In Denotes number of bits in each operand Represents time (in gate delays) THEORY Addition
T> LOGR(N-2)

PRACTICE 4 LOGRN Carry Lookahead 2 LOG3/2(N) +2 LOGRN

Multiplikation T> LOGR2N Example : R = 4, N = 16 THEORY 2 Gate Delays

Addition

PRACTICE 8 Gate Delays 18 Gate Delays

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Multiplikation 3 Gate Delays

SPEED OF SINGLE CHIP MULTIPLIERS

Speed AMD (Advanced Micro Devices) 25S05 Monolithic Memories Inc. 67516 Motorola TRW MP4 16 TJ 74S274 MIPS R3010 TI 8847 40 ns Bits 2x4

800 ns

16x16

100 ns 230 ns 70 ns 40 ns 30 ns
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32x32 32x32 4x4