Logic Design using PLAs PLAs with Input Decoders

Logic Design using Modules

Gerhard Dueck

March 9, 2010

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Outline

Logic Design using PLAs

PLAs with Input Decoders

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

PLA stucture

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

PLA

Direct relation to SOP Logic design is easy Layouts are easyPLAs are structured

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Output Phase Optimization

Networks can often be simplied by realizing f , the complement of f , instead of the original function f . Denition (Achilles heel function) f = x1 x2 x3 x4 x5 x6 x7 x8 x9 xn2 xn1 xn (n = 3r ) is an n-variable Achilles heel function. Lemma Let f be an n-variable Achilles heel function (n = 3r ). Let t(f ) be the number of product terms in a MSOP for f . Then, t(f ) = r , and t(f ) = 3r . The complexity for f and f can be quite different.

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Logic Design using PLAs PLAs with Input Decoders

Some Properties
Property (Function with low density) For n-variable functions whose densities are r , if r 2n1 , then the average number of products in the SOPs increases as r increases. Property (Function with high density) For n-variable functions whose densities are greater than 2n1 , the number of prime implicants is usually very large, and minimization is difcult. So, usually, the SOPs for the complements of the functions are simpler than the SOPs for the original functions.

Gerhard Dueck

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Logic Design using PLAs PLAs with Input Decoders

Output Phase Optimization

Theorem In a truth table for an n-input multiple-output function, if there are t input combinations that make all the output combinations 0, then the functions can be realized by a PLA with at most (2n t) products. From the properties and the theorem we have the following: A good output phase has large number of input combinations that will make all outputs 0s large number of 0s in the truth table.

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Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

An Example

Example (Output phase assignment) Design a 4-input bit counting circuit (WGT4) (see next slide) The straightforward PLA realization requires 15 products. The complemented function has no zero rows. The optimized output phase has 10 products.

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Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

WGT4
Input x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Original f2 f1 f0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1 0 0 Output Optimized f2 f1 f0 0 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Compl. f1 f0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1

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Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Output Phase Optimization

The previous example leads to the following theorem: Theorem The minimum PLA for the n-input bit-counting circuit (WGTn, n = 2r requires (2n 1) products when the output phase is n original, and 2n n/2 products when the output phase is optimized.

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Algorithm
Algorithm (Near optimum output phase assignment)
1

For a given m-output function let PLA1 (with 2m outputs) be the PLA that realizes all m outputs and their complements. Let the output part of PLA1 be G. Attach the labels P1 , P2 , . . . , Pt to the rows of G. For each output fi (i = 0, . . . , m 1), make an SOP: Li = Pa1 Pa2 Par Pb1 Pb2 Pbs where Pa1 Pa2 Par , denote the rows whose (i + 1)th column of G are 1s (i.e. fi ). Pb1 Pb2 Pbs , denote the rows whose (i + m + 1)th column of G are 1s (i.e. f i ). Expand the expression Q(P1 , P2 , , Pt ) = L0 L1 Lm1 into an SOP, and obtain the product with the fewest literals. Obtain the output phase corresponding to the product obtained in 3.
Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Example: output phase assignment

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Example: output phase assignment

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Example: output phase assignment

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

PLAs with Input Decoders

x1

x1 x2 x1 x 2 x 1 x2

Standard PLAs have 1-bit input decoders. The decoders for PLAs with 2-bit input decoders are shown on the left. How many 2 input decoders are possible?

x2

x1 x2

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Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Principle of PLAs with input decoders

2-bit input decoders realize all maxterms of two variables. An two input function can be realized by a logical product of these maxterms. This is the canonical expression f (x1 , x2 ) = (c0 x1 x2 )(c1 x1 x 2 )(c2 x 1 x2 )(c3 x 1 x 2 ) What is the worst case for 2-variable function using a standard PLA?

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Logic Design using PLAs PLAs with Input Decoders

Coincidence function

Example (Coincidence) Consider the f = f1 (x1 , x2 )f2 (x3 , x4 )f3 (x5 , x6 ), where f1 (x1 , x2 ) = x1 x2 x 1 x 2 f2 (x3 , x4 ) = x3 x4 x 3 x 4 , and f3 (x5 , x6 ) = x5 x6 x 5 x 6 Show the PLA realization (see Fig. 12.7 in the text).

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Representation for PLAs with input decoders

2 variables can be combined into one 4-valued variable. In the coincidence example, let X1 = (x1 , x2 ), X2 = (x3 , x4 ), and X3 = (x5 , x6 ). The function is represented as
X1 00 1 01 0 10 0 11 1 00 1 01 0 X2 10 0 11 1 00 1 01 0 X3 10 0 11 1

Theorem
1

Each product line in a PLA with 2-bit input decoders realizes a product f1 (x1 , x2 )f2 (x3 , x4 ) fr (xn1 , xn ) The function realized by the product lines is represented by
1 1 1 1 2 2 2 2 r r r c0 c1 c2 c3 c0 c2 c2 c3 c0 crr c2 c3 (n = 2r )
Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Design method for PLAs with input decoders

Algorithm (Design with input decoders) Step 1 Transform the logical expression into a bit representation
1 2

Partition input variables into pairs. Derived bit representation for the function with 4-valued variables. Input part: For the part 0, make an AND connection Output part: For the part 1, make an OR connection

Step 2 Transform the bit representation into a PLA.

1 2

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Logic Design using PLAs PLAs with Input Decoders

Example (2-bit adder)

Example (2-bit adder) Find the bit representation for the 2 bit adder. (x1 , x0 ) + (y1 , y0 ) = (z2 , z1 , z0 ). We have: z0 = x0 y0 = x0 y 0 x 0 y0 , z1 = x0 y0 x1 y1 = (x 0 y 0 )(x1 y 1 x 1 y1 ) (x0 y0 )(x1 y1 x 1 y 1 ), and z2 = x1 y1 (x0 y0 )(x1 y1 ).

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Logic Design using PLAs PLAs with Input Decoders

Example (2-bit adder) cont.

Example (2-bit adder (cont.)) Let X1 = (x0 , y0 ), X2 = (x1 , y1 ), and X3 = (z0 , z1 , z2 ). Then we have X1 0110 1110 0001 1111 0001 X2 1111 0110 1001 0001 0111 X3 100 010 010 001 001

The PLA realization is shown in Fig. 12.8 (text)

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Bound for an arbitrary function

Theorem An arbitrary n-variable function (n = 2r ) is realized by a PLA with 2-bit input decoders using at most 2n2 products. Proof. An arbitrary n-variable function is expanded as f =
a a a a a n1 a f (x1 , x2 , a) (x3 3 x4 4 ) (x5 5 x6 6 ) (xn1 xn n ), a

where a = (a3 , a4 , . . . , an ), ai {0, 1}. The number of product terms is 2n2 .

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Logic Design using PLAs PLAs with Input Decoders

Bound for symmetric functions

Theorem An arbitrary n-variable symmetric function (n = 2r ) is realized by a PLA with 2-bit input decoders using at most 3r 1 products. Proof. An arbitrary n-variable symmetric function is expanded as f =
b

S(x1 , x2 , b) Sb2 (x3 , x4 ) Sb3 (x5 , x6 ) Sbr (xn1 , xn ),

where b = (b2 , b3 , . . . , br ), bi {0, 1, 2}, and Sj (xi , xi+1 ) = 1, when xi + xi+1 = j 0, otherwise

Note that S(x1 , x2 , b) is symmetric with respect to x1 and x2 .

Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Bound for parity functions

Theorem An n-variable parity function (n = 2r ) is realized by a PLA with 2-bit input decoders using at most 2r 1 products. Proof. An n-variable parity function is expanded as f =
c

P(x1 , x2 , c) Pc2 (x3 , x4 ) Pc3 (x5 , x6 ) Pcr (xn1 , xn ),

where c = (c2 , c3 , . . . , cr ), ci {0, 1}, and Pcj (xi , xi+1 ) = xi xi+1 cj Note that P(x1 , x2 , c) is also a parity function.
Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Comparison

Table: Number of products to realize n-variable functions.

1-bit decoders Arbitrary function (worst case) Symmetric function (worst case) Parity function Adder 10-variable random function (average) 2n1 2n1 2n1 6 2n 4n 5 163

2-bit decoders 2n2 (3)n2 ( 2)n2 n2 + 1 120

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Logic Design using Modules

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Assignment of input variables

Example Given a 2-bit adder 5 products are needed with assignment X1 = (x0 , y0 ) and X2 = (x1 , y1 ). 9 products are needed with assignment X1 = (x0 , x1 ) and X2 = (y0 , y1 ). number of product terms greatly depends on the variable assignment Optimum assignment of input variables
exhaustive (how many possibilities?) for experimental results see Table 12.3 heuristics
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Optimum assignment

Denition (Partition) Let I = {1, 2, . . . , n} be a set of subscripts for the input variables X . Let be a partition of I. Let t(f : ) be the number of products in a MSOP for f , under the partition . Let F be an SOP for the function f . Let q(i, j) be the number of different products in the SOP that are obtained from F by deleting literals for xi and xj . Let t(f : ij ) be the number of products in a minimum SOP for f , when xi and xj are paired.

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Optimum assignment
Example Let F be F = x 1 x 2 x3 x4 + x 1 x2 x3 x4 + x1 x 2 x 3 x4 + x1 x 2 x 3 x4 + x1 x 2 x3 x 4 + x1 x2 x 3 x 4 q(1, 2) = q(1, 3) = q(1, 4) = q(2, 3) = q(2, 4) = q(3, 4) =
Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Optimum assignment

Lemma Let ij = {[1], [2], . . . , [i, j], . . . , [n]}. Then, t(f : ij ) q(i, j).

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Optimum assignment
Proof. Let F be an SOP for f . Assume i = 1 and j = 2 (WLOG). F =
S S S S x1 1 x2 2 xn n

where S = (S1 , S2 , . . . , Sn ), and Si {0, 1}. Note that 1, when Si = {0, 1} x , when Si = {1} xiSi = i x i , when Si = {0}
S S S Factoring F by x1 1 x2 2 xn n we have

F =
S

S S S G(x1 , x2 , S )x3 3 x4 4 xn n ,
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Optimum assignment
continued. where S = (S3 , S4 , . . . , Sn ), and Si {0, 1} t(F1 ) is equal to the distinct number of patterns in S S S x3 3 x4 4 xn n . These are obtained from F by deleting literals x1 and x2 t(F1 ) = q(1, 2) (by denition) Let X1 = (x1 , x2 ). Replace G(x1 , x2 , S ) with literal T X1 1 , (T1 {00, 01, 10, 11}) we have F1 which is an SOP under partition ij . t(f : ij ) t(F1 ) Thus we have t(f : ij ) q(i, j)

Gerhard Dueck

Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Variable assignment graph

Denition (Variable assignment graph) A variable assignment graph G of an n-variable function f (x1 , x2 , . . . , xn ) is a complete graph with weights satisfying the following conditions:
1 2

G has n nodes. The weight of the edge (i, j) is q(i, j).

Gerhard Dueck

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Logic Design using PLAs PLAs with Input Decoders

Variable assignment
Algorithm (Assignment of variables for a PLA with 2-bit input decoders)
1 2 3

Obtain a (near) minimal SOP for f . Obtain a variable assignment graph G for f . Cover all nodes of G by a set of edges that have no common elements. Find a set such that the sum of the weights are minimum. Obtain the partition of the variables corresponding to the edges. The algorithm is heuristic. Minimal results are not guarantied. Experimental results show that it obtains optimal solutions for many functions.
Gerhard Dueck Logic Design using Modules

Logic Design using PLAs PLAs with Input Decoders

Benchmarks

func. addr4 inc8 log8 mul8 rdm8

products 255 255 255 225 255

Stand. PLA Output phase Org. Opt. 75 61 37 36 123 111 119 108 76 76

PLA inp. decod. Output phase Org. Opt. 17 14 21 20 93 89 85 74 47 47

Gerhard Dueck

Logic Design using Modules