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Microprocessor Complete

8086 MICROPROCESSOR DESCRIPTION

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Microprocessor Complete

8086 MICROPROCESSOR DESCRIPTION

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MICROPROCESSOR & INTERFACES (CSE & IT SEM -V) Prepared By: SUDHA NAIR LECTURER(E&TC) R.C.E.T,BHILAI.

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UNIT- I Microprocessor Architecture

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Introduction to Microprocessors

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What is a microprocessor?
A microprocessor is a programmable digital electronic

component that incorporates the functions of a central processing unit or CPU on a single semi conducting integrated circuit.

One or more typically serve as the CPU in computer

systems, embedded devices, or handheld devices.

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What is a microprocessor?
That means your laptop at home and the PC in your

computer lab!
The advent of the microprocessor astounded many

people.
It was an entire computation engine on one tiny chip.

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Going from the ENIAC which filled an entire room and used over 18,000 vacuum tubes to a 1/8th by 1/6th of an inch (fingernail size) mega chip!

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The First Microprocessor: Intel 4004

Transistor count Today's Intel Core2 Duo processors contain over

Who invented the microprocessor and when?

Three Intel engineers named Federico Faggin, Ted Hoff and Stan Mazor are said to be the brilliant minds behind the microprocessor.

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Why was the microprocessor invented?

The microprocessor reduced the word size of the CPU

from 32 bits to 4 bits so that the transistors of its logic circuits would fit onto a single part.

Before the microprocessor, electronic CPUs were

typically made of big discrete switching devices containing only a few transistors.

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Why was the microprocessor invented?

The microprocessor greatly reduced the cost of

processor power and the physical size of the CPU.

follow Moores Law which states that the complexity of an integrated circuit, with respect to minimum component cost, doubles every 24 months.

The evolution of microprocessors has been known to

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Why was the microprocessor invented?

This has held true throughout the years.

. ever since the microprocessor was created.

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The building block

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Automation

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Communication

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Brief history of microprocessor

Intel i4004 processor Identification Model name: i4004.

Supplier: Intel. Component class: CPU.

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Intel i4004 processor

Architecture

4 bit data bus.

12 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture).

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Intel i4004 processor

Physics

Manufacturing technology: PMOS.

Number of transistors: 2250. Die size: 24 mm2. Packaging: 16 pin CerDIP. Dates Introduction date: 1970. First microprocessor ever built.
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Intel i4040 processor

Identification Model name: i4040.

Supplier: Intel. Component class: CPU.

Compatibility Intel i4004 CPU with extra features: more instructions, interrupt support.

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Intel i4040 processor

Architecture 4 bit data bus.

12 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture).

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Intel i4040 processor

Physics

Manufacturing technology: PMOS

Packaging: 24 pin CerDIP. Dates Introduction date: 1972

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Intel i8008 processor

Identification Model name: i8008.

Generation Generation: 8080. Compatibility Intel i8008 CPU with stack.

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Intel i8080/i8080A processor

Architecture

8 bit data bus.

16 bit address bus. Separate address space for instructions and data (Harvard architecture). Physics Packaging: 40 pin CerDIP. Introduction date: April 1974.

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Intel i8085A/i8085AH processor

Identification Model name: i8085A/i8085AH.

Supplier: Intel. Component class: CPU.

Generation Generation: 8080. Compatibility Intel i8080 CPU upward instruction compatible.

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Intel i8085A/i8085AH processor

Extra instructions: SIM (Set Interrupt Mask) RIM (Read Interrupt Mask) Extra interrupt lines, including NMI (Non-Maskable Interrupt).

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Intel i8085A/i8085AH processor

Architecture

8 bit data bus.

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Basic definitions
Semiconductor Memories are classified according to

the type of data storage and the type of data access mechanism into the following two main groups:

Non-volatile Memory (NVM) also known as Read-Only

Memory (ROM) which retains information when the power supply voltage is off. With respect to the data storage mechanism NVM are divided into the following groups:

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Basic definitions
Mask programmed ROM. The required contents of

the memory is programmed during fabrication.

Basic microprocessor architecture

A microprocessor consists of:

ALU performs arithmetic and logic calculation

Registers temporarily store data Control Unit Synchronizes the operations of all

components

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8085 Microprocessor-Features
The Intel 8085 microprocessor is an NMOS 8-bit device. Sixteen address bits provide access to 65,536 bytes of

8 bits each.

Eight bi-directional data lines provide access to a

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8085 Microprocessor-Features
Unlike the 8080 , 8085 makes use of multiplexing of the

lower 8 bits of the address with the data bits on the same 8 pins. The 8085 has many new support devices to ease design work. These include the 8259 Programmable Interrupt controller, the 8202 Dynamic RAM controller, several new I/O devices with various amounts of RAM, ROM, parallel I/O and timer-counters.
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8085 Microprocessor Architecture

Internal architecture description

Internal architecture description

Flags The ALU includes five flip-flops, which are set or reset

after an operation according to data conditions of the result in the accumulator and other registers. (P), and Auxiliary Carry (AC) flags.

They are called Zero (Z), Carry (CY), Sign (S), Parity

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Internal architecture description

The most commonly used flags are Zero, Carry, and

Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator is larger than eight bits, called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flipflop called the Zero (Z) flag is set to one.

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Internal architecture description

The 8-bit register, called the flag register is adjacent to

the accumulator.

However, it is not used as a register; five bit positions

out of eight are used to store the outputs of the five flipflops.

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Internal architecture description

The flags are stored in the 8-bit register so that the

programmer can examine these flags (data conditions) by accessing the register through an instruction

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Internal architecture description

These flags have critical importance in the decision-

making process of the microprocessor.

The conditions (set or reset) of the flags are tested

through the software instructions.

For example, the instruction JC (Jump on Carry) is

implemented to change the sequence of a program when CY flag is set.

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Internal architecture description

Program Counter (PC) This 16-bit register deals with sequencing the execution

of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a16-bit register. The microprocessor uses this register to sequence the execution of the instructions.
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Internal architecture description

Program Counter (PC) The function of the program counter is to point to the

memory address from which the next byte is to be fetched.

When a byte (machine code) is being fetched, the

program counter is incremented by one to point to the next memory location

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Internal architecture description

Stack Pointer (SP) The stack pointer is also a 16-bit register used as a

memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer.

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Internal architecture description

Instruction register & Decoder

An Instruction Register and decoder system interpret

the programmers instructions and implement them via nano code. Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next stage.
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Programming model of 8085

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8085 System Bus

A typical microprocessor communicates with memory

and other devices (input and output) using three busses:

Address Bus Data Bus and Control Bus.

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8085 System Bus

Address Bus: One wire for each bit, therefore 16 bits = 16 wires. Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits.

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8085 System Bus- Address Bus

A 16 bit binary number allows 216 different numbers, or

32000 different numbers, ie 0000000000000000 up to 1111111111111111.

Because memory consists of boxes, each with a unique

address, the size of the address bus determines the size of memory, which can be used.

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8085 System Bus- Address Bus

To communicate with memory the microprocessor

sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. writing data.

8085 System Bus -Data Bus

The Data Bus typically consists of 8 wires. Therefore,

28 combinations of binary digits.

Data bus used to transmit "data , ie information, results

of arithmetic, etc, between memory and the microprocessor.

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8085 System Bus -Data Bus

Bus is bi-directional. Size of the data bus determines what arithmetic can be

done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to be broken down into chunks of 255. This slows microprocessor.

interrupts, reset etc.

Cannot function correctly without these vital control

signals.

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8085 System Bus- Control Bus

The Control Bus carries control signals partly

unidirectional, partly bi-directional.

Control signals are things like "read or write". This tells

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Generating Control Signals

The 8085 generates a single RD signal. However, the

signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O. Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals:

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Generating Control Signals

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8085 Functional Block Diagram

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When containing addresses, these lines are outbound

only; when containing data, they may be either inbound or outbound, depending upon the nature of the machine cycle.
They also will contain the 8 bits of an I/O device

address during an I/O operation.

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8085 Pin description

ALE Address Latch Enable: It occurs during the first clock cycle of a machine state

and enables the address to get latched into the on chip latch of peripherals. hold times for the address information.

The falling edge of ALE is set to guarantee setup and

ALE can also be used to strobe the status information.

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8085 Pin description

ALE Address Latch Enable: ALE is never 3stated . This signal appears outbound early in a machine cycle

to advise the external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a memory address.

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8085 Pin description

ALE Address Latch Enable: It should be used to clock a catch-and-hold circuit such

as a 74LS245 or 74LS373, so that the full address will be available to the system for the rest of the machine cycle.

The falling edge of ALE is the point at which the signals

on the AD lines, as well as the S0, S1, and I-O/M lines will be stable and may be taken by the external circuitry.

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8085 Pin description

STATUS LINES S0, S1, & I-O/M:

These three status lines serve to indicate the general

status of the processor with respect to what function the MP will perform during the machine cycle. The S0 and S1 lines are made available for circuits which need advanced warning of the ensuing operation, such as very slow RAM or other specialized devices.

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8085 Pin description

STATUS LINES S0, S1, & I-O/M: The system may not normally need to monitor these

lines. The I-O/M line approximates in one line what the S0 and S1 lines do in two.

It indicates whether the operation will be directed

device is to be read and that the Data Bus is available for the data transfer.

WR-WRITE; indicates the data on the Data Bus is to be

8085 Pin description

HLDA :

HOLD ACKNOWLEDGE- indicates that the CPU has

received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

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8085 Pin description

INTR : INTERRUPT REQUEST: This line provides a vectored interrupt capability to the

8085.

Upon receipt of INTR, the 85 will complete the

instruction in process, then generate INTA as it enters the next machine cycle.

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8085 Pin description

INTR :

The interrupting device will jam a Restart (RST)

instruction onto the data bus, which the 85 uses to locate an interrupt vector in low RAM. is used as a general purpose interrupt.
It is sampled only during the next to the last clock cycle

of the instruction.

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8085 Pin description

INTR :

If it is active, the Program Counter (PC) will be inhibited

from incrementing and an INTA will be issued.

It is disabled by Reset and immediately after an

interrupt is accepted.

These interrupts have a higher priority than the INTR

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8085 Pin description

TRAP: This is an un maskable interrupt with a fixed vector in

low RAM. Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt
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8085 Pin description

RESET IN :

These lines provide for both MP and system reset.

The reset circuitry in the 8224, used with the 8080, has

been brought inside the MP. The RESET IN line is generated asynchronously by some sort of external circuit, such as an RC network or Reset switch.

by two for the system clock.

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8085 Pin description

CLK :

Clock Output for use as a system clock when a crystal

or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. This line provides a system clock signal to external circuits which need to be in synchronization with the MP.

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8085 Pin description

IO/M : IO/M indicates whether the Read/Write is to memory or

l/O.
Tri stated during Hold and Halt modes

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8085 Pin description

Vcc:

The 8085A provides RD, WR, and IO/Memory signals

for bus control.

An Interrupt Acknowledge signal (INTA) is also

The interrupts are arranged in a fixed priority that

determines which interrupt is to be recognized if more than one is pending as follows: lowest priority.

TRAP highest priority, RST 7.5,RST 6.5, RST 5.5, INTR This priority scheme does not take into account the

priority of a routine that was started by a higher priority interrupt.

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8085 Functional Description

RST 5.5 can interrupt a RST 7.5 routine if the interrupts

were re-enabled before the end of the RST 7.5 routine.

TRAP: The TRAP interrupt is useful for catastrophic errors

such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive.
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8085 Timings
The longest, of five machine cycles, would consist of

five RAM accesses, the first to obtain the instruction byte itself, and the remaining four to be divided into fetching and saving other bytes.

For example, cycles numbers 2 & 3 may be needed to

fetch two more bytes of an address, while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM.

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8085 Timings
The type of machine cycle being executed is specified

by the status lines I-O/M, S0, and S1, and the control lines /RD, /WR, and /INTA.

These six lines can define seven different machine

cycle types as follows.

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Types of machine cycle

OPCODE FETCH: This is the first machine cycle of any instruction. It is defined with S0 and S1 asserted high, and I-O/M

and /RD low. It is a read cycle from RAM to obtain an instruction byte.

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Types of machine cycle

MEMORY READ:

This is a normal read cycle of any byte except the OP

code. It is defined with S0 and S1 set to 0, 1 respectively, and I-O/M and /RD low. It is a read cycle from RAM to obtain a data or address byte.

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Types of machine cycle

MEMORY WRITE: This is a normal write cycle to memory. It is defined with S0 and S1 set to 1, 0 respectively, and

I-O/M and /WR low. It is a write cycle to RAM to store one byte in the specified address

INTERRUPT ACKNOWLEDGE:

This is a response to an interrupt request applied to the

MP via the INTR line. It is defined with S0 and S1 set to 1, 1 respectively, IO/M set high, and both /RD and /WR also high.

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Types of machine cycle

The Interrupt Acknowledge pin is also held to a low

RST or Trap interrupt request. All bits are held high.

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8085 Timings-Special instructions

Halt: This idle cycle indicates that the MP has executed a

Halt instruction. The I-O/M, /RD, and /WR lines are all tri stated, which would allow them to be controlled by other devices. INTA is held inactive, but not tri stated. The Hold line is really the proper one to use for DMA or multiple processors.

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8085 Timings-T-states T-states Each of the machine cycles defined above, during

which an access of a RAM address or an I/O device is made (except the idle cycles), is further divided into Tstates. Each T-state, for an 85 with a 3 MHz clock, will be about 333 nanoseconds in length. The first machine cycle, during which the OP code is being fetched, will be either 4 or 6 T-states in length.

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8085 Timings-T-states T-states-

Whether 4 or 6 T-states are used depends upon

whether the instruction needs further information from RAM, or whether it can be executed to completion straight away . If multiple accesses are needed, the cycle will be 4 states long; if the execution can run to completion, 6 states are required.

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8085 Timings-T-states The actions of the major signals of the 85 during each

of the 10 possible types of T-states. It may be summarized as follows:

T1 STATE: This state is the first of any machine cycle. S0-S1 lines, I-O/M, A8-A15, and AD0-AD7 contains

whatever would be appropriate for the type of instruction being executed.

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of the machine cycle) will assume the proper level for the type of instruction in progress. The address lines retain the bit pattern selecting one byte from RAM or an I/O device; The AD0-AD7 lines will now prepare to either accept or present a data byte (they are in a state of transition during T2).

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8085 Timings-T-states T2 STATE:

I-O/M and the S0, S1 lines are still displaying the

original settings of T1. Either /RD or /WR will assert during T2, to indicate the nature of the data transaction. INTA will assert at T2 if an interrupt cycle has started.

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8085 Timings-T-states WAIT STATE: If the Ready line was negated during T2, a Tw is

inserted to allow the external circuitry more time to prepare for data transmission. A specific point in T2 is defined, after which a late negation of Ready will not cause the Tw to be inserted. This corresponds to the same actions in the 8080 device. All signals set up during T2 will remain constant during Tw.

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8085 Timings-T-states T3 STATE:

All lines set up during T2 will remain the same in T3,

except the AD0-AD7 lines, which will be conducting data either into or out of the 8085. At the end of T3, the /RD or /WR line will negate to indicate the end of the active function. This will cause the data byte standing on AD0-AD7 to disappear

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8085 Timings-T-states T4 - T6 STATES: These states are required for time to permit the 8085 to

continue processing internally.

No bus actions are required. The S0 & S1 lines are both asserted, while I-O/M is

negated, which specifies that the 85 is involved in an Opcode fetch.

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8085 Timings-T-states T4 - T6 STATES:

Since T4 through T6 will exist only on the first machine

cycle of an instruction, this corresponds correctly with the Machine Cycle chart. The AD0-AD7 lines are tri stated; the A8-A15 retain their original setting; the /RD, /WR, and INTA lines are all negated.

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8085 Timings-Special conditions

Special conditions: In addition to the T-states described above, there are

HOLD AND HALT STATES :

It will be ignored if it was not enabled.

An enabled interrupt during a hold state will have to wait

until the hold clears before being given control of the system.

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8085 Timings- Example

The instruction code 0100 1111 (4FH MOV C, A) is

stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

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Example Mp Communication

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Timing Diagram

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Some Terminologies:
After observing timing diagram we can say,

4FH is a one byte instruction One external operation fetching 4F from 2005H Entire operation needs 4 clock periods

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UNIT- II INSTRUCTION SET & PROGRAMMING WITH 8085

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Instruction
An instruction is a binary pattern designed inside a

microprocessor to perform a specific function.

The entire group of instructions, called the instruction

set, determines what functions the microprocessor can perform.

The 8085s instructions are made up of bytes.

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Instruction
In microprocessor parlance, a byte is described as 8

contiguous binary bits treated as a unit.

The least significant bit is on the right, and is labeled Bit

The most significant bit is on the left, and is Bit 7. Thus,

the machine coding is "origin zero", unless noted otherwise.

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Instruction
Note also that there is no parity bit, or provision for it, as

would be found in larger systems. The 8085s instructions are either one, two, or three bytes long. In all cases, the first byte contains the essential information, such as the OP code. The second and third bytes, if included, provide operand information that wont fit in the first byte.

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Instruction Set Classification

These instructions can be classified into the following

five functional categories:

data transfer (copy) operations arithmetic operations, logical operations, branching operations, and machine-control operations.

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Data Transfer (Copy) Operations

Data Transfer (Copy) Operations This group of instructions copy data from a location

called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. The various types of data transfer (copy) are listed below together with examples of each type:

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Data Transfer (Copy) Operations

LXI Reg. pair, 16-bit data

The instruction loads 16-bit data in the register pair

designated in the operand. Example: LXI H, 2034H or LXI H, XYZ

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Data Transfer (Copy) Operations

Load H and L registers direct

LHLD 16-bit address

The instruction copies the contents of the memory

location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered. Example: LHLD 2040H
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Data Transfer (Copy) Operations

Store accumulator direct STA 16-bit address The contents of the accumulator are copied into the

memory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example: STA 4350H

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Data Transfer (Copy) Operations

Store accumulator indirect

STAX Reg. pair

The contents of the accumulator are copied into the

memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered. Example: STAX B

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Data Transfer (Copy) Operations

Store H and L registers direct SHLD 16-bit address The contents of register L are stored into the

memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example: SHLD 2470H
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Data Transfer (Copy) Operations

Exchange H and L with D and E

XCHG none
The contents of register H are exchanged with the

contents of register D, and the contents of register L are exchanged with the contents of register E. Example: XCHG

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Data Transfer (Copy) Operations

Copy H and L registers to the stack pointer

SPHL none
The instruction loads the contents of the H and L

registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered. Example: SPHL

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Data Transfer (Copy) Operations

Exchange H and L with top of stack

XTHL none
The contents of the L register are exchanged with the

stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered. Example: XTHL
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Data Transfer (Copy) Operations

Output data from accumulator to a port with 8-bit

address OUT 8-bit port address The contents of the accumulator are copied into the I/O port specified by the operand. Example: OUT F8H

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Data Transfer (Copy) Operations

Input data to accumulator from a port with 8-bit

address IN 8-bit port address The contents of the input port designated in the operand are read and loaded into the accumulator. Example: IN 8CH

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Arithmetic instructions
Add register or memory to accumulator ADD R The contents of the operand (register or memory) are M

added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADD B or ADD M
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Arithmetic instructions
Add register to accumulator with carry ADC R The contents of the operand (register or memory) and

M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADC B or ADC M
MYcsvtu Notes Rungta College of Engg. & Technology 207

Arithmetic instructions
Add immediate to accumulator

ADI 8-bit data

The 8-bit data (operand) is added to the contents of the

accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ADI 45H

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Arithmetic instructions
Add immediate to accumulator with carry

ACI 8-bit data

The 8-bit data (operand) and the Carry flag are added

to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example: ACI 45H

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Arithmetic instructions
Add register pair to H and L registers

DAD Reg. pair

The 16-bit contents of the specified register pair are

added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected. Example: DAD H
MYcsvtu Notes Rungta College of Engg. & Technology 210

Arithmetic instructions
Subtract register or memory from accumulator

SUB R
The contents of the operand (register or memory ) are

M subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SUB B or SUB M
MYcsvtu Notes Rungta College of Engg. & Technology 211

Arithmetic instructions
Subtract source and borrow from accumulator

SBB R
The contents of the operand (register or memory ) and

M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. Example: SBB B or SBB M
MYcsvtu Notes Rungta College of Engg. & Technology 212

Arithmetic instructions
Subtract immediate from accumulator

SUI 8-bit data

The 8-bit data (operand) is subtracted from the contents

of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction. Example: SUI 45H

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Arithmetic instructions
Subtract immediate from accumulator with borrow

SBI 8-bit data

The 8-bit data (operand) and the Borrow flag are

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Arithmetic instructions
Decimal adjust accumulator DAA none The contents of the accumulator are

changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation.

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Arithmetic instructions
Decimal adjust accumulator If the value of the low-order 4-bits in the accumulator is

greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: DAA

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Branching operations
Jump unconditionally

JMP 16-bit address The program sequence is

transferred to the memory location specified by the 16bit address given in the operand. Example: JMP 2034H or JMP XYZ

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Branching operations
Jump conditionally

Operand: 16-bit address

The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Example: JZ 2034H or JZ XYZ

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Branching operations
JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

JP Jump on positive S = 0 JM Jump on minus S = 1 JZ Jump on zero Z = 1 JNZ Jump on no zero Z = 0 JPE Jump on parity even P = 1 JPO Jump on parity odd P = 0
MYcsvtu Notes Rungta College of Engg. & Technology 223

Subroutine
Unconditional subroutine call CALL 16-bit address The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Example: CALL 2034H or CALL XYZ
MYcsvtu Notes Rungta College of Engg. & Technology 224

Subroutine
Call conditionally Operand: 16-bit address The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Before the transfer, the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack.
Example: CZ 2034H or CZ XYZ
MYcsvtu Notes Rungta College of Engg. & Technology 225

Subroutine
CC Call on Carry CY = 1
CNC Call on no Carry CY = 0 CP Call on positive S = 0 CM Call on minus S = 1 CZ Call on zero Z = 1 CNZ Call on no zero Z = 0 CPE Call on parity even P = 1 CPO Call on parity odd P = 0
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Subroutine
Return from subroutine unconditionally RET none The program sequence is transferred from the

subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RET
MYcsvtu Notes Rungta College of Engg. & Technology 227

Subroutine
Return from subroutine conditionally

Operand: none
The program sequence is transferred from the

subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RZ
MYcsvtu Notes Rungta College of Engg. & Technology 228

Subroutine
RC Return on Carry CY = 1

RNC Return on no Carry CY = 0

RP Return on positive S = 0 RM Return on minus S = 1 RZ Return on zero Z = 1 RNZ Return on no zero Z = 0 RPE Return on parity even P = 1 RPO Return on parity odd P = 0
MYcsvtu Notes Rungta College of Engg. & Technology 229

Other instructions
Load program counter with HL contents

PCHL none
The contents of registers H and L are copied into the

program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte. Example: PCHL

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Other instructions
Restart RST 0-7 The RST instruction is equivalent to a 1-byte

call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are:
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Restart

Instruction Restart Address RST 0 0000H RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H

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Restart
The 8085 has four additional interrupts and these

interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are: Interrupt Restart Address TRAP 0024H RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH
MYcsvtu Notes Rungta College of Engg. & Technology 233

Logical instructions
Compare register or memory with accumulator CMP R The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved .

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Logical instructions
The result of the comparison is shown by setting the

flags of the PSW as follows: if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset Example: CMP B or CMP M

238

Logical instructions
Logical AND immediate with accumulator

ANI 8-bit data

The contents of the accumulator are logically ANDed

with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. Example: ANI 86H
MYcsvtu Notes Rungta College of Engg. & Technology 239

Logical instructions
Exclusive OR register or memory with accumulator XRA R The contents of the accumulator are Exclusive ORed

with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M
MYcsvtu Notes Rungta College of Engg. & Technology 240

Logical instructions
Exclusive OR immediate with accumulator XRI 8-bit data The contents of the accumulator are Exclusive ORed

with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRI 86H

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Logical instructions
Logical OR register or memory with accumulator ORA R The contents of the accumulator are logically ORed with

M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORA B or ORA M
MYcsvtu Notes Rungta College of Engg. & Technology 242

Logical instructions
Logical OR immediate with accumulator ORI 8-bit data The contents of the accumulator are logically ORed with

the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORI 86H

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Logical instructions
Rotate accumulator left RLC none Each binary bit of the accumulator is rotated left by one

position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P,AC are not affected. Example: RLC

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Logical instructions
Rotate accumulator right

RRC none
Each binary bit of the accumulator is rotated right by

one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P,AC are not affected. Example: RRC
MYcsvtu Notes Rungta College of Engg. & Technology 245

Logical instructions
Rotate accumulator left through carry

RAL none
Each binary bit of the accumulator is rotated left by one

position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected. Example: RAL
MYcsvtu Notes Rungta College of Engg. & Technology 246

Logical instructions
Rotate accumulator right through carry

RAR none
Each binary bit of the accumulator is rotated right by

one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected. Example: RAR
MYcsvtu Notes Rungta College of Engg. & Technology 247

Logical instructions

Complement accumulator CMA none The contents of the accumulator are complemented. No flags are affected. Example: CMA

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Logical instructions
Complement carry

CMC none
The Carry flag is complemented. No other flags are affected. Example: CMC

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Logical instructions
Set Carry

STC none The Carry flag is set to 1. No other flags are

affected. Example: STC

Machine control instructions

Disable interrupts

DI none
The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled. No flags are affected. Example: DI

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Machine control instructions

Enable interrupts

EI none
The interrupt enable flip-flop is set and all interrupts are

enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flip flop is reset, thus disabling the interrupts. This instruction is necessary to enable the interrupts (except TRAP). Example: EI
MYcsvtu Notes Rungta College of Engg. & Technology 254

Machine control instructions

Read interrupt mask

RIM none
This is a multipurpose instruction used to read the

status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM

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Machine control instructions

Set interrupt mask

SIM none
This is a multipurpose instruction and used to

implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM

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Stack
The Stack Pointer The stack on an 8080/8085 can be located anywhere in

RAM memory, pointed to by the stack pointer SP.

Every time something is pushed on to the stack, the SP

pointer is decremented, so the stack is growing down in memory.

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Stack
Stack operations are always performed with registers

pairs. A register pair is referenced by the name of the MSB register: B, D or H. The only exception is PSW, which in fact is the LSB register of the AF pair

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Stack
A push on the stack, whether it comes from the PUSH

instruction, a subroutine call, or interrupt has the following sequence:

Decrement SP by 1 Save most significant byte of register pair Decrement SP by 1 Save least significant byte of register pair Naturally a pop from the stack has just the opposite effect:
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MYcsvtu Notes

Stack
Load least significant byte of register pair

Increment SP by 1
Load most significant byte of register pair Increment SP by 1

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Stack
Push register pair onto stack PUSH Reg. pair The contents of the register pair designated in the

operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the high order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location. Example: PUSH B or PUSH A
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Stack
Pop off stack to register pair POP Reg. pair The contents of the memory location pointed out by the

stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1. Example: POP H or POP A
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The 8085 Addressing Modes

The instructions MOV B, A or MVI A, 82H are to copy

data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output port. The sources and destination are operands. The various formats for specifying operands are called the ADDRESSING MODES.
MYcsvtu Notes Rungta College of Engg. & Technology 263

The 8085 Addressing Modes

For 8085, they are:

Immediate addressing.
Register addressing. Direct addressing. Indirect addressing. Implicit addressing

MYcsvtu Notes

Indirect Addressing

This means that the Effective Address is calculated by

the processor and the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register.
MYcsvtu Notes Rungta College of Engg. & Technology 267

8085 Assembler Directives

Assembler directives are instructions to the assembler

concerning the program being assembled. They are not translated into machine code or assigned any memory locations in the object file.
ORG (origin) org 20 The next block of instructions or data should be stored

in memory locations starting at 2010. Either hex or decimal numbers are acceptable.
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8085 Assembler Directives

END

end
start end of assembly. A HLT instruction may suggest the end of a program,

but does not necessarily mean it is the end of assembly. "start" is the label at the beginning of the program*.

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8085 Assembler Directives

EQU

(equate)
lookup equ 2 The value of the term, lookup, is equal to 2. lookup's value may be referred by name in the program. Similar to a constant statement.

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8085 Assembler Directives

inbuf equ 2099

The value of the term, inbuf, is 2099.

This may be the memory location used as an input

buffer.

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8085 Assembler Directives

(define byte)
data: db 34 or data: db 34 db A2,db 93 Initializes an area byte by byte. Assembled bytes of data are stored in successive

memory locations until all values are stored. The label is optional and may be used as the memory location of the beginning of the data.
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8085 Assembler Directives

DW (define word) long: dw 2050 Initializes an area two bytes at a time. DS (define storage) table: ds 10 Reserves a specified number of memory locations.In

this example,10 memory locations are reserved for "table". The label may be used as the memory location of the beginning of the block of memory.
MYcsvtu Notes Rungta College of Engg. & Technology 273

Instruction Format
An instruction is a command to the microprocessor to

perform a given task on a specified data.

Each instruction has two parts: one is task to be

performed, called the operation code (opcode), and the second is the data to be operated on, called the operand. ways.It may include 8-bit (or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address.
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The operand (or data) can be specified in various

MYcsvtu Notes

Instruction Format
In some instructions, the operand is implicit. Instruction word size The 8085 instruction set is classified into the following

three groups according to word size: One-word or 1-byte instructions Two-word or 2-byte instructions Three-word or 3-byte instructions

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Instruction Format
One-Byte Instructions A 1-byte instruction includes the op code and operand

in the same byte. Operand (s) are internal register and are coded into the instruction. For example: Copy the contents of the accumulator in the register C. MOV C,A 0100 1111 4FH

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Instruction Format
Add the contents of register B to the contents of the

accumulator. ADD B 1000 0000 80H

Invert (compliment) each bit in the accumulator. CMA 0010 1111 2FH

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Instruction Format
MOV rd, rs
rd <-- rs copies contents of rs into rd. Coded as 01 ddd sss where ddd is a code for one of the

7 general registers which is the destination of the data, sss is the code of the source register.

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Instruction Format
Two-Byte Instructions In a two-byte instruction, the first byte specifies the

operation code and the second byte specifies the operand. Source operand is a data byte immediately following the op code. For example: Load an 8-bit data byte in the accumulator. MVI A, Data 3E
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Instruction Format
Assume that the data byte is 32H. The assembly

language instruction is written as Mnemonics Hex code MVI A, 32H - 3E 32H The instruction would require two memory locations to store in memory.
MVI r, data r <-- data Example: MVI A,30H coded as 3EH 30H as two

contiguous bytes.

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Instruction Format
ADI data A <-- A + data OUT port

where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but points directly to where it is located this is called direct addressing.

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Instruction Format
Three-Byte Instructions In a three-byte instruction, the first byte specifies the op

code, and the following two bytes specify the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order address. Op code + data byte + data byte

For example: Transfer the program sequence to the memory location

2085H. JMP 2085H

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Instruction Format
C3 85 20 First byte Second Byte Third Byte This instruction would require three memory locations to

store in memory. Three byte instructions - opcode + data byte + data byte
LXI rp, data16 rp is one of the pairs of registers BC, DE, HL used as

16-bit registers. The two data bytes are 16-bit data in L H order of significance. rp <-- data16
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Instruction Format
Example:

LXI H,0520H coded as 21H 20H 50H in three bytes.

This is also immediate addressing. LDA addr A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H 21H. This is also an example of direct addressing.

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Delay generation
Delay are generated using subroutine

Delays are generated for different purpose

Example- Traffic signal, counters (timer circuits) etc They may also be generated using NOP instruction.

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Delay generation
Ways to generate delay-

Delay depends on the total number of T states present

in the subroutine To start with a counter is set up For small delays an 8 bit register is set up For large delays a 16 bit register is used as counter Nested lops are also used in which two registers are used
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Delay generation
Small delay generation

8 bit register is used as counter

SUBROUTINE Set an 8 bit register as a counter

MVI B, FFH DELAY DCR B JNZ DELAY RET

MYcsvtu Notes

-7T -4T -10T/7T -10T

MYcsvtu Notes

ASCII TO BINARY
SUBROUTINE

SUI 30 H
CPI 0A H RC SUI 07 H RET

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BCD TO BINARY CONVERSION

LXI SP, STACK

LXI H, 4050 H LXI B, 4060 H MOV A,M CALL BCD TO BINARY STAX B HLT
MYcsvtu Notes Rungta College of Engg. & Technology 303

BCD TO BINARY CONVERSION

SUBROUTINE BCD TO BINARY

PUSH B PUSH D MOV C,A ANI OF H MOV B,A MOV A,C

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BCD TO BINARY CONVERSION

ANI F0 H RRC RRC RRC RRC MVI E,0A H MOV D,A XRA A

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BINARY TO BCD CONVERSION

MYcsvtu Notes

CALL CONVERSION MVI B,0A H CALL CONVERSION MOV M,A CONVERSION MVI M, FF H LOOP INR M SUB B JNC LOOP ADD B INX H RET

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BCD TO 7 SEGMENT LED CODE CONVERSION

LXI SP, 4FFF H LXI H, 4050 H MVI D, 03 H CALL UNPACK HLT UNPACK LXI B, 4060 H

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BCD TO 7 SEGMENT LED CODE CONVERSION

AHEAD MOV A,M ANI F0 H RRC RRC RRC CALL LED CONVERSION INX B MOV A,M

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BCD TO 7 SEGMENT LED CODE CONVERSION

ANI 0F H

CALL LED CONVERSION

INX B INX H DCR D JNZ AHEAD RET

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BCD TO 7 SEGMENT LED CODE CONVERSION

LED CONVERSION PUSH H LXI H, CODE ADD L MOV L,A MOV A,M STAX B POP H RET
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MYcsvtu Notes

Sample Programs
Write an assembly program to add two numbers

Program
MVI D, 8BH MVI C, 6FH MOV A, C ADD D OUT PORT1 HLT
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Sample Programs
Write an assembly program to multiply a number by

8 Program MVI A, 30H RRC RRC RRC OUT PORT1 HLT

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Sample Programs
Write an assembly program to find greatest between

two numbers Program MVI B, 30H MVI C, 40H MOV A, B CMP C JZ EQU JC GRT OUT PORT1 HLT
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Sample Programs
EQU: MVI A, 01H

OUT PORT1
HLT GRT: MOV A, C OUT PORT1 HLT

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Sample Programs
Write a 8085 machine code program:

Read two different memory locations Add the contents Send the result to output port 02 (display) if there is no overflow Display FF if there is an overflow Stop

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Sample Programs
2000 2001 2002 2003 2004 2005 2006 2007 2008 LDA 2050 MOV B,A LDA 2051
ADD B JNC 2013

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Data transfer & device selection

Input-Output (I/O) describes the transference of

information between main memory and the various peripheral devices attached to a computer.

On other occasions, the user may wish to interrupt what

the computer is doing. For example, under the Unix operating system typing Control-c will stop a program that is running, in contrast under a Windows type operating system typing Control-c is an editing command to copy data and typing Control, Alt, Delete will restart a PC. In terms of computation these are examples of unexpected inputs, since the program that is undergoing execution is not expecting such inputs or interrupts.
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Data transfer & device selection

On a multi user system, many keyboards might be

connected to a single computer. The computer must have the capability to distinguish between the different keyboards. The computer must not lose input data even if several keyboards transmit a character input simultaneously. The computer must be able to respond quickly to each keyboard, and the physical distances of the keyboards to the computer may be long.
MYcsvtu Notes Rungta College of Engg. & Technology 329

Data transfer & device selection

Task How do you think a mouse action can act as an

interrupt? Disks, printers, screens and other I/O devices operate under the CPU program control. VDUs and most printers are output devices, and the output that is produced is determined by the program undergoing execution.

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Data transfer & device selection

Disks are storage devices, but as we have previously

discussed there can be a blur to this concept and disks can be considered to be both I/O devices as well as storage devices, where the input and the output are determined by the program undergoing execution. In these cases, it is always the program undergoing execution in the CPU that initiates I/O data transfer. Furthermore, the CPU will continue processing other tasks while waiting for a particular I/O operation to complete.
MYcsvtu Notes Rungta College of Engg. & Technology 331

Data transfer & device selection

There are occasions when an I/O device being

addressed is busy or not ready. For example, a printer may already have a print job, or it may be stalled due to a miss feed of paper. There might not be a floppy disk in a floppy disk drive or a hard disk might be servicing a different request. In such cases, it is beneficial for the I/O device to be able to provide status information to the CPU, in order that appropriate action can be taken.
MYcsvtu Notes Rungta College of Engg. & Technology 332

Data transfer & device selection

Requirements for sufficient and effective handling of I/O a) There must be a means for individually addressing

different I/O devices. b) There must be mechanisms by which I/O devices can communicate with the CPU. c) Programmed I/O is suitable for slow devices and word transfers. d) Faster I/O devices must have mechanisms to transfer blocks of data. e) There must be mechanisms to handle devices with extremely different control requirements.
MYcsvtu Notes Rungta College of Engg. & Technology 333

Data transfer & device selection

Consequently, it is impractical to connect I/O devices

directly to a CPU without some form of interface unit that is unique to each device.

For example, the formats required by different devices

are different. Some devices require a single portion of data, others a block of data. Some devices expect 8 bits of data, others 16, 32 or even 64.

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Data transfer & device selection

Data may be transmitted serially or in parallel. Therefore, a computer system requires substantially

different interface hardware and software for each I/O device.

Incompatibilities in speed between the various I/O

devices and the CPU render synchronization a major problem.

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MYcsvtu Notes

Data transfer & device selection

Magnetic disks have electromechanical control

requirements that must be met. Such control requirements would consume a vast amount of CPU time. I/O devices therefore have different requirements. Additionally, there is a necessity for the provision of addressing, synchronization, status control and external control capabilities. Consequently, each I/O device requires its own unique interface module to serve between itself and the CPU.
MYcsvtu Notes Rungta College of Engg. & Technology 336

Interface modules
Interface modules

Interface modules can be very simple and control a

single I/O device. Alternatively, interface modules can be complex, controlling many I/O devices and may have substantial built in intelligence

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Interface modules Serial & parallel data transfer

Interface modules
A simple parallel I/O interface.

The unit is composed of three registers: a data register,

a control register and a status register, which can be accessed by the CPU over the system bus.

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Interface modules
The external data bus is a collection of parallel data

lines that can be configured to be either input or output by writing a suitable bit pattern into the control register.

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Interface modules
Once configured, data is transferred to or from the

349

I/O DATA TRANSFER SCHEME

interrupted to react to a special event. For example, typing Control, Alt, Delete on a PC interrupts the program that is running and restarts the PC. Interrupt driven I/O is more efficient than programmed I/O, because an I/O device signals the CPU when it requires a service.
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Interrupt driven I/O

Consequently, interrupt driven I/O frees the CPU to

continue executing other tasks. Most computers have interrupt lines to detect and record the arrival of an interrupt request. It is common for a PC to have between 8 and 15 interrupt lines, which are labeled IRQ1, IRQ2 and so on, where IRQ represents Interrupt Request.

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Interrupt driven I/O

In the case that an IRQ is asserted the computer

suspends the program that is undergoing execution. When an interrupt is accepted, the CPU passes program control to an interrupt handler or service routine. Before control is passes to the interrupt handler, the PC and status register are saved by pushing them onto a Return Address Stack (RAS).

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Interrupt driven I/O

The interrupt handling program is now executed until a

Return from Exception (RTE) instruction is encountered at the end of the interrupt. Once the interrupt has been completed the PC and status register is popped from the RAS, and control is passed back to the interrupted program. Multiple interrupts can occur together, in which case a priority mechanism must decide the order in which the interrupts are handled.
MYcsvtu Notes Rungta College of Engg. & Technology 359

Interrupt driven I/O

There are two major disadvantages of interrupt driven

I/O. First, all data transfers involve moving data to and from the CPU registers. Second, since the PC and Status Register are pushed onto the RAS before control is passed to the interrupt handler and they are popped from the RAS when an RTE is encountered, then a significant overhead is involved which can impact on processor performance

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DMA I/O
Modes of I/O Transfer: DMA I/O An alternative mechanism that avoids the use of the

CPU is called Direct Memory Access (DMA).

Many device controllers, particularly those used for

block devices such as magnetic disks use DMA, see storage device handout.

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DMA I/O
Data is directly transferred between a peripheral device

364

Asynchronous and synchronous data transmission

Asynchronous and synchronous data transmission Asynchronous transmission uses start and stop bits to

signify the beginning bit ASCII character would actually be transmitted using 10 bits e.g.: A "0100 0001" would become "1 0100 0001 0". The extra one (or zero depending on parity bit) at the start and end of the transmission tells the receiver first that a character is coming and secondly that the character has ended.
MYcsvtu Notes Rungta College of Engg. & Technology 365

Asynchronous and synchronous data transmission

This method of transmission is used when data are sent

intermittently as opposed to in a solid stream. In the previous example the start and stop bits are in bold. The start and stop bits must be of opposite polarity. This allows the receiver to recognize when the second packet of information is being sent.

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Asynchronous and synchronous data transmission

Synchronous transmission uses no start and stop bits

but instead synchronizes transmission speeds at both the receiving and sending end of the transmission using clock signals built into each component.
nodes.

A continual stream of data is then sent between the two

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Asynchronous and synchronous data transmission

Asynchronous and synchronous data transmission

When the clocks of each modem are in synchronization,

the data stream is sent. In asynchronous transmission, data is coded into a series of pulses, including a start bit and a stop bit. A start bit is sent by the sending modem to inform the receiving modem that a character is to be sent. The character is then sent, followed by a stop bit designating that the transfer of that bit is complete

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Memory-Mapped I/O
I/O devices are treated like memory locations

Processor uses memory-access instructions and

addressing modes to access I/O devices I/O devices and memory locations cannot have the same address Address is 16 bits wide Memory of 64K is shared with I/O devices

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I/O-mapped I/O
Processor controls I/O by a group of dedicated control

signals Processor uses special instructions to access these I/O Each I/O (or port) is identified by a unique port number IN and OUT instructions are used. 256 combinations or 256 I/O devices can be assembled Same 8 bit address is copied to A0-A7 and A8 A15. 64 k memory and 256 I/O devices are available.
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Memory structure & its requirements

RAM
Data Lines

ROM
WR

Input Buffer

Address Lines

Output Buffer

Data Lines

Date Lines

The process of interfacing the above two chips is the

same. However, the ROM does not have a WR signal.

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Memory structure & its requirements

8085 requires memory to-

Read op code
To read/write data Hence both EPROM & RAM are interfaced with it Multiple EPROM & RAM could be interfaced anywhere

with in the address range of 8085

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Steps for memory interfacing with 8085

We can have multiple EPROM and multiple RAM.

Reset address of 8085 if 0000 h. So at least mapping of

one EPROM is necessary at 0000 h Some address lines of 8085 are used to connect directly to the memory chip. Some are used for decoding the address of the memory chip. This may require the use of the decoder IC 74LS138. All these steps depend on the range of the memory chip to be connected to 8085
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Steps for memory interfacing with 8085

Accessing memory can be summarized into the following three steps: Select the chip. Identify the memory register. Enable the appropriate buffer.

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Steps for memory interfacing with 8085

Translating this to microprocessor domain: The microprocessor places a 16-bit address on the address bus. Part of the address bus will select the chip and the other part will go through the address decoder to select the register. The signals IO/M and RD combined indicate that a memory read operation is in progress. The MEMR signal can be used to enable the RD line on the memory chip.

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Address decoding
The result of address decoding is the identification of a

register for a given address. A large part of the address bus is usually connected directly to the address inputs of the memory chip. This portion is decoded internally within the chip. What concerns us is the other part that must be decoded externally to select the chip. This can be done either using logic gates or a decoder.
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The Overall Picture

Putting all of the concepts together, we get:
A15- A10
Chip Selection Circuit

8085
A15-A8
ALE
CS

AD7-AD0

Latch

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Examples of memory interfacing with 8085

Interface 2KB of memory to 8085 with starting address

8000 H Sol Placing the starting address of the chip on the address lines of 8085 we have
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1

0 0 0 0 0 0 0 0 0 0

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Examples of memory interfacing with 8085

2 KB = 2*2^10

= 2 ^ 11 Hence 11 address lines (A0-A10) are connected directly to the memory chip and A15 to A11 are used for selecting the chip

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Examples of memory interfacing with 8085

The final address of the chip is obtained as follows A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

Hence the range of the chip is from 8000 H to 87FF H. A15 to A11 are used to select the chip using the NAND gate. The chip is selected by providing a low signal at its chip select

pin. The A15 to A11 address lines are used as inputs to the NAND gate. Their logic is so adjusted so that the output of NAND gate is low.
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Shadow memory/Folded memory/Linear decoding

Its also known as partial or linear decoding

In this type of decoding its not necessary to use all

address lines Address lines which are not really required for selection of chip could be used for finding different address range of a single memory chip

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Shadow memory/Folded memory/Linear decoding

Example-

Interface 1K*8 EPROM to 8085 using linear decoding

Sol Lets assume the starting address as 0000 H.

The address range of the given chip is obtained as follows A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 ie the range is 0000 H to 03FF H.

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Shadow memory/Folded memory/Linear decoding

Now if the logic of A15 and A14 lines are changed as

follows A15 A14 0 0 0 1 1 0 1 1 we have the different address range of the same chip as followsMYcsvtu Notes Rungta College of Engg. & Technology 392

Shadow memory/Folded memory/Linear decoding

0000 H

03FF H 4000 H 43FF H 8000 H 83FF H C000 H C3FF H This results in wastage of address space.

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Shadow memory/Folded memory/Linear decoding

0000 H Actual Address 03FF H 4000 H 43FF H 8000 H Folded Address83FF H C000 H C3FF H FFFF H

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Absolute decoding
In absolute decoding no address space is wasted

Its used when number of peripherals is more

More hardware is required

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UNIT- IV INTERRUPTS

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Interrupts
Interrupt is a process where an external device can get

the attention of the microprocessor.

The process starts from the I/O device The process is asynchronous.

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Interrupts
Classification of Interrupts

Interrupts can be classified into two types:

Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or

Rejected)

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Interrupts
Interrupts can also be classified into: Vectored (the address of the service routine is hard-

wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)
An interrupt is considered to be an emergency signal

that may be serviced. The Microprocessor may respond to it as soon as possible.

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MYcsvtu Notes

Interrupts
What happens when MP is interrupted ? When the Microprocessor receives an interrupt signal, it

suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.
Each interrupt will most probably have its own ISR.

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Responding to Interrupts
Responding to an interrupt may be immediate or

delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.

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8085 Interrupts
TRAP RST7.5 RST6.5 RST 5.5 INTR INTA

8085

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Interrupt Vectors and the Vector Table

An interrupt vector is a pointer to where the ISR is

stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually located in memory page 00 (0000H - 00FFH). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.
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Interrupt Vectors and the Vector Table

Example: Let , a device interrupts the Microprocessor

using the RST 7.5 interrupt line. Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location

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The 8085 Non-Vectored Interrupt Process

The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted

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The 8085 Non-Vectored Interrupt Process

The 8085 recognizes 8 RESTART instructions: RST0 - RST7.

Each of these would send the execution to a predetermined hard-wired memory location:

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Hard-wired memory location of Restart

Restart Instruction RST0 RST1 RST2 RST3 RST4 RST5 RST6 RST7
MYcsvtu Notes

Equivalent to CALL 0000H CALL 0008H CALL 0010H CALL 0018H CALL 0020H CALL 0028H CALL 0030H CALL 0038H
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Restart Sequence
The restart sequence is made up of three machine

cycles In the 1st machine cycle: The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction.

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Restart Sequence

In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction.

During the interrupt acknowledge machine cycle, (the

1st machine cycle of the RST operation): The Microprocessor activates the INTA signal. This signal will enable the Tri-state buffers, which will place the value EFH on the data bus. Therefore, sending the Microprocessor the RST 5 instruction.

The RST 5 instruction is exactly equivalent to CALL

0028H

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Issues in Implementing INTR Interrupts

How long must INTR remain high?

The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional CALL instruction which requires 18 T-states.

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Issues in Implementing INTR Interrupts

Therefore, the INTR must remain active for 17.5

T-

states. If f= 3MHZ then T=1/f and so, INTR must remain active for [ (1/3MHZ) * 17.5 5.8 micro seconds].

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Issues in Implementing INTR Interrupts

How long can the INTR remain high?

The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again. Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0). Therefore, INTR should be turned off as soon as the INTA signal is received.

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Multiple Interrupts & Priorities

How do we allow multiple devices to interrupt using the

INTR line? The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.
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Multiple Interrupts & Priorities using Priority Encoder

The solution is to use a circuit called the priority

encoder (74LS148). This circuit has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to the increasing index of the input. Input 7 has highest priority and input 0 has the lowest. The 3 outputs carry the index of the highest priority active input.
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Multiple Interrupts & Priorities using Priority Encoder

Note that the op codes for the different RST instructions

follow a set pattern. Bit D5, D4 and D3 of the op codes change in a binary sequence from RST 7 down to RST 0. The other bits are always 1. This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction. The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.
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Multiple Interrupts & Priorities using Priority Encoder

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The 8085 Maskable/Vectored Interrupts

The 8085 has 4 Masked/Vectored interrupt inputs.

RST 5.5, RST 6.5, RST 7.5 They are all maskable. They are automatically vectored according to the following table: Interrupt Vector RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH
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MYcsvtu Notes

The 8085 Maskable/Vectored Interrupts

The vectors for these interrupt fall in between the

vectors for the RST instructions. Thats why they have names like RST 5.5 (RST 5 and a half).

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Masking RST 5.5, RST 6.5 and RST 7.5

These three interrupts are masked at two levels:

Through the Interrupt Enable flip flop and the EI/DI instructions. The Interrupt Enable flip flop controls the whole maskable interrupt process. Through individual mask flip flops that control the availability of the individual interrupts. These flip flops control the interrupts individually.

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Manipulating the Masks

The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction. This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts.

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How SIM Interprets the Accumulator

7 6 5 4 3 2 1 0

SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5

Serial Data Out

Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin

RST5.5 Mask 0 - Available RST6.5 Mask 1 - Masked RST7.5 Mask Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2

Not Used

Force RST7.5 Flip Flop to reset

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SIM and the Interrupt Mask

Bit 0 is the mask for RST 5.5 Bit 1 is the mask for RST 6.5 Bit 2 is the mask for RST 7.5.

If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked.

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SIM and the Interrupt Mask

Bit 3 (Mask Set Enable - MSE) is an enable for setting

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Triggering Levels
RST 6.5 and RST 5.5 are level sensitive.

The interrupting signal must remain present until the microprocessor checks for interrupts.

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Determining the Current Mask Settings

RIM instruction: Read Interrupt Mask

Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.
RST7.5 Memory RST 7.5
M 7.5

5 4

SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5

RST 6.5
M 6.5

RST 5.5
M 5.5
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Interrupt Enable Flip Flop

448

How RIM sets the Accumulators different bits

7 6 5 4 3 2 1 0

SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 RST5.5 Mask RST6.5 Mask RST7.5 Mask

Serial Data In RST7.5 Interrupt Pending RST6.5 Interrupt Pending RST5.5 Interrupt Pending

Bit 7 is used for Serial Data Input.

The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.

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Pending Interrupts
Since the 8085 has five interrupt lines, interrupts may

occur during an ISR and remain pending.

Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts.

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TRAP
TRAP is the only non-maskable interrupt.

It does not need to be enabled because it cannot be disabled. It has the highest priority amongst interrupts. It is edge and level sensitive.

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TRAP
It needs to be high and stay high to be recognized. Once it is recognized, it wont be recognized again until it goes low, then high again.

TRAP is usually used for power failure and emergency

shutoff.

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The 8085 Interrupts

Interrupt Name INTR RST 5.5 / RST 6.5 RST 7.5 Maskable Masking Method DI / EI DI / EI SIM DI / EI SIM Vectored Memory Triggering Method Level Sensitive Level Sensitive Edge Sensitive Level & Edge Sensitive
457

Yes

TRAP
MYcsvtu Notes

8155-RAM+ 3 I/O Ports+Timer

8251-Communication Controller
8253-Programmable Interval Timer 8254-Programmable Interval Timer 8255-Programmable Peripheral Interface 8257-DMA Controller 8259-Programmable Interrupt Controller 8279-KeyBoard/Display Controller 8755-EPROM+2 I/O Ports
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8355/8755 Multifunction Device (memory +IO)

Features

2kbytes ROM(8355) / EPROM(8755)

Two bidirectional 8 bit I/O ports Each port line individually programmable for I or O Internal AD demux using ALE Generates ready signal Separate control lines for I/O section

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Block diagram- 8355/8755

Vdd=25V for programming EPROM

Vcc=5V, Vss=0V

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8355/8755
8085ROMI/OLSI 8355 for the 8085 circuit has been

designed around ROM and parallel I / O ports are integrated in the LSI. 80858088 Address and data bus interfaces directly by the state because they can more 8085 to 8088 can also be applied. ROM8755UV EPROM 8355 mask ROM, 8755 is a builtin UV EPROM.

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8355/8755
Port and DDR

addresses
A1 A0 Port/DD R

0
0 1 1
MYcsvtu Notes

0
1 0 1

Port A
Port B DDR A DDR B
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8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The 8251 is a USART (Universal Synchronous

Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.

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Block diagram of the 8251 USART

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8251 USART
The 8251 functional configuration is programmed by

software. Operation between the 8251 and a CPU is executed by program control. Table shows the operation between a CPU and the device.

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8251 USART
Control Words There are two types of control word. 1. Mode instruction (setting of function) 2. Command (setting of operation)

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8251 USART
Mode Instruction

Mode instruction is used for setting the function of the

8251. Mode instruction will be in "wait for write" at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a "mode instruction." Items set by mode instruction are as follows: Synchronous/asynchronous mode Stop bit length (asynchronous mode) Character length
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8251 USART
Parity bit

Baud rate factor (asynchronous mode)

Internal/external synchronization (synchronous mode) Number of synchronous characters (Synchronous

mode)

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8251 USART
The bit configuration of mode instruction is shown in

Figures. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

It is possible to write a command whenever necessary after writing a mode instruction and sync characters.

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8251 USART

Items to be set by command are as follows: Transmit Enable/Disable Receive Enable/Disable DTR, RTS Output of data. Resetting of error flag. Sending to break characters Internal resetting Hunt mode (synchronous mode)

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8251 USART Pin Description

RXRDY (Output terminal) This is a terminal which indicates that the 8251 contains

a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set.
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8251 USART Pin Description

RXD (input terminal)

This is a terminal which receives serial data.

RXC (Input terminal) This is a clock input signal which determines the

transfer speed of received data. In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.
MYcsvtu Notes Rungta College of Engg. & Technology

The Intel 8255 (or i8255) Programmable Peripheral

Interface chip is a peripheral chip originally developed for the Intel 8085 microprocessor, and as such is a member of a large array of such chips, known as the MCS-85 Family. This chip was later also used with the Intel 8086 and its descendants. It was later made (cloned) by many other manufacturers.

MYcsvtu Notes

Rungta College of Engg. & Technology

499

8255 Programmable Peripheral Interface

Are in DIP 40 and PLCC 44 pins encapsulated versions. This chip is used to give the CPU access to

programmable parallel I/O, and is similar to other such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the MOS Technology 6522 (Versatile Interface adapter) and the MOS Technology CIA (Complex interface Adapter) all developed for the 6502 family.

Other such chips are the 2655 Programmable

MYcsvtu Notes Rungta College of Engg. & Technology 500

8255 Programmable Peripheral Interface

Peripheral Interface from the Signetics 2650 family of

microprocessors, the 6820 PIO

(Peripheral Input/Output) from the Motorola 6800 family,

the Western Design Center WDC 65C21, an enhanced 6520, and many others. all MSX, but is perhaps most well known for its use in the original IBM-PC's parallel printer port (now largely defunct and replaced by the USB standard, and considered a legacy port).
Rungta College of Engg. & Technology

The 8255 are used in home computers as SV-328 and

MYcsvtu Notes

501

8255 Programmable Peripheral Interface

However, most often the functionality the 8255 offered

is now not implemented with the 8255 chip itself anymore, but is embedded in a larger VLSI chip as a sub function.

The 8255 chip itself is still made, and is sometimes

used together with a micro controller to expand its I/O capabilities.

MYcsvtu Notes

Rungta College of Engg. & Technology

8255 PPI
Block diagram

MYcsvtu Notes

Rungta College of Engg. & Technology

506

8255 PPI
The 8255A is a programmable peripheral interface (PPI)

(RD) Read. A low on this Input pin enables the 8255A to send the

data or status information to the CPU on the data bus. In essence, it allows the CPU to read from the 8255A.

MYcsvtu Notes

Rungta College of Engg. & Technology

510

8255 PPI
(WR) Write. A low on the input pin enables the CPU to write data

or control words into the 8255A.

(A0 and A1) Port Select 0 and Port Select 1. The Input signals, in conjunction with the RD and WR

Inputs, controls the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (A0 and A1).
MYcsvtu Notes Rungta College of Engg. & Technology 511

8255 PPI
(RESET)

Reset
A high on this Input clears the control register and all

ports (A, B, C) are set to the Input mode

MYcsvtu Notes

Rungta College of Engg. & Technology

512

8255 PPI
Group A and Group B Controls

The functional configuration of each port is programmed

by the systems software. In essence, the CPU output a control word to the 8255A. The control word contains information such as mode, bit set, bit reset, etc. that Initializes the functional configuration of the 8255A.

MYcsvtu Notes

Rungta College of Engg. & Technology

513

8255 PPI
Each of the Control blocks (Group A and Group B)

accepts commands from the Read/Write Control Logic, receives control words from the internal data bus and issues the proper commands to its associated ports.

MYcsvtu Notes

Rungta College of Engg. & Technology

514

8255 PPI
Control Group A

Port A and Port C upper (C7 C4)

Control Group B Port B and Port C lower (C3 C0) The Control Word Register can only be written into. No Read operation of the Control Word Register is

allowed.

MYcsvtu Notes

Rungta College of Engg. & Technology

515

8255 PPI
Ports A, B, and C The 8255A contains three 8-bit ports (A , B, and C). All can be configured in a wide variety of functional

characteristics by the system software but each has its own special features or personally to further enhance the power and flexibility of the 8255A.

MYcsvtu Notes

Rungta College of Engg. & Technology

516

8255 PPI
Port A- One 8 bit data output latch/buffer and one 8-bit

data input latch. Port B - One 8-bit data output latch/buffer and one 8-bit data input buffer. Port C-One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the controls signal outputs and status signal inputs in conjunction with ports A and B.
MYcsvtu Notes Rungta College of Engg. & Technology 517

8255A OPERATIONAL DESCRIPTION

Mode Selection There are three basic modes of operation that can be

selected by the systems software: Mode 0 Basic Input/Output Mode 1 Strobed Input/Output Mode 2 Bi-Directional Bus

The Mode definitions and possible mode combinations

may seem confusing at first but after a cursory review of the complete device operation a simple , logical I/O approach will surface. The design of the 8255A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no use of the available pints.
MYcsvtu Notes Rungta College of Engg. & Technology 523

8255A OPERATIONAL DESCRIPTION

Single Bit Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset using

a single OUT put Instruction. This feature reduces software requirements in Controlbased applications. When Port C is being used as status/control for Port A or B.These Bits can be set or reset by using the Bit set/reset operation just as if they were data output port.

MYcsvtu Notes

Rungta College of Engg. & Technology

524

8255A OPERATIONAL DESCRIPTION

MYcsvtu Notes

Rungta College of Engg. & Technology

525

8255A OPERATIONAL DESCRIPTION

Interrupt Control Functions When the 8255A is programmed to operate in mode 1

Output Control Signal Definition OBF (Output Buffer Full F/F). The OBF output will go low to indicate that the CPU

has written data out to the specified port. The OBF F/F will be set by rising edge of the WR input being low. ACK (Acknowledge Input). A low on this input informs the 8255A that the data from port A or port B has been accepted.
MYcsvtu Notes Rungta College of Engg. & Technology 535

8255A Operating Modes

In essence, a response from the peripheral device

541

8255A Operating Modes

Output Operations OBF (Output Buffer Full). The OBF output will go low to indicate that the CPU

has written data out to port A. ACK (Acknowledge). A low on this input enables the tri-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PC6
MYcsvtu Notes Rungta College of Engg. & Technology 542

8255A Operating Modes

Input Operations STB (Strobe Interrupt) STB (Strobed Input). A low on this input loads data into the input latch. IBF (Input Buffer Full F/F). A high on this output indicates that data has been loaded into the input latch. INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PC4.

MYcsvtu Notes

Rungta College of Engg. & Technology

543

8255A Operating Modes

A1 0 0 1 A0 0 1 0 Select PA PB PC

1
MYcsvtu Notes

CONTROL REGISTER
Rungta College of Engg. & Technology 544

8255A Operating Modes

BSR mode

Bit set/reset, applicable

to PC only. One bit is S/R at a time. Control word:

D7 D6 D5 X D4 X D3 B2 D2 B1 D1 B0 D0 S/R( S=1, R=0)
545

0(0=B X SR)

MYcsvtu Notes

Rungta College of Engg. & Technology

8255A Operating Modes

I/O mode
D7 1 (1=I/O) D6 D5 D4 PA D3 PCU D2 GB mode select D1 PB D0 PCL

GA mode select

MYcsvtu Notes

Rungta College of Engg. & Technology

546

8255A Operating Modes

D6, D5: GA mode select:

549

8255A Operating Modes

Input mode: D4, D2: Set/Reset INTE using BSR. STB-bar input is

connected to external peripheral's strobe output (i.e. PC2, PC4 pin to external strobe).

INTE is internal connection. STB-bar is external

connection.

MYcsvtu Notes

Rungta College of Engg. & Technology

550

8255A Operating Modes

Output mode:

D6, D2: Set/Reset INTE using BSR. ACK-bar input is

connected to external peripheral's acknowledge output (i.e. PC2, PC6 pin to external ack).
INTE is internal connection. ACK-bar is external

connection.

MYcsvtu Notes

Rungta College of Engg. & Technology

551

8255A Operating Modes

Mode 2

Only for PA
Status:

OBF- INTE IBF-A INTE INTR X A-bar 1(O/P 2(I/P) -A )/ / ACKSTBAA-Bar BAR
MYcsvtu Notes Rungta College of Engg. & Technology

552

Programmable Keyboard/Display Interface 8279

A programmable keyboard and display interfacing chip.

Scans and encodes up to a 64-key keyboard. Controls up to a 16-digit numerical display.

Keyboard has a built-in FIFO 8 character buffer.

The display is controlled from an internal 16x8 RAM that

stores the coded display information.

MYcsvtu Notes

Rungta College of Engg. & Technology

553

PIN DIAGRAM OF 8279

MYcsvtu Notes

Rungta College of Engg. & Technology

554

Pin out Definition of 8279

A0: Selects data (0) or control/status (1) for reads and

The keyboard matrix can be any size from 2x2 to 8x8.

Pins SL2-SL0 sequentially scan each column through a

counting operation. The 74LS138 drives 0's on one line at a time. The 8279 scans RL pins synchronously with the scan. RL pins incorporate internal pull-ups, no need for external resistor pull-ups.

MYcsvtu Notes

Rungta College of Engg. & Technology

559

Keyboard Interface of 8279

D7 D6 D5 000

Function Mode set

Purpose Selects the number of display positions, type of key scan Programs internal clk, sets scan and debounce times. FIFO Selects type of FIFO read and address of the read.
560

001

Clock

010

Read

MYcsvtu Notes

Rungta College of Engg. & Technology

Keyboard Interface of 8279

D7 D6 D5 011 100 101 110 111

Function Read Display

Write Display Display Clear End interrupt

Purpose Selects type of display read and address of the read. Selects type of write and address of the write. write inhibit Allows halfbytes to be blanked. Clears the display or FIFO Clears the IRQ signal to microprocessor
561

MYcsvtu Notes

Rungta College of Engg. & Technology

Keyboard Interface of 8279

First three bits given below select one of 8 control

registers (opcode). 000DDMMM Mode set: Opcode 000. DD sets displays mode. MMM sets keyboard mode. DD field selects either: 8- or 16-digit display Whether new data are entered to the rightmost or leftmost display position
MYcsvtu Notes Rungta College of Engg. & Technology

562

Keyboard Interface of 8279

DD
00 01 10 11

Function 8-digit display with left entry 16-digit display with left entry 8-digit display with right entry 16-digit display with right entry

MYcsvtu Notes

Rungta College of Engg. & Technology

563

Keyboard Interface of 8279

MMM field: DD Function

000 001

010
011 100 110 111
MYcsvtu Notes

Encoded keyboard with 2-key lockout Decoded keyboard with 2-key lockout Encoded keyboard with N-key rollover Decoded keyboard with N-key rollover Encoded sensor matrix101Decoded sensor matrix Strobed keyboard, encoded display scan Strobed keyboard, decoded display scan
Rungta College of Engg. & Technology 564

Keyboard Interface of 8279

Encoded: Sl outputs are active-high, follow binary bit pattern 0-7 or 0-15. Decoded: SL outputs are active-low (only one low at any time). Pattern output: 1110, 1101, 1011, 0111. Strobed: An active high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO for reading by micro later.

MYcsvtu Notes Rungta College of Engg. & Technology 565

Keyboard Interface of 8279

2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed simultaneously/Accepts all keys pressed from 1st to last.

MYcsvtu Notes

Rungta College of Engg. & Technology

566

Keyboard Interface of 8279

001PPPPP

The clock command word programs the internal clock driver. The code PPPPP divides the clock input pin (CLK) to achieve the desired operating frequency, e.g. 100KHz requires 01010 for a 1 MHz CLK input.

010Z0AAA

The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111). Z selects auto-increment for the address.

MYcsvtu Notes Rungta College of Engg. & Technology 567

Keyboard Interface of 8279

011ZAAAA

The display read control word selects the read address of one of the display RAM positions for reading through the data port.

100ZAAAA

Selects write address -- Z selects auto-increment so subsequent writes go to subsequent display positions.
Rungta College of Engg. & Technology 568

MYcsvtu Notes

Keyboard Interface of 8279

1010WWBB

The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or rightmost 4 bits. BB works similarly except that they blank (turn off) half of the output pins.

MYcsvtu Notes

Rungta College of Engg. & Technology

569

Keyboard Interface of 8279

1100CCFA

The clear control word clears the display, FIFO or both. Bit F clears FIFO and the display RAM status, and sets address pointer to 000. If CC are 00 or 01, all display RAM locations become 00000000. If CC is 10, --> 00100000, if CC is 11, --> 11111111. 1110E000 -End of Interrupt control word is issued to clear IRQ pin in sensor matrix mode.

MYcsvtu Notes Rungta College of Engg. & Technology 570

Keyboard Interface of 8279

Clock must be programmed first. If 3.0 MHz drives CLK

input, PPPPP is programmed to 30 or 11110.

8253/54 Programming
Each counter is individually programmed by writing a

control word, followed by the initial count.

The control word allows the programmer to select the

counter, model of operation, binary or BCD count and type of operation (read/write

MYcsvtu Notes

Rungta College of Engg. & Technology

583

8253/54 Programming

MYcsvtu Notes

Rungta College of Engg. & Technology

584

8253/54 Programming
Each counter may be programmed with a count of 1 to

FFFFH. Minimum count is 1 all modes except 2 and 3 with minimum count of 2.
Each counter has a program control word used to select

the way the counter operates. If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte (MSB) starts the counter with the new count.
MYcsvtu Notes Rungta College of Engg. & Technology 585

589

8253/54 Modes
Mode 4: Software triggered one-shot (G must be 1).

MYcsvtu Notes

Rungta College of Engg. & Technology

590

8253/54 Modes
Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

MYcsvtu Notes

Rungta College of Engg. & Technology

591

8253/54 Program
Explain the 8253 control word format and set up the

8253 as a square wave generator with 1 ms period if the input frequency to the 8253 is 1 MHz

MYcsvtu Notes

Rungta College of Engg. & Technology

592

8253/54 Program
Sol-

Assume counter 0 is used to generate the square wave

and the addresses of counter 0 = 10 H and the control register is 13 H

The output period required is 1 ms.The input frequency

is 1 MHz, so input period = 1 micro secs.

MYcsvtu Notes

Rungta College of Engg. & Technology

593

8253/54 Program
Count value = Required period/Input period

= 1 ms/ 1 micro secs= (1000)d The control word format to initialize counter 0, 16 bit counter, BCD counting and square wave generator mode will be as follows

MYcsvtu Notes

Rungta College of Engg. & Technology

594

8253/54 Program
7 6 5 4 3 2 1 0

0 0 1 1 0 1 1 1

Select counter 0

BCD counting Mode 3 square wave generator

Select counter 0

load lsb first then msb

Read load lsb first then msb

MYcsvtu Notes

Rungta College of Engg. & Technology

595

8253/54 Program
The 8253 initialization program will be as follows-

MVI A,
OUT MVI A, OUT MVI A, OUT

37H 13 H 00H 10 H 10H 10 H

MYcsvtu Notes

Rungta College of Engg. & Technology

596

MYcsvtu Notes

Rungta College of Engg. & Technology

607

Pin Description of 8155

IO/M (bar) (I) IO/ memory select This line selects the memory if low and selects the IO if

high
PA0-PA7(I/O) These 8 lines are general purpose IO lines.
MYcsvtu Notes Rungta College of Engg. & Technology 608

Pin Description of 8155

The in out direction is selected by programming the

command and status register

PB0-PB7

These 8 lines are general purpose IO lines.

The in out direction is selected by programming the

Timer out (O) this pin is the timer output this output can be either a square wave or a pulse

depending on the timer mode

MYcsvtu Notes

Rungta College of Engg. & Technology

612

Pin Description of 8155

VCC(I)

+5 volt power supply

VSS Ground reference

MYcsvtu Notes

Rungta College of Engg. & Technology

613

Programming information
The command register

It consists of 8 latches, one for each bit

Four bits(0-3) define the mode of the ports. Two bits(4-5) enable or disable the interrupts from port

C when it acts as control port. The last two bits are for timer. The C/S register contents can be altered at any time by using the I/O address xxxxx000 during a write operation
MYcsvtu Notes Rungta College of Engg. & Technology 614

Programming information
Status register

It consists of seven latches, one for each bit.

Rungta College of Engg. & Technology

618

Timer section
Bits 6-7 of the C/S register are used to start and stop

the counter C/S7 C/S6 0 00 11 01 1-

Function NOP STOP STOP AFTER TC START

MYcsvtu Notes

Rungta College of Engg. & Technology

619

Timer section
Timer format

MYcsvtu Notes

Rungta College of Engg. & Technology

620

Timer section
M2 and M1 define the timer mode as follows M2 M1 Function 0 0 Puts out low during 0

1 1

0 1

second half of the count. Square wave ie the period of the square equals the count length programmed with automatic reload at terminal count Single pulse upon TC being reached Automatic reload ie single pulse every time TC being reached
621

MYcsvtu Notes

Rungta College of Engg. & Technology

Solution - Manual The 8051 Microcontroller Based Embedded Systems
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