IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.

4, APRIL 2008 757

Digital Circuit Design Trends

Mark Horowitz, Fellow, IEEE, Donald Stark, Member, IEEE, and Elad Alon, Member, IEEE

I. INTRODUCTION by the improvements in processor design and increases in com-

plexity created two additional “new” problems that needed to
be addressed. The first was the need for increased communi-
T HE past 20 years have seen enormous growth in the
capability and ubiquity of digital integrated circuits.
Today, it sometimes seems difficult to buy any product without
cation bandwidth required to sustain the drastic improvements
in on-chip computation, and thus Section IV describes how I/O
them—even greeting cards have chips in them. In a short systems evolved to satisfy this need. The second issue brought
review paper like this, it is unfortunately impossible to mention on by complexity and performance scaling was the reemergence
(let alone describe) all of the great work that was done and of a power dissipation problem even in CMOS. This issue was
published in the VLSI Circuits Symposium during this period. initially thought only to be critical for systems with limited bat-
So, rather than attempting this task, this paper uses papers from tery sizes and thermal envelopes (like cellphones and personal
the conference to illustrate some of the major trends in the digital assistants), but over time it has become clear that power
design of digital circuits during the past 20 years. Adopting this dissipation is critical in all digital circuits, including high-end
approach means that many interesting papers are not included, processors. This trend is discussed in Section V.
and we apologize in advance if your favorite is one of these.
II. TECHNOLOGY AND CIRCUIT DESIGN TRENDS
At the time of the first VLSI Circuits Symposium in 1987,
many of the dominant digital technology trends had already As clearly evidenced by the papers presented in the confer-
emerged. The first microprocessors were developed in the 1970s ence, the primary concerns of the digital designer have changed
and were already starting to drive computing in the mid 1980s. significantly over these past two decades. In the early years,
Due to power issues with both nMOS and bipolar technology, there were many more publications focused on new circuit
by the mid 1980s, the industry had also mostly transitioned to forms or on circuits for technologies other than CMOS. The
CMOS technology for high-performance digital design. How- early conference papers might even give the impression that
ever, in the late 1980s, both microprocessors and CMOS ap- bipolar/BiCMOS was the technology of the future. In 1987,
peared to be vulnerable to competing alternatives. Significant there were a number of BiCMOS papers including an invited
effort was expended in trying either to improve CMOS circuit paper by Kubo on BiCMOS technology trends [1]. Three years
performance or to find alternative technology/approaches for later, George Wilson from BIT gave a keynote on the bipolar
high-performance designs. BiCMOS was quite popular in the microprocessors that SUN and MIPS were developing [2], and
late 1980s and early 1990s, and many different CMOS circuit that year (which was clearly the peak for bipolar digital circuits)
forms were also presented during this time. the digital logic session had only one CMOS paper. The other
Indeed, looking over the papers dealing with low-level cir- papers were on BiCMOS circuits, including complementary
cuit design issues (as we will do in Section II) makes it apparent BiCMOS [3] and a new nonthreshold bipolar logic [4].
that technology’s path was not as clear then as it seems now in While 1991 still saw a number of BiCMOS papers, there was
hindsight. However, over time, the industry settled on a rela- also a rump session [5] that discussed the problematic future
tively small set of circuit styles, and circuit innovation moved of BiCMOS in the face of continued voltage scaling. Although
toward dealing with the new problems that arose due to the in- there was further work on getting bipolar circuits to work at
creases in complexity enabled by scaling. For example, many lower voltages by Razavi [6] and others, the number of digital
papers dealing with issues such as signal integrity, power supply bipolar papers dropped off considerably. The early years of the
quality, and the distribution of precise timing references were conference also saw digital circuit papers in other unusual tech-
presented during the 1990s, and many of these issues continue nologies, including superconducting Josephson circuits [7] in
to be explored today. 1989 and a CCD processor in 1992 [8]. However, by the mid
Since much of the work in digital circuits was driven by pro- 1990s, it was clear that plain voltage-scaled CMOS technology
cessor design, and since these new system problems were most was going to win, and since that time there have been few pa-
acute for processors, Section III examines the evolution of both pers about novel digital technologies.
application specific and general purpose processors. During the Like papers describing bipolar and BiCMOS circuits, pa-
mid to late 1990s, the growing computational power enabled pers describing novel CMOS logic families were much more
common in the first decade of the conference than in the second
Manuscript received January 10, 2008; revised January 14, 2008.
decade. A good example is a multivalued logic technique pro-
M. Horowitz and D. Stark are with the Department of Electrical Engineering, posed by Kawahito [9]. Representing a sign/digit number on one
Stanford University, Stanford, CA 94305–9505 USA (e-mail: horowitz@ee. wire greatly reduced the hardware needed in a multiplier. Also,
stanford.edu). in the late 1980s and early 1990s, creating new pass transistor
E. Alon is with the Department of Electrical Engineering and Computer Sci-
ence, University of California, Berkeley, CA 94720-1770 USA. logic families was common—especially for adders. Examples
Digital Object Identifier 10.1109/JSSC.2008.917523 include Yoshida’s ALU design using double-path transistor
0018-9200/$25.00 © 2008 IEEE
758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

logic (DPL) [10] and Cheng’s current-sensed complementary sors, including the need for more pin bandwidth (which is dis-
pass transistor logic [11]. Other circuit ideas that were tried cussed in Section IV), scaling clock frequency, and the impor-
include using a high-speed memory technique—self-resetting tance of instruction set compatibility [25]. Overcoming these
gates—to create high-performance registers and incrementers, challenges has allowed us to create the multi-GHz multicore
presented by Haring [12], and making tradeoffs between speed processors we see today [27].1
and noise margin by precharging and/or predischarging internal This increase in processor performance came from two main
nodes of dynamic logic [13]. factors: exploiting instruction-level parallelism and higher
As the complexity of chips grew during the 1990s, the digital clock rates. In 1990, Uvieghara presented HPSm [28], the
circuit designer’s focus moved to address system-level issues first integrated processor to execute instructions out of pro-
that had now become critical: supply distribution, clock distri- gram order. This ability to rearrange instructions dynamically
bution and latch design, and noise robustness. Power supply dis- was the key technology that allowed processors to exploit
tribution grew to be a huge issue as the rising complexity and instruction-level parallelism and execute more instructions
performance of digital systems coupled with decreasing supply each cycle. The other factor driving performance was scaling
voltages led to large increases in supply current. Lower voltage clock frequency. Part of the increase in clock frequency came
and higher current required that the supply impedance decrease from technology scaling providing faster gates, but the rest
even more rapidly. Early work in this area included Loinaz mea- came from reducing the number of levels of logic between
suring and modeling noise coupling through the common sub- flops. Initially these fast cycle-time machines used the simpler
strate in 1992 [14] and Kitchin evaluating electro-migration in in-order issue model, but in 1997 Farrell described how to build
an Alpha microprocessor in 1995 [15]. By early 2000, power an out-of-order processor that ran at 600 MHz [29]. By the
supply design was a major conference topic. In 2002, Rahal- late 1990s there was a speed race to see who could build the
Arabi presented the design and validation of the supply network shortest clock cycle machine. The result in 2000 was a 1 GHz
in a couple of Intel processors [16]. A circuit to detect supply processor produced in a 0.18 m technology by IBM Research
noise was presented in 2003 [17], and by 2004 there was an en- [30], [31]. Processor frequency continued to scale, with Intel
tire session devoted to power supply design, analysis, and mea- reaching 3 GHz in 2002 [32].
surement. More recent work has focused on trying to mitigate The push for higher clock speeds was not without a large
the effect of supply noise on performance [18]. cost, and 2004’s rump session, titled “Limitations of low FO4
As designers tried to improve performance by reducing designs” [33], signaled that designers had begun to recognize
the number of gates between flops in order to increase clock that this path would hit significant barriers. The principal issue
frequency, clock distribution and latch design also became facing these machines was that their power consumption rose
a challenge during the mid 1990s. In the early 1990s, Dig- to around 100 W, which is right at the limit of cost-effective
ital Equipment Corporation introduced the first “short tick” cooling solutions. Power constraints thus greatly slowed the
processor which spurred interest in this area. Yuan presented scaling of clock frequencies, and, in fact, most of today’s
new true single phase clocking flops in 1996 [19], and Klass processors run at lower clock frequencies than those of the
presented his pulsed dynamic flop in 1998 [20] with reduced processors from the early 2000s. By 2006, power was clearly at
timing overhead. The conference in 1998 also included Restle’s the forefront of digital design, and that year Naffziger described
talk on how to distribute a high-quality clock [21]. Clocking the changes in processor design required to cope with the new
has continued to grow in importance, with an entire session power constraint [34]; these methods will be described in
devoted to this topic at the 2003 conference. Section V.
More recently, designers have become concerned that noise Before moving on, it is interesting to look at some of the
events such as cosmic rays and the increasing device variability specialized processors that were presented at the conference
that comes with scaling will affect circuit robustness. Karnik in in order to gain insight into which application areas were crit-
2001 analyzed the effect of soft errors in latches [22], and in ical enough to warrant chip development. In the late 1980s, fax
2007 Mathew presented a paper on how to build fault-tolerant transmission was growing, and being able to compress and de-
processor execution units [23]. compress images efficiently was critical. This led to specialized
As we have already seen, one of the major drivers for these image compression chips, like the one presented by Kowashi
circuits papers were microprocessor designs. Thus, Section III in 1989 [35]. Many facets of image processing were of growing
takes a step up from low-level circuits to look at how processors importance; the discrete cosine transform chip from 1991 [36] is
have evolved during the past 20 years. one example of a more general image compression device devel-
oped during this time. This interest in image processing broad-
ened to the more general area of multimedia in the early 1990s,
III. PROCESSOR DESIGN
and in 1993 Ackland outlined the opportunities for VLSI in this
The advance in processors during the past 20 years has been area [37]. Media processing became a large growth area during
breathtaking. In the late 1980s, the debate over instruction set the rest of the 1990s, leading to chips optimized for different ap-
complexity (RISC versus CISC) was in full swing, new ISAs plications. By 1996, Chromatic Research had built a more gen-
were being developed, and processors ran at 10–30 MHz. A eral multimedia processor that was flexible enough to handle all
good example of this early processor was the TRON TX1 pre- 1Interestingly, in 1990 Katz and his student proposed building caches from
sented by Tokumaru in 1988 [24]. In 1989, Katz correctly pre- DRAM [26], a topic that has recently become popular as Mbytes of cache
dicted a number of the challenges and trends for microproces- memory are integrated on processors.
HOROWITZ et al.: DIGITAL CIRCUIT DESIGN TRENDS 759

of the multimedia needs (e.g, video, sound, and graphics) of a delay lines and voltage-controlled oscillators (VCOs) com-
PC [38]. posed of inverters running from a regulated supply could have
During the internet boom in the late 1990s, many processor good power supply rejection in addition to well-controlled loop
designs were optimized for operation in networking hardware. dynamics [50].
Since network switches had very high computational load and As process speeds improved and designers gained expe-
many parallel tasks, these designs contained some of the first rience with circuit topologies, the primary system limitation
chip-level multiprocessors [39]. The bursting of the Internet in terms of I/O shifted from the devices themselves to the
bubble and rapid growth of the consumer market has caused interconnect. The 4-PAM signaling and pre-emphasis adopted
recent processor designers to focus more on visual/video pro- in Farjad-Rad’s 1998 paper [51] are good examples of the types
cessing. For example, talks in this year’s conference described of techniques used to compensate for channel characteristics.
processors for mobile graphics [40], mobile multimedia [41], Classic techniques from communications systems were reap-
and H.264 encode/decode [42]. plied to inter-chip communication, as with Sohn’s decision
High-performance processors—whether for visual/video feedback equalizer (DFE) for SSTL DRAM interfaces [52].
processing or for general computation—require huge memory In the 21st century, link design entered the power-limited
bandwidth to supply the data they consume. Satisfying this regime. Higher frequencies and more elaborate equalization
requirement created an active area of circuit research on schemes now had to be balanced against the energy per bit
high-speed I/O design, which is the topic of Section IV. transferred, and the new figure of merit became milliwatts
per gigabit per second. Lee’s 2001 transceiver achieved 20
mW/Gb/s [53], which was surpassed in the 2003 conference by
IV. HIGH-SPEED LINKS Wong’s 7.5 mW/Gb/s design [54].
Communication between devices was not a major issue at
the early VLSI Circuit Symposiums. The TRON processor pre- V. LOW-POWER CIRCUITS
sented in 1988 had a clock speed of 25 MHz, and I/O was While high-performance processors and links just recently
not even mentioned in the paper [24]. Higher speed devices, became power-limited, reducing power was a critical issue
such as the SRAM from Schuster, typically had ECL interfaces much earlier for many digital systems. Soon after the switch
[43] because compatibility with existing systems and standards to CMOS in the mid 1980s, designers realized that low power
was paramount. Designers used considerable ingenuity to make and increasing integration would enable new high-functionality
CMOS compatible with the older bipolar ECL/TTL families, portable devices powered by batteries. For these applications,
concentrating on meeting all aspects of the standard without re- very low operating power would be needed, and the power
quiring external components[44], [45]. of standard CMOS was simply too high to meet this require-
It soon became apparent that requiring backward compat- ment. Broderson’s invited 1991 paper [55] outlined many
ibility was not always necessary or desirable. Ishibe’s 1991 of the approaches that designers would use to reduce power
paper paid close attention to characteristics of the communi- consumption: technology scaling, logic family selection, and
cation channel and impedence matching, achieving 1 Gb/s in architectural and algorithm selection. He also described the
a purely CMOS topology [46]. In 1992, Kushiyama described favorable power tradeoff available by adopting lower frequency
a multi-drop system with 500 Mb/s/pin performance that used and more parallel designs, a lesson that the processor commu-
many of the techniques which became mainstream, including nity is just now applying.
PLL-synchronized data reception/transmission and source Many initial approaches concentrated on reduction of dy-
synchronous clocking [47]. namic power. Nakagome’s 1992 paper is a good ex-
Larger industry trends accelerated the movement to higher ample of this: reduced bus swings gave lower power consump-
speed interfaces. As Rent had noted in the 1960s, increases tion, with low threshold devices used to maintain speed [56].
in component count lead to higher interconnect bandwidth re- Gutnik’s 1996 paper took this idea to its logical conclusion:
quirements, and technology scaling brought both more gates scaling the supply voltage dynamically based on the device’s
and higher clock frequencies. Diverging technology roadmaps workload [57]. However, on-die variability can stress the robust-
made communication between logic and memory a particular ness of this type of tracking power supply system. Das’s paper in
problem. By 1994, the symposium had an entire session dedi- 2005 presented one solution to this issue for a processor—build
cated to inter-chip communication. Designers struggled to find a flop which can detect when data arrives late and then lower the
the best PLL and DLL architectures, interconnect topologies, supply until some errors start to appear [58]. The paper proposed
and termination schemes. Lee’s serial link paper exemplifies using the standard processor retry mechanism to recover from
many of these trends and was notable both for its use of bidi- the few errors that are detected, which allowed the processor to
rectional signaling and of a digital PLL [48]. run at a lower voltage and power than any other approach.
Increasing use of digital techniques was a feature throughout By 1994, low-power design efforts were in full swing, with
the 1990s. Older analog circuit structures became difficult to a dedicated session at the Symposium. In addition to reduced
reuse as power supplies decreased, and link proliferation drove swing, some authors experimented with adiabatic techniques,
topologies that could be more easily ported between processes. which minimize power consumption by keeping the voltage
For example, Yang’s 4 Gb/s oversampling receiver showed that drop across conducting devices small. Kramer’s 2N-2ND logic
both high link speed and good jitter tolerance could be achieved family was a good example of this [59]. In addition to mini-
in a semi-digital design [49], and Sidiropoulos showed that mizing voltage drops, it also presented a constant load to the
760 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

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true-ECL output buffer,” in Symp. VLSI Circuits Dig., 1989, pp. 13–14. He is the Yahoo Founders Professor of the School
[45] Y. Urakawa, M. Matsui, A. Suzuki, N. Urakawa, K. Sato, T. Hamano,
2 2
H. Kato, and K. Ochii, “11.5 ns 1 M 1/256 K 4 TTL BiCMOS
of Engineering at Stanford University. In 1990,
he took leave from Stanford to help start Rambus
SRAM’s with voltage- and temperature-compensated interfaces,” in Inc., Mountain View, CA, a company designing
Symp. VLSI Circuits Dig., 1989, pp. 69–70. high-bandwidth memory interface technology. His
[46] M. Ishibe, S. Otaka, J. Takeda, S. Tanaka, Y. Toyoshima, S. Takatsuka, current research includes multiprocessor design, low-power circuits, high-speed
and S. Shimizu, “1 Gbps pure CMOS I/O buffer circuits,” in Symp. links, and new graphical interfaces.
VLSI Circuits Dig., 1991, pp. 47–48. Dr. Horowitz is a fellow of the ACM and a member of the National Academy
[47] N. Kushiyama, S. Ohshima, D. Stark, K. Sakurai, S. Takase, T. Fu- of Engineering. He was the recipient of the 1985 Presidential Young Investigator
ruyama, R. Barth, J. Dillon, J. Gasbarro, M. Griffin, M. Horowitz, V.
Lee, W. Lee, and W. Leung, “500 Mbyte/sec data-rate 512 kbits 9 2 Award, the 1993 ISSCC Best Paper Award, and the ISCA 2004 Most Influential
Paper of 1989, and the 2006 winner of the IEEE Donald Pederson Award in
DRAM using a novel I/O interface,” in Symp. VLSI Circuits Dig., 1992, Solid State Circuits.
pp. 66–67.
[48] K. Lee, S. Kim, G. Ahn, and D.-K. Jeong, “A CMOS serial link for
1 Gbaud fully duplexed data communication,” in Symp. VLSI Circuits
Dig., 1994, pp. 125–126.
[49] C.-K. K. Yang, R. Farjad-Rad, and M. Horowitz, “A 0.6 m CMOS Donald Stark (M’91) received the B.S. degree
4 Gb/s transceiver with data recovery using oversampling,” in Symp. from the Massachusetts Institute of Technology,
VLSI Circuits Dig., 1997, pp. 71–72. Cambridge, in 1985 and the M.S. and Ph.D. degrees
[50] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive from Stanford University, Stanford, CA, in 1987 and
bandwidth DLL’s and PLL’s using regulated supply CMOS buffers,” 1991, respectively, all in electrical engineering.
in Symp. VLSI Circuits Dig., 2000, pp. 124–127. From 1991 to 1993, he was a DRAM Designer
[51] R. Farjad-Rad, C.-K. Ken Yang, M. Horowitz, and T. Lee, “A 0.4-m with the Semiconductor Device Engineering Labo-
CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” in Symp. ratory, Toshiba Corporation, Kawasaki, Japan. From
VLSI Circuits Dig., 1998, pp. 198–199. 1993 to 2001, he was with Rambus Inc., Mountain
[52] Y.-S. Sohn, S.-J. Bae, H.-J. Park, and S.-I. Cho, “A 1.2 Gbps CMOS View, CA, where he was involved with high-speed in-
DFE receiver with the extended sampling time window for application terface design. From 2001 to 2007, he was Vice Pres-
to the SSTL channel,” in Symp. VLSI Circuits Dig., 2002, pp. 92–93. ident of Engineering at Aeluros Inc., Mountain View, CA. Since 2007, he has
[53] M.-J. E. Lee, W. J. Dally, J. W. Poulton, P. Chiang, and S. F. Green- been a Consulting Professor at Stanford University.
wood, “An 84-mW 4-Gb/s clock and data recovery circuit for serial
link applications,” in Symp. VLSI Circuits Dig., 2001, pp. 149–152.
[54] K. L. J. Wong, M. Mansuri, H. Hatamkhani, and C.-K. K. Yang, “A
27-mW 3.6-Gb/s I/O transceiver,” in Symp. VLSI Circuits Dig., 2001, Elad Alon (S’02–M’06) received the B.S., M.S., and
pp. 99–102. Ph.D. degrees from Stanford University, Stanford,
[55] R. W. Brodersen, A. Chandrakasan, and S. Sheng, “Technologies for CA, in 2001, 2002, and 2006, respectively, all in
personal communications,” in Symp. VLSI Circuits Dig., May 1991, electrical engineering.
vol. 5, pp. 5–9. In January 2007, he joined the University of Cal-
[56] Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, “Sub-1-V ifornia, Berkeley, as an Assistant Professor of Elec-
swing bus architecture for future low-power ULSIs,” in Symp. VLSI trical Engineering and Computer Sciences, where is
Circuits Dig., Jun. 1992, vol. 6, pp. 82–83. now a codirector of the Berkeley Wireless Research
[57] V. Gutnik and A. Chandrakasan, “An efficient controller for variable Center (BWRC). He has also held visiting positions
supply-voltage low power processing,” in Symp. VLSI Circuits Dig., at Intel, AMD, Rambus Inc., Hewlett Packard, and
Jun. 1996, vol. 10, pp. 158–159. IBM Research, where he worked on integrated cir-
[58] S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, cuits for a variety of applications using bulk and SOI processes from 130 nm
and K. Flautner, “A self-tuning DVS processor using delay-error de- down to 45 nm. His research focuses on the design and implementation of
tection and correction,” in Symp. VLSI Circuits Dig., Jun. 2005, pp. energy-efficient integrated systems and the circuits/technologies that comprise
258–261. them.