Design For Test
Design For Test
Testing centers around detection of faults in a circuit. The digital world is made up of interconnected gates
Thus, only two things can fail - gates and their interconnections
A faulty gate fails to perform its function correctly A faulty interconnection produces a stuck at 1, stuck at 0, or permanently tri-stated input. Problem: can you set up experiments that produce one result if the gate/interconnect is good, and another if it is bad? This leads to two closely related concepts.
Notes adopted from Prof Sam Russ
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Controllability: An Example
A B C D 1 2 3 A B C D 1
Observability: An Example
2 3
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Some Problems
#1: Four additional test vectors are required for every additional 2-input gate. The number of test vectors increases as the number of gates increases. #2: The number of gates is increasing much faster than the number of inputs/outputs. This is making both controllability and observability more difficult. #3: Sequential circuits can be notoriously difficult to test. For example, a 16-bit counter has to cycled through its entire count for complete testing. Some strategies have emerged to deal with these problems.
Notes adopted from Prof Sam Russ
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BIST Approach
Add circuitry so that on powerup a small ROM or pseudo-random sequence generator applies a series of inputs The outputs are tested for a correct answer, usually by accumulating the outputs into a checksum value (either by XOR or Cyclic Redundancy Check CRC) The psuedo random pattern generation and checksum accumulation does not need many gates The probability of passing self-test with an undiagnosed fault can be made small (depends on number of patterns).
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Notes adopted from Prof Sam Russ
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Is Fault Coverage Sufficient Without Extra Hardware? Consider study results that show defect level vs. fault coverage
100,000 10,000 1,000 100 10 90 99 99.9
Source: 1980 study by Delco and Motorola, as cited in TIs IEEE 1149.1 Testability Primer
To get a single chip defect rate of 100 defective parts per million parts, you need 99.9% fault coverage! Do you really need a defect rate of less than 100 ppm?
Notes adopted from Prof Sam Russ
Goal PCB ppm Rate If you have 5 ASICs on a board, you need to have around 60 ppm defective ASICs to achieve 300 ppm defective boards.
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A Scan Path
SEN SI Q D C SEN SI Q D C
When SEN = 1, then DFF gets SI value, not the D value. For normal operation, SEN = 0
Assume ALL FFs in design are in tied into a Scan Path and let there be N FFs. Apply SEN = 1, and clock test vector serially into scan path. Will take N clocks. Apply, SEN = 0, and clock ONCE. This will test the design using the test vector! Apply SEN = 1, and clock in next test vector. At same time, you clocking OUT the result of the last test vector!!! After first test vector, each test vector takes N+1 clocks!!
Notes adopted from Prof Sam Russ
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B C
Scan Reg
A,B,C,D,E do not have to externally accessible!! Could be buried deep within the design (and usually they are!)
Notes adopted from Prof Sam Russ
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Basics of JTAG
The JTAG standard adds four signals to every compatible device
TCK: a clock signal for the test port TMS: Test Mode Select - determines whether or not the scan path is active and controls the mode it is in. TDI: Test Data In - serial data input TDO: Test Data Out - serial data output
JTAG Architecture
OE Input pins
BSC BSC
BSC
Output pins
BSC
BSC
The standard also specifies some standard operating modes For example, the the serial shift register can be set to bypass the chip, making access to other chips faster. Vendor specific commands be added.
Notes adopted from Prof Sam Russ
BSC
BSC
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Only four external pins needed. The JTAG port can drive outputs and capture inputs, board connections between pins can be tested!
Boundary Scan can be used to either stimulate ASICs or simply test board connections between chips.
Notes adopted from Prof Sam Russ
Identify software tools for test vector generation, fault grading Have to plan test strategy through development, prototyping, manufacturing, and maintenance Adding a JTAG bus to a board (and JTAG compatible components) can be a cost effective way of adding a large amount of testability to your design
Notes adopted from Prof Sam Russ
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Summary
The purpose of testing is to uncover faults in a system (chip or board) Faults are found by applying test vectors and observing results Test vectors can be generated manually or automatically Usually have to add extra hardware to improve testability. Scan paths can increase chip and board level testability. JTAG adds four pins and supports a variety of test modes; almost all electronics vendors support JTAG.
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