Implementation of a multi-channel UART Controller based on FIFO technique and FPGA

I.INTRODUCTION Today, owing to availability of state-of-the-art microcontrollers and digital signal processors DSPs), complex control algorithms can be easily implemented to attain the desired system performance. But in actual control systems, it is difficult to attain the expected result for various Factors affect the control systems such as control algorithms itself, capability of controllers, capability of implements equipment and states of control circumstance [1]. Except those factors, communication parameters of control systems including Baud Rate, BER (Bit Error Rate) and synchronization between sub-systems also engender great effect. In order to improve precision of control system and make good use of modern control algorithms, we should pay much more attention on communication in control systems .In several control systems, UART a kind of serial communication circuit is used widely. A universal asynchronous receive/transmit (UART) is an integrated circuit which plays the most important role in serial communication. It handles the conversion between serial and parallel data. Serial communication reduces the distortion ofa signal, therefore makes data transfer between two systems separated in great distance possible [2].In some complex systems, communications between them aster controller and slaver controllers are implemented by Serial or parallel port. Parallel communication needs a lot of multi-bit address bus and data bus and it is only convenient for short distance transmission. Serial communication is another way of communication used extensively because of its simple structure and long transmission distance. But sometimes a common serial port could not meet requirements of complex systems with different Baud Rate equipments even some special Baud Rate equipments. As showing in figure 1, in a system, the PCs Baud Rate is 115200bps and the Ep1 i.e. equipment 1s Baud Rate is57600bps, equipment 2s Baud Rate is 19200bps, and other Equipments are set at 9600bps or other Baud Rates. It is impossible to implement this multiBaud Rate communication system without a special Baud Rate converter.

In a 6-DOF robot, there are 6 sub-controllers which are all the same structure to be designed. The PC is used to implement the control algorithm of the robot and send control parameters to subcontrollers and sub-controllers are used to collect feedback signals and send them to the PC. The PC and sub-controllers communicate with each other on a RS485 BUS NET. Each sub-controller has a unique address number and the PC uses this number to identify each sub-controller. When the PC wants to send

data to node 6, it has to access front 5 nodes, this engenders time delay and makes performance of the robots each DOF not synchronization. So it reduces the control algorithms Precision and brings difficulties in researching of the control algorithm. To solve these problems described as above, we design a multi-channel UART controller based on FIFO techniques and FPGAs. It can receive data with a UART block at a certain Baud Rate and transmit data to subequipment with a UART block at the same Baud Rate or at other kind of Baud Rate which is different from the receiving Baud Rate. And it also can be used to reduce time delay between sub controllers. FPGA (Field Programmable Gate Array) is using extensively and playing more and more important roles in the designing of digital circuit. Its programmable characteristics make circuit design much more flexible and shorten the time to market. Using FPGAs can also improve the systems integration, liability and reduce power consumptions. FPGAs are always used to implement simple interface circuit or complex tate machines to satisfy different system requirements. In this paper, using a FPGAEP1C6Q produced by ALTERA and FIFO techniques design a Baud Rate converter to implement communications within equipments at different Baud Rates. FIFOs are usually used for clock domains crossing to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are different ways to design a FIFO right. This paper details one method that is used to design, synthesize and analyze a safe FIFO between two different clock domains using Gray code. In several systems such as high data collection system, high speed control system based on PCI and multi-DSP signal processing system, FIFO is used to complete communication between high speed device and low speed. Device or to complete communication between the same sub controller. FIFO is the most important part of these systems and it works as a bridge between different devices [3, 4]. As the same, in our controller, asynchronous FIFO based on FPGA is also the most important part. So the features and capabilities of the asynchronous FIFO determine the features of our controller. FIFO can be used to complete communication in parallel or serial port. A synchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data value are read from the same FIFO buffer from another clock domain, where the two clock domains are Asynchronous to each other. FIFOs are always used for data cache, storing differences of frequency or phase of Asynchronous signals. And asynchronous FIFOs are often used to quickly and safely pass data from one clock domain to another asynchronous clock domain. In asynchronous clock circuit, periods and phases of each clock domain are completely independent so the probability of data loss is always not zero. This paper introduces a way of designing FIFO based on FPGAs with high write/read speed and high reliability. Generally, a FIFO consists of a RAM Array block, a Status block, a writer pointer (WR_ptr) and a read point (RD_ptr) and its structure is showing in figure 2. A RAM array with separate read and write ports is used to stored data. The writer pointer points to the location that will be written next, and the read pointer points to the location that will be read currently. A write operation increments the writer pointer and a read operation increments the read pointer. On reset, both pointers are reset to zero, the FIFO is empty. The writer pointer happens to be the next FIFO location to be written and the reader pointer is pointing to invalid data. The responsibility of the status block is to generate the Empty and Full signals to the FIFO. If the

Full is active then the FIFO cannot accommodate more data and if the Empty is active then the FIFO can not Provide more data to readout. When writing data into the FIFO walk will be used as the clock domain and when Reading data out of the FIFO rack will be used as the clock domain. These both clock domains are asynchronous.

In designing of asynchronous FIFOs, two difficult problems cannot be ignored. One is how to judge FIFOs status according to the writer pointer and read pointer. The other is how to design circuit to synchronize asynchronous clock domains to avoid Met stability.
B. Status of Empty and Full of FIFO

Creating empty and full signals is the most important part of designing a FIFO. No matter under what circumstance, the read and write pointers cannot point to the same address of the FIFO. So, the empty and full signals play very important roles within FIFO that they block access to further read or write respectively. The critical importance of this blocking lies in the fact that pointer positions are the only control that is over the FIFO, and write or read operation changes the pointers. Generally, in an ordinary FIFO, when the read pointer equals to the writer pointer the FIFO is empty. But in a circular FIFO it is either empty or full when both of the pointers are equal. Because the full and empty signals can not only be decided by the pointers value but also be influenced by the operation that caused the pointers to become equal. If a reset or read makes the pointers equal to each other, the FIFO is really empty. If a write makes the pointers equal, the FIFO is full [5]. In order to exactly know whether the FIFO is full or empty, we can set a direction flag keeps track of what causes the pointers to become equal to each other. The flag tells the status circuit the direction in which the FIFO is currently headed. The implementation of the direction flag is a little complex because you have to set the threshold of going toward full and going toward empty. In this paper, this method is instead of another design technique used to distinguish between full and empty is to add an extra bit to each pointer. The pointers length n Equals to log2 (array _ size) .The array _ size is the depth of the FIFO needed in a project. For example, when setting the array _ size of the FIFO 64 byte (8 bits one byte), the writer and read pointers length is 2 log 64 = 6 . Using n +1 bits pointer when n is the number of address bits required to access the entire FIFO memory buffer. When both pointers including the MSBs are equal the FIFO is empty. And the FIFO is full when both pointers, except the MSBs are equal. As figure 3 showing, when the array _ size of the FIFO is 8 bytes, the number of address

Bits required to access the entire FIFO memory buffer is 4. With an additional address bit the full and empty signals can be easily created [5, 6].

The status block fundamentally performs operations on the two pointers, and these run off two different clock mains. This is what causes the real difficulty. If you were to sample the read pointer with the write pointer (or vice versa), you will potentially run into a problem called met stability. Met stability is the name for the physical phenomenon that happens when an event tries to sample another event. In a physical circuit the met stability causes the output uncertainty either be a logical 1 or a logical 0 or something between. In physical systems, sampling an event by another event yields unpredictable results. Unpredictability also implies another phenomenon and this is the real danger that met stability poses. To eliminate these kinds of problems caused by met stability is a difficulty in designing a FIFO [5,
7].

C. Solutions of Met stability Met stability can cause unpredictable problems in a FIFO, so in the designing stage we should do the best to reduce the met stability. If asynchronous element is in a system, bmetastability is unavoidable. There is absolutely no way to eliminate met stability completely, so what we do is calculate a probability of error and express this in terms of time ie. MTBF (Mean Time between Failures). MTBF is a statistical measure of failure probability, and requires some Much more complex, empirical and experimental data to arrive at. In a D flip-flop, when the input signal changes instantaneously from 0 to 1 at timed = 0 , the value of Q is nun certain. This is met stability. In the FIFO, it needs to sample the value of a counter with a clock that is synchronous to the counter clock. Thus it will meet a situation where the counter is changing from FFFF to 0000, and every single bit goes detestable. This means that the counter would potentially read any value between FFFF to 0000 and the FIFO does not work. The most important things that must to be done are to make sure that not all bits of the counter will change simultaneously. In order to minimize the probability of occurrence of such errors, we should make sure that precisely one bit changes every time the counter increments. So we need a counter that counts in the Gray codes. Gray codes are named after the person who originally patented the code back in 1953, Frank Gray. Gray code is different form binary code that is

every next value differs from the previous in only one bit position. The conversion between the Binary codes and the Gray codes is as following: