AN INTRODUCTION TO MICROCOMPUTERS

eft
VOLUME
I

BASIC CONCEPTS
Copyright

1976 by

Adam

Osborne and Associates. Incorporated

I97G
-

Is! Prinlinq.

2nd

Printing

1977
o!

AH

rights reserved. Printed

in

in

(he United States

reproduced stored
ars.

a retrieve

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cr transmitted

America No pan of this publication ma i be in anv form or by any means, slectront

oi
1
i

mechanical, photocopying, recording, or ccherwisi;. without the pr or witter permiasJOi

Published by
P.O.

Adam Osborne and

Box 2036. Berkeley

Associates, Incorporated
California

94702

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TABLE OF CONTENTS
CHAPTER
1

PAGE

WHAT

IS

A MICROCOMPUTER

1-1

THE EVOLUTION OF COMPUTERS THE ORIGINS OF THE MICROCOMPUTER

1-1

1-4 1-6
1-6

ABOUT

THIS

HOW

THIS

BOOK BOOK HAS BEEN PRINTED

SOME FUNDAMENTAL CONCEPTS

NUMBER SYSTEMS DECIMAL NUMBERS BINARY NUMBERS CONVERTING NUMBERS FROM ONE BASE TO ANOTHER OTHER NUMBER SYSTEMS
BINARY ARITHMETIC BINARY ADDITION BINARY SUBTRACTION BINARY MULTIPLICATION BINARY DIVISION

2-1 2-1 2-1 2-1

2-2

2-4
2-5 2-5 2-5 2-7 2-7 2-7

BOOLEAN ALGEBRA AND COMPUTER LOGIC

"OR" OPERATION

2-8 2-8 2-9 2-9 2-9

"AND" OPERATION "EXCLUSIVE OR" OPERATION "NOT" OPERATION COMBINING LOGICAL OPERATIONS DE MORGAN'S THEOREM
THE MAKINGS OF A MICROCOMPUTER

2-10
3-1 3-1

MEMORY ORGANIZATION MEMORY WORDS

THE BYTE

3-3
3-4 3-4

MEMORY ADDRESSES
INTERPRETING THE CONTENTS OF

MEMORY WORDS

3-10
3-11

STAND ALONE PURE BINARY DATA INTERPRETED BINARY DATA CHARACTER CODES INSTRUCTION CODES
THE MICROCOMPUTER CENTRAL PROCESSING UNIT

3-12

3-20 3-22
4-1 4-1

CPU REGISTERS HOW CPU REGISTERS ARE USED THE ARITHMETIC AND LOGIC UNIT THE CONTROL UNIT STATUS FLAGS
INSTRUCTION EXECUTION INSTRUCTION TIMING INSTRUCTION CYCLES

4-4
4-11

4-11

4-12 4-16 4-16 4-17

HOW MUCH SHOULD AN

INSTRUCTION DO?

4-25

TABLE OF CONTENTS (CONTINUED)

CHAPTER
MICROPROGRAMMING AND THE CONTROL UNIT MICROPROCESSOR BASED MICROCOMPUTERS CI-HP SLICE BASED MICROCOMPUTERS
REGISTERS ARITHMETIC AND LOGIC CHIP SLICE THE CHIP SLICE CONTROL UNIT COMBINING ARITHMETIC AND LOGIC UNIT WITH CONTROL
UNIT
5

PAGE
4-31

4-36 4-44 4-47 4-59 4-65

5-1 5-1 5-1

LOGIC BEYOND THE CPU

PROGRAM AND DATA MEMORY

READ-ONLY MEMORY (ROM) READ-WRITE MEMORY (RAM) TRANSFERRING DATA BEYOND THE MICROCOMPUTER SYSTEM (INPUT/OUTPUT)

5-5
5-8

PROGRAMMED
INTERRUPT I/O

I/O

5-8

5-14 5-18
5-22

A MICROCOMPUTER'S RESPONSE TO AN INTERRUPT

INTERRUPTING DEVICE SELECT CODES INTERRUPT PRIORITIES DIRECT MEMORY ACCESS CYCLE STEALING DIRECT MEMORY ACCESS DMA WITH MULTIPLE EXTERNAL DEVICES

5-26 5-34
5-37
5-41

SIMULTANEOUS DMA SIMULTANEOUS VERSUS CYCLE STEALING THE EXTERNAL SYSTEM BUS SERIAL INPUT/OUTPUT
IDENTIFYING SERIAL TELEPHONE LINES

5-45

DMA

5-47 5-47

5-48
5-49

DATA

BITS

5-54
5-55 5-55 5-56
5-57

ERROR DETECTION SERIAL INPUT/OUTPUT PROTOCOL

SYNCHRONOUS SERIAL DATA TRANSFER SYNCHRONOUS TELEPHONE PROTOCOL ASYNCHRONOUS SERIAL DATA TRANSFER SERIAL I/O COMMUNICATIONS DEVICE DUAL IN-LINE PACKAGE SIZE
LOGIC DISTRIBUTION

5-59 5-60 5-60

5-61 5-61

THE CPU-SERIAL I/O DEVICE INTERFACE THE SERIAL I/O INTERFACE SERIAL I/O CONTROL SIGNALS MODEM CONTROL SIGNALS CONTROLLING THE SERIAL I/O INTERFACE DEVICE ADDRESSING THE SERIAL I/O INTERFACE DEVICE REALTIME LOGIC
LOGIC DISTRIBUTION

5-62 5-65
5-66

5-67 5-68 5-69

AMONG MICROCOMPUTER

DEVICES

5-70

TABLE OF CONTENTS (CONTINUED)

CHAPTER
6

PAGE
PROGRAMMING MICROCOMPUTERS
THE CONCEPT OF A PROGRAMMING LANGUAGE SOURCE PROGRAMS OBJECT PROGRAMS CREATING OBJECT PROGRAMS PROGRAM STORAGE MEDIA
6-1

6-1

6-2 6-3

6-4
6-5

ASSEMBLY LANGUAGE ASSEMBLY LANGUAGE SYNTAX ASSEMBLER DIRECTIVES

6-5 6-6
6-11

MEMORY ADDRESSING
MICROCOMPUTER MEMORY ADDRESSING
IMPLIED MEMORY ADDRESSING DIRECT MEMORY ADDRESSING DIRECT VERSUS IMPLIED ADDRESSING

WHERE

6-12
IT

BEGAN

6-12 6-13

6-14 6-14
6-15 6-18

VARIATIONS OF DIRECT MEMORY ADDRESSING PAGED DIRECT ADDRESSING DIRECT MEMORY ADDRESSING IN MICROCOMPUTERS

6-24
6 32 6 32 6 . 32 6-34

AUTO INCREMENT AND AUTO DECREMENT

THE STACK

MEMORY STACKS THE CASCADE STACK HOW A STACK IS USED NESTED SUBROUTINES AND USE OF THE STACK INDIRECT ADDRESSING
A PAGED COMPUTER'S INDIRECT ADDRESSING PROGRAM RELATIVE INDIRECT ADDRESSING
INDIRECT ADDRESSING

6-34
6-37 6-38 6-38
6-41
6 _ 42

MINICOMPUTERS VERSUS
...

MICROCOMPUTERS
INDEXED ADDRESSING

6 . 44

MICROCOMPUTER INDEXED ADDRESSING

7

6-48
7_
y

'

AN INSTRUCTION SET
CPU ARCHITECTURE STATUS FLAGS ADDRESSING MODES A DESCRIPTION OF INSTRUCTIONS INPUT/OUTPUT INSTRUCTIONS MEMORY REFERENCE INSTRUCTIONS SECONDARY MEMORY REFERENCE (MEMORY REF^RCNC^
OPERATE) INSTRUCTIONS LOAD IMMEDIATE INSTRUCTIONS JUMP AND JUMP-TOSUBROUTINE IMMEDIATE OPERATE INSTRUCTIONS BRANCH ON CONDITION INSTRUCTIONS REGISTER-REGISTER MOVE INSTRUCTIONS REGISTER-REGISTER OPERATE INSTRUCTIONS

7 _1 7.4
7_4

7.5
7.5 7_8
7 _ 15

7 _ 19

7_23

7_25
7.3

7-32

TABLE OF CONTENTS (CONTINUED)

CHAPTER
REGISTER OPERATE INSTRUCTIONS STACK INSTRUCTIONS

PAGE
7-36

PARAMETER PASSING INSTRUCTIONS

INTERRUPT INSTRUCTIONS

STATUS INSTRUCTIONS HALT INSTRUCTIONS

7-44 7-46 7-48 7-52

7-53 7-53

AN INSTRUCTION SET SUMMARY

APPENDIX

STANDARD CHARACTER CODES

A-1

LIST OF FIGURES
FIGURE
1-1

PAGE
A
Microcomputer Chip And DIP
Digits
xvii

2-1

A
A

Symbolic Representation Of Binary Represented By A Bistable Device

1024-Bit

2-1

3-1
4-1

Memory

Device

3-5

Functional Representation Of
Control Unit Signals For
Register. Arithmetic

Control Unit

4-12
4-37

4-2

Simple Microcomputer
Slice

4-3 4-4
5-1

And

Logic Unit From Figure 4-1. Reorganized

To Meet The Needs Of A Chip

4-50

Two

4-Bit

ALU

Slices

Concatenated To Generate

An

8-Bit

ALU

4-51
5-2 5-3
5-5

5-2

5-3 5-4 5-5

5-6 5-7

Read-Only Memory Chip Pins And Signals ROM And CPU Connected Via External Data Bus Read-Write Memory Chip Pins And Signals

RAM

(Without

RAM

Interface).

ROM And CPU

Chips Connected Via

5-6
Via External Data Bus

External Data

Bus

RAM Interface. ROM And CPU Chips Connected A Single Port, Parallel I/O Interface Device A Two-Port. Parallel I/O Interface Chip
Parallel

5-7

5-10
5-11

5-8
5-9

I/O Interface Chip Using I/O Addressing Logic

5-13 5-15

5-10

Microcomputer Controlling The Temperature Of Shower Water An External Device Using An Interrupt Request To Let The
Microprocessor

Know

That Data

Is
"

Ready To Be Input
5-11

5-17

Using I/O Chips

5-12

An

External

And ROM Chips To Handle Interrupts Device Using An Interrupt Request And A

5-23

Device Identification Code To Let The Microcomputer Know That Data Is Ready To Be Input

5-24
5-27

5-13 5-14
5-15 5-16
5-17

An An

Interrupt Priority Device Interrupt Priority Device

Connected To The External System Bus

Operations For Five External Devices

5-30
5-35 5-42 5-46
5-71

Cycle Stealing Direct

Memory Access

DMA
Using

Device Controlling

DMA

Data. Address
Serial

And

Control Paths

5-18
6-1

I/O With Interrupt

Used In Simultaneous DMA To Send Received Data To The CPU

A A

6-2 6-3

An

Source Program Written On Paper Object Program On Paper Tape Paper Tape Source Program
.

6-3
6-3 6-4

LIST
TABLE
2-1 3-1

OF TABLES
PAGE

Number Systems
Computer Word Sizes Signed Binary Numeric

2-4 3-3
Interpretations

3-2 3-3
4-1

3-14
3-17 4-37

Binary Representation Of Decimal Digits

Control Unit Signals

'

4-2

Data Flow Select

When C0 =

Or C1 =1

4-3
4-4 4-5

ALL! Select Signals

An

Instruction Fetch

Microprogram

4-6
4-7 4-8

4-9

Accumulator Microprogram Three-Instruction Memory Read One Instruction To Load 16-Bit Address Into Data Counter Single Instruction, Direct Addressing, Memory Read ALU Sources As Defined By The Low Order Three
Microinstruction Bits

A Complement

4-38 4-38 4-40 4-42

4-42 4-43

4-43
4-51

4-10
4-1 5-1
7-1

ALU ALU
Serial

Operations Specified By Middle Microcode

Bits

4-53 4-54
5-67 7-55

Destinations Specified By Last Three Microcode Bits

I/O

Mode

Parameters

A Summary

Of The Hypothetical Microcomputer Instruction Set

QUICK INDEX
INDEX

PAGE
ABSOLUTE BRANCH
4-30
4-1

ACCUMULATOR ACCUMULATOR DATA COUNTER ADDITION ADD ADD BINARY ADD DECIMAL ADD IMMEDIATE ADD OPERATION SIGNALS AND TIMING ADDRESS BITS THE OPTIMUM NUMBER
-

7-33 7-15 7-33

7-15. 7-33

7-24

4-22
61

ADDRESS SPACE ADDRESSING MATRICES ALU INPUT IDENTIFIED ALU SLICE

3-10 7-33 4-50 4-48

7-15. 7-19

AND AND IMMEDIATE

ARITHMETIC SHIFT

7-33

7-24
7-37
6-6

ASSEMBLER ASSEMBLER DIRECTIVES - THEIR VALUE ASSEMBLY LANGUAGE INSTRUCTION MICROPROGRAMS ASYNCHRONOUS EVENTS AUTO DECREMENT AUTO INCREMENT AUTO INCREMENT AND SKIP JUSTIFICATION AUTO INCREMENT OR DECREMENT JUSTIFICATION
v

7-23
4-41

5-34 7-10 7-10

7-12 7-12
6-21

BASE PAGE BAUD RATE BCD ARITHMETIC BINARY CODED DECIMAL

BINARY BINARY BINARY BISYNC
BITS
DIGIT

5-53 3-18 3-16

2-1

SUBTRACT TO DECIMAL CONVERSION PROTOCOL

-

7-17
2-2

5-57
3-1

BOOLEAN LOGIC JUSTIFIED BRANCH INSTRUCTION BRANCH ON CONDITION INSTRUCTION JUSTIFICATION BRANCH ON LESS EQUAL OR GREATER BRANCH ON WHAT CONDITIONS? BRANCH PHILOSOPHY BRANCH TABLE BRANCHING AT PAGE BOUNDARY
BYTES AND
C

7-18 4-30 7-26 7-29 7-28 7-26

7-35. 7-52

WORDS

4-30 3-4
4-58 4-59 4-58

CARRY GENERATION CARRY GENERATE DEVICE CARRY LOOK AHEAD

QUICK INDEX
INDEX
CARRY PROPAGATION CARRY STATUS CHARACTER SETS
CHIP

(Continued)
PAGE
4-58
4-12, 4-58

3-20
1-1

CHIP SLICE CHIP SLICE

ALU DESTINATION ALU OPERATION IDENTIFICATION

4-53

4-52
4-52 4-54 4-44 7-40 7-36
5-49. 5-53

CHIP SLICE ARITHMETIC

AND

LOGIC UNIT

CHIP SLICE STATUS CHIP SLICING PHILOSOPHY

CLEAR CLEAR REGISTER CLOCK SIGNALS

5-63

COMMENT
COMPARE

FIELD

6-10

7-15,7-17
7-33

COMPARE IMMEDIATE COMPLEMENT COMPLEMENT MICROPROGRAM COMPUTED JUMP COMPUTER HOBBYISTS THE CONCEPT OF AN INTERRUPT CONDITIONAL RETURN FROM SUBROUTINE
CONVERTING FRACTIONS CPU CPU OPERATE INSTRUCTIONS CPU PINS AND SIGNALS CPU REGISTERS SUMMARY
CYCLIC

7-24
7-36, 7-40

4-41
7-31
1-4

5-14 7-30 2-3

4-1

4-29 4-18
7-4

REDUNDANCY CHARACTER
I/O INTERFACE DEVICES

5-55
5-31
4-3, 7-1

DAISY CHAINING WITH

DATA COUNTER DATA PATHS

DECIMAL ADJUST DECIMAL TO BINARY CONVERSION

4-49 7-17
2-2

DECREMENT REGISTER DEFINE ADDRESS DEFINE ADDRESS DIRECTIVE DEFINE CONSTANT

DEVICE DEVICE SELECT LOGIC DIRECT ADDRESSING DIRECT ADDRESSING JUSTIFICATION DISABLE INTERRUPT DMA BEING TURNED OFF DMA CAUGHT ON THE FLY

7-40
6-12
7-35

6-12
1-1

5-32
4-27, 7-9

7-13

7-50 5-39
5-39
5-41

DMA END

QUICK INDEX
INDEX

(Continued)
PAGE

DMA DMA DMA

EXECUTION
INITIALIZATION

5-39

WRITE TIMING

5-38 5-40
3-7

DYNAMIC RAM
EDITORS EFFECTIVE ADDRESS EFFECTIVE MEMORY ADDRESS ENABLE INTERRUPT
' END DIRECTIVE EQUATE ASSEMBLER DIRECTIVE EQUATE DIRECTIVE EXCHANGE EXCLUSIVE OR

6-4

6-47

6-19 7-50
6-11

7-22
6-11. 7-35

7-32
7-15. 7-19

EXTENDED DIRECT ADDRESSING EXTERNAL DATA BUS EXTERNAL LOGIC REQUIREMENTS

F

7-33 6-24
5-1

4-22

FIELD IDENTIFICATION

FLOATING BUSSES

FRAMING FRAMING ERROR FULL DUPLEX

6-10 5-39 5-59 5-60 5-55

4-19
5-55 5-16
2-4

G
H

GROUND
HALF DUPLEX HANDLING AN INTERRUPT REQUEST

HEXADECIMAL NUMBERS
IMMEDIATE INSTRUCTIONS JUSTIFICATION IMMEDIATE OPERATE INSTRUCTIONS JUSTIFIED IMPLIED ADDRESSING INCREMENT AND DECREMENT INCREMENT AND SKIP INCREMENT REGISTER
INDEX REGISTER INDIRECT ADDRESS INDIRECT ADDRESS COMPUTATION INDIRECT AUTO INCREMENT AND DECREMENT INDIRECT VIA BASE PAGE

7-19

7-24
7-9

7-36

7-10 7-40
6-45

6-38
-38
-41

-40
-37
-6

CONTROL INPUT LONG INPUT SHORT

INHIBIT

7-6

INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION

EXECUTE FETCH FETCH SIGNALS AND TIMING

REGISTER

4-18 4-17
4-19 4-3
>

QUICK INDEX
INDEX

(Continued)
PAGE

INSTRUCTIONS INTERMEDIATE CARRY STATUS INTERRUPT ACKNOWLEDGE INTERRUPT ADDRESS VECTOR INTERRUPT PRIORITIES AND WHAT THEY MEAN INTERRUPT PRIORITY AND DAISY CHAINING INTERRUPT PRIORITY AND MULTIPLE REQUEST LINES INTERRUPT PRIORITY CHIP INTERRUPT REQUEST INTERRUPT SERVICE ROUTINE INTERSIL IM6100
I/O I/O I/O

4-4

4-13
5-16. 7-50

5-19 5-26

5-29 5-28 5-26 5-16 5-19 6-15 5-12

5-12 5-9

CONTROL PORT ADDRESSES

PORTS I/O PORTS ADDRESSED USING MEMORY ADDRESS LINES I/O STATUS ISOSYNCHRONOUS SERIAL I/O

5-10 5-12
5-67 7-22
4-30, 7-20
7-22. 7-23

JUMP JUMP INSTRUCTION JUMP TO SUBROUTINE JUMP TO SUBROUTINE INSTRUCTION JUMP TO SUBROUTINE ON CONDITION
LABEL FIELD LARGE SCALE INTEGRATION LITERAL OR IMMEDIATE DATA

7-44
7-21

7-30
6-7
1-3

4-6
7-8

LOAD LOAD LOAD LOAD LOAD

DATA COUNTER SIGNALS AND TIMING

DIRECT

IMMEDIATE
IMPLIED

4-23 7-10 7-22

7-10
7-11 7-11

LOAD/STORE WITH AUTO INCREMENT AND SKIP LOAD/STORE WITH AUTO INCREMENT OR DECREMENT
MACROINSTRUCTION COMPLEXITY MACROINSTRUCTIONS MACROLOGIC MARKING MEDIUM SCALE INTEGRATION

4-36 4-34 4-36 5-54

1-3

MEMORY MODULE MEMORY READ SIGNALS AND TIMING MEMORY WRITE SIGNALS AND TIMING MICROCOMPUTER MEMORY CONCEPTS
MICROCOMPUTER SYSTEM BOUNDS MICROINSTRUCTION BIT LENGTH
MICROINSTRUCTIONS

3-6

4-21

4-22
3-5
5-8

4-39 4-34

QUICK INDEX
INDEX

(Continued)
PAGE

MICROPROCESSOR MICROPROCESSOR SLICE MICROPROGRAM COUNTER MICROPROGRAM SEQUENCER LOGIC MICROPROGRAMMABLE MICROCOMPUTER

4-1

4-36 4-60 4-45 4-36

MICROPROGRAMS
MINICOMPUTER MEMORY CONCEPTS

4-34 3-5
6-6

MNEMONIC

FIELD

MODEM
MOVE
MULTIBYTE ADDITION MULTIBYTE BINARY ADDITION MULTIBYTE BINARY SUBTRACTION MULTIFUNCTION DEVICES MULTIPLE STACKS MULTIPLEXED LINES MULTIWORD BINARY DATA MULTIWORD SIGNED BINARY NUMBERS
NEGATIVE BCD DATA
NIBBLES

5-48
7-32
7-17

3-12

3-13

5-34
7-31

5-20
3-12 3-16 3-16
3-4
3-1

NON VOLATILE MEMORY NUMBER OF LOAD AND STORE INSTRUCTIONS NUMBER OF REGISTERS
OCTAL NUMBERS ONES COMPLEMENT OPERAND FIELD OR OR IMMEDIATE
ORIGIN DIRECTIVE

7-9
7-1

2-4
2-6

6-8
7-15, 7-33

7-24
6-11. 7-35

OUTPUT LONG OUTPUT SHORT OVERFLOW STATUS OVERFLOW STATUS SET STRATEGY
PACKING
ASCII DIGITS

7-7 7-7
4-14, 4-55

4-16 7-43

PAGE BOUNDARY ERROR PAGE NUMBER PAGED DIRECT ADDRESSING PAPER TAPE PARAMETER PASSING
PARITY PARITY BITS PARITY STATUS

6-20
6-19 6-30
6-3

7-46 3-20
5-55. 5-60

PASS PARAMETER INSTRUCTION PASSING PARAMETERS TO SUBROUTINES

PDP-8

4-16 7-47 7-47 6-15

QUICK INDEX
INDEX
POP
POST-INDEXING POWER FAIL INTERRUPT POWER SUPPLIES PRE-INDEXING

(Continued)
PAGE
6-33, 6-34.

7-44
6-47
5-31
-19

-46
-6

PRIMARY ACCUMULATOR PROGRAM COUNTER PROGRAM LOOP PROGRAM RELATIVE BRANCH PROGRAM RELATIVE PAGING PROTOCOL IN SERIAL DATA
PUSH

-3

-28

-30

6-22 '5-54
6-33, 6-34,

7-44

RAM RAM
.

3-2

CHIP

MEMORY

SIZE

3-7

RECURSIVE SUBROUTINES REFERENCING DATA TABLES REGISTER BLOCK REGISTER TO REGISTER MOVE INSTRUCTIONS JUSTIFIED REGISTER TO REGISTER OPERATE INSTRUCTIONS JUSTIFICATION RESTORING REGISTERS FROM STACK RETURN FROM INTERRUPT RETURN INSTRUCTIONS

6-37

4-28

4-49
7-31

7-33
7-52 7-50 7-45

RETURN FROM SUBROUTINE

7-44
3-2 5-2

ROM ROM

DEVICE SELECT

ROTATE
SAVING REGISTERS AND STATUS SAVING REGISTERS ON STACK SECONDARY MEMORY REFERENCE INSTRUCTIONS
JUSTIFICATION

7-37

5-18
7-51

7-17
5-21
'

SELECTING I/O DEVICES

SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL SERIAL

DATA DATA DATA DATA DATA

I/O I/O I/O

HANDSHAKING
INPUT

OUTPUT
RECEIVING CLOCK SIGNAL TRANSMITTING CLOCK SIGNAL

5-57 5-63 5-64

5-51 5-51

COMMANDS
ERROR CONDITIONS

5-67
5-67 5-68
5-67 5-65

I/O INPUT

CONTROL SIGNALS

MODE
CONTROL

RECEIVE CONTROL SIGNALS RECEIVE SYNCHRONIZATION

SYNCHRONOUS HUNT MODE

5-65 5-57

QUICK INDEX
INDEX

(Continued)
PAGE

SERIAL TRANSMIT CONTROL SIGNALS SERIAL XI CLOCK SIGNAL SERIAL X16 CLOCK SIGNAL SERIAL X64 CLOCK SIGNAL

5-65

5-&
5-53 5-53
1-3

SEVENTY FOUR HUNDRED INTEGRATED CIRSMTS-

ROTATE ROTATE INSTRUCTIONS ROTATE THROUGH CARRY SHIFT ROTATE WITH BRANCH CARRY SHIFT MULTIBYTE SHIFTING BINARY CODED DECIMAL DATA SIGN OF ANSWER IN SUBTRACTION SIGN PROPAGATION SIGN STATUS SIGNAL SETTLING DELAY
SHIFT SHIFT

SHIFT SHIFT

7-36

AND AND AND AND

7-36 7-40
7-37 7-37
7-41

7-38
2-7

4-31
4-13. 4-54

5-51

SIGNAL SETTLING TIME SIGNED BINARY NUMBERS SIMPLE SHIFT AND ROTATE SIZE OF CHIP SELECT

5-50 3-14
7-37
3-9 3-8

OF MEMORY ADDRESS PHILOSOPHY STACK POINTER START BIT

SIZE SKIP

7-26
6-32

5-59
3-7

STATIC

RAM

STATUS IN MICROPROGRAMS STATUS RESET STATUS SET STOP BITS STORE STORE DIRECT STORE IMPLIED SUBROUTINE CALL SUBROUTINE PARAMETER PASSING SUBROUTINE PARAMETERS SUBROUTINE RETURN SUBROUTINES SUBTRACT DECIMAL SWITCH CHANGE TESTS SWITCH TESTING SYNC CHARACTER
TELETYPE SERIAL DATA FORMAT TENS COMPLEMENT TRI-STATE BUFFER TRUTH TABLES TWELVE-BIT WORD DIRECT ADDRESSING

4-41

7-53

7-53
5-59. 5-60

7-8

7-10 7-10
6-35 7-44 7-46 6-36
6-34. 7-22
7-15, 7-33

7-18 7-42 5-54

5-60
2-5

5-47
2-8

6-15

QUICK INDEX
INDEX

(Continued)
PAGE

TWOS COMPLEMENT
V
VOLATILE

2-6
3-1

MEMORY
MODIFIED

W
Z

WHEN STATUSES ARE WORD SIZE

ZERO STATUS

4-13
3-3

-4-13,4-55

figure 1-1

Microcomputer Qijp And DIP

Chapter 1 WHAT IS A MICROCOMPUTER

A
logic devices,

microcomputer is a logic device. More precisely, it is an indefinite variety of implemented on a single chip; and because of the microcomputer, logic design will never be the same again.

The word "microprocessor" is also widely used in conjunction with microcomputers. The term "microprocessor" was coined to reflect the limited functions of these devices as compared to computers; a microprocessor, therefore, represents something less than a microcomputer. Current trends have blurred the distinction between "microprocessors" and "microcomputers"; therefore in this book we use only the term "microcomputer", identifying logic implemented on chips by
specific function

using
a

traditional terminology.
|

microcomputer. The logic of the microcomputer is on a chip, which is mounted in a Dual In-Line Package (DIP). We refer to the DIP as a logic device, as opposed to the silicon wafer, which is a logic chip.
Figure
1-1
illustrates

_____
\

CHIP

DEVICE
imply.

The microcomputer

is

also a digital computer, as its

name would

There are, indeed, striking similarities between microcomputers and other comvia instruction sets, puters. The established method of comparing computers makes some microcomputers look so addressing modes and execution speeds similar to other computers that any distinction between the two products appears to be a distinction in search of a difference.

But microcomputers are a new and different product, and that is why the established method of comparing computers does not apply to microcomputers. Instruction sets, addressing modes and execution speeds are of secondary importance to the microcomputer user. The distribution of logic on chips and the price of microcomputer devices are the comparisons of primary importance; and it is these comparisons that set microcomputers apart from all other types of computer, as a new and different product.

The purpose
addition;

of this

book

is

they must be evaluated computer comparisons.

why

to explain not only what microcomputers are but, in in a way that differs so markedly from prior

The book does not assume you understand how computers work; therefore, computer concepts are described, beginning with
first principles.

other computers share a common ancestor, however. To acquire a little perspective, we will therefore begin with a short history of computer evolution and identify the origins of the microcomputer.

Microcomputers and

all

THE EVOLUTION OF COMPUTERS

Today's smallest microcomputer and largest mainframe computer share a common the UNIVAC 1 which was built out of vacuum tubes in 1 950, and filled ancestor a room; yet it had less computing power than most of today's microcomputers.

1-1


UNIVAC
limited
1,

and the vacuum tube computers that followed, were used

for a very

of "expense-is-no-object" applications, frequently to solve mathematical problems that might otherwise be impossible to solve.

number

The vacuum tube computer's

plications; its logic

logic was not particularly well suited to scientific apwas the immediate and natural consequence of being built out of

bistable logic devices

the building block of every

digital

computer.

Indeed, the basic concepts for the design of a computing machine go all the way back to Charles Babbage, who in 1833 laid out the concepts that can be found, with minor variations, in every digital computer built today. In Chapters 2 and 3 we describe these basic concepts concepts that allow computing logic to be built out of binary digits, irrespective of how the computer will be used.

What we
been no

is that since the dawn of the computer industry, there have breakthroughs in the basic concepts of computing. It is advances in solid state physics that have been the computer industry's evolutionary force. New electronic technology has caused computer prices to fall so rapidly that every few years entire new markets have been engulfed by computers.

are saying

radical

In 1960 computer prices had declined to the point where they could be used for data processing, and the day of the general purpose computer had arrived.

1965 the PDP-8, at $50,000, brought computers into the laboratory and the manufacturing plant's production line; and the minicomputer industry was born. Today minicomputers cost as little as $1,000, and their sphere of influence has spread as prices have come down.
In

where

But microcomputer prices range from $5 to $250 and we have entered an era a computer can control a washing machine or an oven, or it can be a component in consumer products that are mass merchandised.
are the advances in solid state physics that
is

What
fifties

we

speak of?

The vacuum tube

it

was

a bulky device with expensive internal elements. In the late replaced by the transistor, a small piece of germanium metal, suitably

doped with

impurities.

Soon an array

of discrete,

low cost components were

available;

signal inverter:

An AND

gate:

o
gate:

D>
AB

An OR

gate:

r>

A+B

An EXCLUSIVE OR

>
as a single,

AB+AB

A NOT AND

gate could have been:

but instead

was designed

new NAND

gate:

AB
*" b

1-2

Four

single

NAND gates were built NAND gate) to give a

into

one chip (costing the same as. or little more than, a quadruple 2-input positive-NAND buffer:

affectionately

Devices such as the quadruple 2-input positive-NAND buffer spawned a whole range of devices, known, by a generation of logic designers, as 7400 series integrated circuits.

Indeed, the

7400

series integrated circuits, in their day,

industry as microcomputers are having today;

had as deep an impact on the electronics because 7400 series integrated circuits converted a
---

generation of "circuit designers" into a generation of "logic designers" occurred almost overnight.

and the conversion

Four gates on one chip became ten, and then a hundred, and then a thousand; today ten thousand gates worth of logic can be implemented on a single silicon chip, and the end is by no means predictable, or even in sight.

chip with a number of gates on it is called an integrated cirIf there are approximately 100 to 1000 gates on a chip, we refer to the logic as Medium Scale Integration (or MSI). At some
cuit.

7400

INTEGRATED
CIRCUITS

ill-defined level,

above 1000 gates of

logic

on a chip,

we are talkMEDIUM SCALE

INTEGRATION

ing of Large Scale Integration (or LSI).

The

interesting aspect of integrated circuits is that the cost of a chip is a function of physical size it is not a function of how

much
chips

logic

has been implemented on the chip. Therefore, as

built.

LARGE SCALE
INTEGRATION

become more complex, cheaper computers can be

Two
1

aspects of the amazingly shrinking computer need to be

if

clarified:

Does the whole computer shrink? And

the microcomputer puters?
If

not,

which parts remained the same?

it

2)

is

so inexpensive,

why

has

not eliminated

all

other com-

all, the whole computer cannot shrink; only the electronics can. What remains is the human interface consoles and switches, means for accepting data inputs and generating results in human readable form all the parts of the computer that are unnecessary once a computer becomes a logic device.

First of

The microcomputer

will never eliminate all other computers because when computers are used to process data or solve scientific problems, there is a relentless economic need to make the computer more powerful. So with every major advance

1-3

-oiid state electronics technology, you get two new products: a yesterday's computer and a more powerful "today's" computer:

RANGE OF COMPUTERS

FIRST

COMPUTER
FOUR MAJOR ADVANCES IN SEMICONDUCTOR TECHNOLOGY

CHEAPEST COMPUTER

As time went

by, there developed a considerable spread between the capabilities of the cheapest computer and the most powerful computer. Thus in 1965 the first ar-

bitrary division

was made

between minicomputers and

large computers.

We will

not attempt to define what a minicomputer is, as against a large computer. A minicomputer is a minicomputer because the product's manufacturer calls it a

minicomputer.
In

1970, a second arbitrary division was made, between minicomputer and microcomputer; but this time the differences between products are easier to define:
logical devices, destined to

microcomputer is sold as one, or a very few components in a larger logic system.

become

By way
But
ring

of contrast, all other computers are vehicles for the execution of computer programs, each of which transiently defines the function of the computer system.
this definitive difference

between a "minicomputer" and

"microcomputer"

is

already blur-

for

two reasons:
is

First,

the day of the computer hobbyist

here; the hobbyist builds his

own computer out

like

of a microcomputer, then writes

programs

for

it

COMPUTER
HOBBYISTS

just

any minicomputer programmer would do.

Second, an increasing number of "microcomputers" are single chip implementations of existing "minicomputers"

THE ORIGINS OF THE MICROCOMPUTER

Since this is a book about microcomputers, nated in the first true microcomputer.
let

us look at the events which culmi-

Datapoint Corporation of San Antonio, Texas, are a manufacturer of "intelligent terminals" and small computer systems. In 1969, they (along with Cogar and Viatron) attempted to make a "great leap forward." Datapoint engineers designed a very elementary computer, and contracted with Intel and Texas Instruments to implement the design on a single logic chip. Intel succeeded, but their product executed instructions approximately ten times as slowly as Datapoint had specified; so Datapoint declined to buy, and built their own product using existing logic components.

were left with a computer-like logic device, whose development had been paid They were faced with the choice of manufacturing and selling it, or shelving it. They chose to sell it. called it the Intel 8008, and the microcomputer had arrived.
Intel
for.

1-4

Despite the fact that the Intel 8008 was designed to perform simple data processing, the traditional job for computers, it created a market where none had existed: as a programmable logic device. Let us explore this concept.
In

any catalog of

logic

devices. The simplest trated as follows:

we

components, there are perhaps ten thousand different have already described; simple logic gates may be

logic
illus-

AND
Inputs

OR XOR
etc.

Output

Data inputs are transformed into data outputs according to the criteria of some transfer function. But consider a more interesting logic device, a 4-bit, two-input, buffer multiplexer:

Data Inputs

There are two interesting concepts in this buffer multiplexer. First, data are being handled in 4-bit units. Second, there are two non-data signals present: Select and Enable. Select determines which data input will become the data output. Enable determines when it will become an output.
If an LSI chip can contain thousands of gates worth of logic on it, how about condensing a catalog of logic onto a single, general purpose chip, as follows:

AND
OR XOR
Data
Inputs

ADD
SUB BUFFER
etc.

Data Outputs

F~T
Select signals choose

one

logic device

1-5

The general purpese chip

illustrated above has a good deal of unnecessary, duplicated logic on it. Any one of the ten thousand chips listed in a catalog may be synthesized out of a few, basic logic functions AND, OR, XOR, ADD, SUB plus a

few

buffers, selects

and enables:

BASIC LOGIC

FUNCTIONS
Select

and
Enable
Signals

^^E^

mm.
[
|
|

BUF A

BUF B

BUF

Three bidirectional
data paths

This basic logic device can synthesize any individual logic device, or any sequence of
individual logic devices.

This

is

the concept of the microcomputer.

ABOUT THIS BOOK

this book is to give you a thorough understanding of what microcomputers are and how they differ from other computer products. Since the book does not assume that you have had any prior contact with computers, basic concepts are covered in considerable detail; and from basic concepts we build the necessary components of a microcomputer system.

The purpose of

The book does concentrate on

and minicomputers.

highlighting the differences

between microcomputers
build logic

The book does Jiot discuss the various technologies which are used to

chips because, in the end, the nature of the technology is usually quite unimportant to a user. Your application may have some key parameters such as the amount of power that you can afford to consume or the execution speeds that you can tolerate; indeed the various technologies that are used influence power consumption, execution speed and other critical factors, but where these factors are critical, selecting the right microcomputer simply involves looking at product specifications. Understanding whether the product is fabricated using N-MOS technology or C-MOS technology does not make it significantly harder or easier to understand what a microcomputer is or how to use it.

HOW THIS BOOK HAS

BEEN PRINTED

Notice that text in this book has been printed in boldface type and lightface type. This has been done to help you skip those parts of the book that cover subject matter with which you are familiar. You can be sure that lightface type only expands on information presented in the previous boldface type. Therefore, only read boldface type until you reach a subject about which you want to know more, at which point start reading the
lightface type.

1-6

Chapter 2 SOME FUNDAMENTAL CONCEPTS

The reason there is no fundamental difference between a microcomputer and any other computer is because all computer products are based on the same fundamental computing concepts which in turn devolve to one fundamental logical concept

that of the binary digit.

binary digit

is

number

that can

have one of two values:

or

1.

bi-

BINARY
DIGIT

nary digit can have no other value.

What makes

the binary digit so useful

is

that

it

can be represented by any bistable device. Anyin

thing that can be "on" or "off", "high" or "low", can represent a zero

one

state

and a one

in

the other state. Figure 2-1 illustrates a bistable device.

And

that

is all

the physics you need to

know

in

order to understand microcomputers.

o
is

o
equivalent to
Digits Repre-

is

equivalent to

~z_T

Figure -2-1.

Symbolic Representation Of Binary

sented By

Bistable Device

NUMBER SYSTEMS
A computer
tunately,

no higher than one would not be a very useful machine. Forbinary digits can be used to represent numbers of any magnitude, just as a string of decimal digits can be used to represent numbers in excess of nine. Let us
that could count
of.

therefore consider what. numbers really consist

DECIMAL NUMBERS
When
each
a decimal
digit really represents?

number has more than one digit, have you ever considered what The two digits "11" really mean ten plus one:
11

= 1X10 +

Likewise, the

number 83

really

means

eight tens plus three:

83

= 8X10 +

The number 2347

really

means two
2

thousands, plus three hundreds, plus four tens, plus seven:

7

347 = 2X1000 + 3X100 + 4X10 +

The

There

is

nothing unique or special about decimal numbers.

fact that

man

has ten fingers and

ten toes almost certainly accounts for the universal use of base ten numbers, but any other

num-

ber base would serve just as well.

BINARY NUMBERS
Because decimal digits cease to be unique with the digit 9. ten must be represented by "10". which means 1 times the number base (in this case, ten) plus 0. Usinq the letter "B" to represent
the

number

base,

we

have:

10

= 1XB +
2-1

Now
in

in

the binary numbering system, "B" does not represent ten;

it

represents two.- Therefore,

the binary system, 10

decimal

2:

10
Similarly, in

= 1X2

+0
1

the binary system,

1 1

represents decimal three:

11

= 1X2 +

Stated generally, suppose any numbering system's digits may be represented symbolically by dj d;, d|<, etc. If B represents the number base, then any number can be explained by this equation:
d^dkd,
Consider a decimal example
2
(B

= d,XB 3 + d,XB 2 +

d k XB

= 10)

and binary example (B=2).

17

4=

2X10 3 + 1X10 2 + 7X10 +

d k xB

d,djd k d]

= d,xB 3 + d,xB 2 +

+
1

d,

10 11 = 1X2 3 + 0X2 2 + 1x2 +

CONVERTING NUMBERS FROM ONE BASE TO ANOTHER

easy to convert numbers from one number base to another number base. Since we have only discussed decimal and binary numbers so far, consider the conversion of numbers between these two systems.
It is

BINARY

TO DECIMAL CONVERSION

10

= 1X2 3 + 0X2 2 + 1X2 =

8 and 2
2

+1

4,

therefore:

= 1X8 + 0X4 + = 8+0 + 2 + = (decimal)

1

1X2+1
1

Continuous division by 2, keeping track of the remainders, provides a simple method of converting a decimal number to its binary equivalent;
for

example, to convert decimal

1 1

to

its

binary

DECIMAL TO BINARY CONVERSION

equivalent, proceed as follows:

Quotient
5

Remainder
1

t
Thus
11 10

<

101

The

subscripts 10

and 2

identify the

numbers as base 10 and base

2,

respectively.

2-2

The general equation to convert a

decimal equivalent

may be

fractional binary written as follows:

1 )

number to

its

CONVERTING FRACTIONS
(d,

d,d,d k di ...etc.

=(d,xB-

+(d,xB- 2 +
)
.

(d k

XB~ 3 +
)

XE

etc.

where
the

dj

d,j,

d|<.

etc.,

represents numeric digits and B represents

number
0.

base.
2

For example, to convert

101

to

its

decimal equivalent, proceed as follows:

0.1011

= (1X2-') + (OX2- 2 + (1X2

)

-3
)

+ (1X2- 4
"3

where 2~' =

i
-L

0.5

~2

0.25

0.125

2~ 4 =
Thus,

0.0625

0.101

= =

0.5i

0.125,0

0.0625 10

0.6875,0

To convert a
0.6875 10 to
its

fractional decimal

number to its binary equivalent (e.g., to convert binary equivalent), use the following approximation method:
0.6875

0.3750

0.7500

0.5000

(p.3750

. 7500

(p. 5000

0000

T
1

Unfortunately, binary-decimal fractional conversions are not always exact; just as a 2 fraction such as h has no exact decimal representation, so a decimal fraction that is not the sum
of 2
_
"

terms

will

only approximate a binary fraction.

;

Consider 0.42357 10 the binary representation of

this

number may be created as

0.38856

follows:

0.42357

0.84714

0.69428

0.77712

r
The answer
is

2
"

69428

Q). 38856

77712

0.55424

1
1

T
1 1

0.01 101 ....

As

a check,

let

us convert back

0.01101

= 0X2 -1 + 1X2 -2 + 1X2~ 3 + 0X2 = + 0.03125 + 0.25 + 0.125 + = 0.40625,o 0.40625. which equals 0.01732;
In

-4

+ 1X2-

The

difference

is

0.42357

this difference

is

caused by the

neglected remainder, 0.55424.

the smallest

other words, the neglected remainder (0.55424) multiplied by

total error:

computed term (0.03125) gives the

0.55424 X 0.03125

0.01732

2-3

OTHER NUMBER SYSTEMS

Because binary numbers tepd to be very long, binary digits are often grouped into sets of three or four. The numbers are now base 8 (octal) or base 16 (hexadecimal), as

shown

in

Table 2-1. Consider the

binary number:

110111101100
By grouping the binary
to octal format:
digits into sets of three, the

number

is

converted

OCTAL

NUMBERS
110 111
6
7

101

100 4

= 6754 8
"

Base 8

(octal)

includes only the

digits:

0.

1.

2,

3, 4,

5. 6.

7.

Decimal 8

is

the

same

as octal 10.
digits into sets of four,

By grouping the binary hexadecimal base:

the

number

is

converted to

HEXADECIMAL

NUMBERS
1101

DEC
digits:

1110 1100

= DEC 16

Base 16 (hexadecimal) includes the

0,
1,

2,

3,

4, 5, 6, 7, 8, 9.

A, B, C, D,

E, F.

Decimal 16

is

the

same

as hexadecimal 10.

Table 2-1.

Number Systems

HEXADECIMAL
1

DECIMAL
1

OCTAL
1

BINARY
0000
0001

2 3

2 3

0010
0011

4
5

4
5 6
7

4
5 6
7

0100
0101

6
7

0110
0111 1000
1001

8 9

8
9

10
11

A
B

10
11

12

1010
1011

13 14 15 16
17

D
E F

12 13 14 15

1100
1101

1110
1111

2-4

BINARY ARITHMETIC
Binary numbers can be operated on in the same way as decimal numbers; in fact, binary arithmetic is much easier than decimal arithmetic. Consider binary addition, subtraction, multiplication and division.

BINARY ADDITION
The
possible combinations

when adding two

binary digits are:

Augend

+ + + + +
as
in

Addend
o1

Result

Carry

=
is

The

carry,

decimal addition,
is

added

to the next higher binary position. For example:

This Decimal addition

equivalent to this Binary addition.

carry
3

+6
9

+ 110
1001

This Decimal addition

is

equivalent to this Binary addition.

11 -*

carry

1*-

-carry

"208

11010000

+92
300

+1011100
100101100

BINARY SUBTRACTION
Microcomputers cannot subtract binary digits; they can only add. Fortunately that no problem, since subtraction can be converted into addition.
Subtracting a decimal number complement of the number.
is is

equivalent to adding the tens

TENS

COMPLEMENT
is

The tens complement

of a

number

generated by subtracting the number from

via

10.

The final carry, however, must be ignored when performing decimal subtraction ment addition.
Consider the decimal subtraction.

tens comple-

The tens complement

performed
via the

of 2

is

(10-2), which equals

8.

The decimal

subtraction can therefore be

tens complement addition:

ignore

final carry

2-5

Performing decimal subtraction

evaluate than

via

tens complement addition

is silly,

since

10-2
is

is

no simpler to
lot

9-2 was The binary equivalent of a tens complement

twos complea
of sense;

ment. Performing binary subtraction via twos complement addition makes moreover, twos complement logic is well suited to computers.
The twos complement of a binary number is derived by replacing digits with digits, and digits with digits, then adding 1. The first step generates a "ones complement" of a binary number. For example, the ones complement of 10110111Q1 is 0100100010.
1 1

ONES

COMPLEMENT

Here are some other examples:

Binary number Ones complement Binary number Ones complement

0101 1010 1010100 0101011

The twos" complement of a binary number is formed by adding 1 to the ones complement of that number. For example, the ones
complement
of

TWOS
COMPLEMENT

0100

is

101

1:

Original

number:

0100
1011

Ones complement:

+
Twos complement:

1100
of the

Now

look at how binary subtraction can be performed by adding the twos complement SUBTRAHEND to the MINUEND. First consider the following binary subtraction.

MINUEND SUBTRAHEND
DIFFERENCE

10001

-01011

00110
of the to

The same operation can be performed by forming the twos complement adding to the minuend. The final carry must be discarded, just as had ment subtraction:
it it

subtrahend and
for tens

be

comple-

MINUEND

TWOS COMPLEMENT OF SUBTRAHEND

discard
final carry

Thus the difference

is

001

10.

Consider another example:

11001

-101

MINUEND SUBTRAHEND

11001

MINUEND

+11011

TWOS COMPLEMENT OF SUBTRAHEND

= 10100
discard

lll0100

"J
2-9

final carry

When

a larger number is subtracted from a smaller number, there is no carry to be discarded. Consider the decimal version of this case. becomes 2 + (10 - 9), or 2 + 1. The answer. +3, is the tens complement of the correct negative result, which is -(10 - 3)

-7. Here

is

a binary

example of the same

thing:

2-6

101

-11011

MINUEND SUBTRAHEND
DIFFERENCE

101

MINUEND

400101

-10110

01010

TWOS COMPLEMENT OF SUBTRAHEND NEGATIVE ANSWER IN TWOS COMPLEMENT FORM.

larger binary

tive,

but

it

is in

101

10).

number has been subtracted from a smaller one. The answer on the right is negatwos complement form; taking the twos complement of 01010 (twos complement and assigning a minus sign, provides the same answer as on t he left, -101 10.

When

performing twos complement subtraction, the final carry provides the sign of the answer. If the final carry is 1, the answer is positive. (The minuend is greater than the subtrahend.) If the final carry is 0, the answer is negative (the minuend is smaller than the subtrahend), and is in its twos complement, positive form.

SIGN OF

ANSWER

IN

SUBTRACTION

BINARY MULTIPLICATION
Binary multiplication is actually easier than decimal multiplication, since each partial product, in binary, is either zero (multiplication by 0) or exactly the multiplicand
(multiplication

by

).

For example:
is

This Decimal multiplication

equivalent to this Binary multiplication:

+1001
X1Q1
1001

X5
45

0000
1001

101101

BINARY DIVISION
Binary division can be performed using the
example:

same steps

as decimal division. Here

is

an

1011-*Divisor

-Quotient -Dividend

-*-101

110111-*
101

0011

0000
111 101
Intermediate
multiplications

0101 0101

and subtractions

BOOLEAN ALGEBRA

AND COMPUTER LOGIC

Boolean algebra
important in microcomputer applications because it provides the basis for decision making, condition testing and numerous logical operations.
is

and 1 to define logical decisions. Three Boolean algebra uses the binary digits Boolean operators, OR, AND, and Exclusive OR (XOR) combine two binary digits to produce a single digit result. A fourth Boolean operator, NOT. complements a binary
digit.

2-7

"OR" OPERATION
The OR operation
If
I

is

defined, for
J. or

two

integers
1,

and

J,

by the statement:
is 1.

OR

both, equal

then the result

Otherwise

the result

is zero.

plus sign

is

used to represent "OR". While the Boolean symbol

for

OR

is

also

used to repre-

sent arithmetic addition, the

are not identical.

two operators should not be confused; they

are very similar, but they

Two

binary digits are

ORed

as follows:

0+0=0
+ 1=1 1+0 =
=
1) is
1

1+1=1
the only

Notice that the

last

OR

operation

( 1

OR

operation

where the

result differs

from binary addition.

Logic functions are

lists

commonly defined using a Truth Table which

is

TRUTH
TABLES

the output signals associated with allowed input signal combinations.

The OR Gate Truth Table

given below:

TRUTH TABLE FOR

INPUTS
1

AIM

OR GATE OUTPUT =

+J
1

"AND" OPERATION
The

AND

operation
If
I

may be

defined for two integers

1,

and

J by the statement:

AND J
is

are both

then the result

is 1.

Otherwise the

result

0.

The dot

and

binations of

symbol are both used to represent the and 1 for the AND operation are:

AND operation. The four possible

cofff

0-0=0 0-1=0
1

1-1=1
The

AND

Gate Truth Table

is

given" below:

TRUTH TABLE FOR AN AND GATE

INPUTS
1

OUTPUT =
J
1

2-8

"EXCLUSIVE OR" OPERATION

The EXCLUSIVE OR
differentiates between input binary digits which are identical and input binary digits which are different. The output is when the inputs are different symbol is used to represent the XOR operaor and when the inputs are the same. The
1

tion.

The

four possible combinations of

and

for the

XOR

operation are:

= = = =

The XOR Truth Table

is

given below:

TRUTH TABLE FOR TWO-INPUT EXCLUSIVE OR GATE

INPUTS

OUTPUT =
B

AB
1

"NOT" OPERATION
"NOT" complements any
binary digit or group of digits.

NOT NOT
Because of the nature of microcomputer
tion: instead of
logic.

= =

NOT

is

not a particularly significant logical opera-

using the

NOT

operation, the microcomputer's ability to generate a

ones comple-

ment

is

employed.

Combining
results of

AND with NOT generates NAND. Combining OR with NOT NAND and NOR are the NOT of AND and OR. respectively.
digit to

generates NOR. The

bar

is

placed over a

represent NOT. Therefore,

T =

COMBINING LOGICAL OPERATIONS

A
microcomputer need not have
all

clusive OR;

some

operators
by

may be combined
B; this
:

three of the Boolean operators AND, OR and Exto generate others, as follows:

A + B

is

reproduced

is

illustrated as follows:

\a-% &

A
1

B
1

A-:^.B.
=

W&M W$M WM&

|:|:|:|:ji!:j:|:i:|

"=~

-'

1
=

-rJf>-"=

W$
'^^\

M^i
2-9

The Exclusive OR may be generated as

follows:

A
This
is

(A

B)

(A

B)

illustrated

as follows:
:#:':@:B:;
ixxiQix;:;:

A
1

B
1

'

'

-<A

'-:'

}'

A$.

>'
:

.B).

10
1
1 1

1:

10

.'&'
1

'.V:

11
= A + = A

Q:

DE MORGAN'S THEOREM
Boolean operations can be combined to produce any desired output from a set of known inputs. De Morgan's theorem is a valuable aid in designing such combinations. The theorem can be written in either of these ways:

A A +

B B

B B
others, since:

Therefore a microcomputer only needs one Boolean operator. OR, to generate

all.

A
generates

= A +

AND

out of

OR and NOT.

Similarly,

A
generates

(A

B)

(A

B)

XQR

out of

OR and NOT.

2-10

Chapter 3 THE MAKINGS OF A MICROCOMPUTER

Given that Binary digiTs (referred to as BITs) are capable of being BITS manipulated to perform any of the operations described in Chapter 2, how are these basic operations going to be harnessed in order to generate a microcomputer? First let us examine how information is stored as binary data.

MEMORY ORGANIZATION
Binary data are stored
ble elements.
of

in memories. Every computer memory consists of an array of bistaMinicomputers used to use and still- frequently use "core" memories, which consist minute metal "donuts" which can hold a clockwise or counterclockwise magnetic charge:

*- DIRECTION

OF CURRENT

Microcomputers use semiconductor memories, which may be conducting or not conducting:

consist of an array of

gates

which

etc.

etc.

Core memories hold their magnetic charge even when disconNON VOLATILE electric power: you can pull a core memory card out of a MEMORY computer, plug into another similar computer, and the memory data should still be intact Core memories are therefore said to be "non volatile"
nected from
it

Semiconductor memories loose all stored data the moment you shut off their power source; therefore they are said to be
"volatile".

VOLATILE

MEMORY

3-1

"

The type

of

memory used

with a microcomputer

is

unimportant.

It

is

only necessary that the

memory

consist of a

number

of bistable, individually addressable elements,

each representing a

single binary digit:

10110011101011100100001011

There are two absolutely necessary properties which any memory must have:
1)

The
It

location

where every binary

digit is stored

must be uniquely addressable.

2)

must be possible to read the state

of every binary digit.

I I

With some memories it is not possible to change the state of ROM ~~ binary digits in the memory. If the state of binary digits can be read, but not changed, then the memory is called a Read-Only Memory, or ROM. Of course, by its very nature, any ROM memory is non volatile.
If the state of binary digits within a memory can be changed, RAM l l as well as being read, then the memory is called a Read-Write memory. Read-write memories are commonly referred to as Random-Access

Memories (RAM).
There
digits
is

no good reason

why

a read-write

memory, as against
is

a read-only

memory, should be
if

referred to as a

randomly accessible memory; memory within the memory can be accessed directly:

randomly accessible

individual binary

If

binary digits within a

memory were
digits:

not randomly accessible, they would be sequentially ac-

cessible,

which means
all

that the tenth binary digit, for example, could only

be accessed by

first

passing over

preceding

mon

Read-only memories and read-write memories are both randomly accessible. Nevertheless, comterminology refers to read-only memories as ROMs and read-write memories as RAMs.
3-2

MEMORY WORDS
combined to represent numbers in excess of 1. just as numbers in excess of 9. Table 2-1 gave some binary representations of small numbers. The primary level at which binary digits are grouped within any computer is one of the most imWORD porta nt features of the computer and is referred to as the comSIZE puter's word size. For example, an "8-bit" computer acquires the "8bit" label because binary data within the computer will be accessed and processed in eight binary
Chapter 2 explained
decimal
digits are

how

binary digits are

combined

to represent

digit units.

A memory

organized into 8-bit units might be visualized as follows:

MEMORY

Each dot
word.

in

the above illustration represents a single binary

digit.

Each box represents an

8-bit

By common convention the

order
turers

bits of a word are numbered from right (0 for the low to left (7 for the high order bit) as illustrated above. Some computer manufacreverse the convention, numbering from left to right.
bit)

Table 3-1.

Computer Word

Sizes

Word
Size
(Bits)

Microcomputers

Minicomputers

Large Computers

4
6

Many
None

None

None None

A few
obsolete

models
8
12 16

Most common

A few

None None

few

few

A few
None

Most common

A few A few A few

Most common

18

A few A few

24 32 64

None None None

few

None

Common
largest

for

computers

3-3


A large number of different word

sizes have been used by microcomputer, minicomputer and mainframe (large computer) manufacturers. Table 3-1 lists the more common word sizes and identifies those word sizes which are used by microcomputers, minicomputers and large computers.
8-bit

Most microcomputers use an

very

much

oriented toward digital

word. There are a number of 4-bit microcomputers which are logic replacement. There are also a number of 16-bit
for their traditional markets.

microcomputers, which tend to compete with minicomputers

THE BYTE
An 8-bit data unit
puter industry;
puter, for
it

is called a byte. The byte is the most universally used data unit in the comused even by computers that do not have an 8-bit data word. A 16-bit comexample, will often have memory words interpreted as two bytes:
is

16-bit
.

word

/^_
15
1

14
1

13
1

12
1

11

10

0-

-Bit

number

v
High order
byte

-A.

Y
Low
order
byte

When
same
If

microcomputer has an

8-bit

word

size,

we

can
they

refer

in-

BYTES AND

terchangeably to
thing.

"memory

bytes" and

"memory words";

mean

the

WORDS

a microcomputer's

mean

the

refers to

word size is not eight bits, then a memory word and a memory byte do not same thing; a memory byte refers to an 8-bit memory unit, whereas a memory word a memory unit of the microcomputer's word size.

Many 4-bit microcomputers refer to the 4-bit unit as a "nibble". Thus each word of 4-bit memory is a "nibble", and two 4-bit
memory words
constitute a byte.

{NIBBL ES

MEMORY ADDRESSES
Even though every binary
digit

within a

memory must be

uniquely addressable, binary digits are

not very useful as single entities, therefore

accessed out of memory is memory is accessed, eight binary

the smallest unit of information that is usually a word. For example, when using an 8-bit memory, each time
digits are referenced.

Each word of memory has a unique memory address. Words within memory have sequential memory addresses, with the first word in the memory having an address of 0, and the last word in the memory having the highest address of any word in that memory. The actual
value of this highest address
will

depend on the

size of the

memory.
)

Thus the address of a word is its location in memory; for example, the words of a 1000 (4096 16 10 word memory would be addressed and numbered as follows (in hexadecimal notation):

OFFE

OFFD

OFFA

0FF9

09C2
J

09C1
J

09C0

09BF

...

3-4

some subtle differences between the way minicomputer and microcomputer programmers use memories. Some of these differences are introduced now, while others are described later, since they will not be meaningful until you understand how microcomputers are used.
Conceptually, there are

To the minicomputer programmer, memory

of individually addressable

is

simply a sequence
the size of the

MINI-

RAM words, with addresses beginning at

in

COMPUTER

and ending
puter's

at

some
will

large
It

number which depends on

only
rare

MEMORY
CONCEPTS
as data

minicomputer's memory.

is

cases that part of the minicom-

memory

be ROM. Certainly a minicomputer

programmer

never needs to worry about the physical implementation of memory. So long can be stored and retrieved on demand, where and how this happens is irrelevant.

The microcomputer programmer

will

memory

is

implemented, because
units.

there are

be very interested in how many applications where

will

MICRO-

COMPUTER

a microcomputer-based product, once developed,

be sold

in

tens of

MEMORY
CONCEPTS

thousands of
a

This being the case,

it

is

very important that the

num-

ber of discrete components within the microcomputer system be kept to minimum, since every extra (and therefore unnecessary) component will be multiplied by tens of thousands thus increasing costs.

The microcomputer programmer has a further interest in memory organization because almost all microcomputer based products use ROM for some part of memory. The reason ROM is desirable

when

using microcomputers
in

modified, nothing stored

characteristic
in

safe. Since no binary digit within a ROM can be can be accidentally erased. This is a very desirable a product which may end up in obscure or inaccessible locations.
is is

that ROM ROM memory

The microcomputer user thinks of memory as semiconductor trates a 1024-bit memory device in a dual in-line package.

chips. Figure 3-1

illus-

3 8 5

7 5 2

Figure 3-1.

1024-bit

Memory

Device.

ROM memory is implemented in single chips. For example, a microcomputer may have 1024 8-bit words of ROM memory on a single chip. This single chip will have a capacity of 8192 binary digits, divided into (and accessed as) 1024 8-bit units. A microcomputer
Usually

programmer

will

be interested

in

how memory

is

memory space
to the system.

provided by a single

ROM

device requires an additional

implemented, because moving out of the ROM device to be added

3-5

Read-write
write
eight

memory

requires

more

logic

than read-only memory, since the individual

bits of a read-write

memory is RAM chips may

of the word:

memory can be changed as well as being read. Therefore, readcommonly implemented on more than one chip. In a very simple case,
implement
8-bit read-write

memory

words, with each chip contributing

one

bit

if
One Memory Module

a single
8-bit

word

We

will refer to this set of

eight chips as a

memory module.

MEMORY MODULE

Small microcomputer systems

memories. For

may use fewer memory chips to implement small read-write example, two RAM chips may each contribute four bits of an 8-bit word:

a single 8-bit

word

One Memory Module

3-6

Now

there are

two memory chips

is

in

the

memory module.
with entire words implemented on a single chip:

RAM memory

also available like

ROM,

RAM

single 8-bit

word

One Memory Module

RAM
RAM

memories cost increases, in terms of cents-per-bit, when fewer chips are used to implement a single memory word. Thus implementing an 8-bit read-write memory word
using eight

RAM

chips generates the cheapest

chip generates the most expensive

memory. Having the memory.

16,384-bit
in

entire 8-bit

word on one

Currently 4096-bit

RAM

chips are

common, and

RAM

chips

are almost here. 65,536-bit

quantities by late 1977

RAM

chips should be available

commercial

RAM CHIP MEMORY SIZE

DYNAMIC

-for between $5 and S10

per chip.

There are two types of RAM memory: dynamic RAM and Static RAM. Dynamic RAM, which is cheaper, can only hold data for a

RAM

few milliseconds; therefore dynamic RAM must constantly be refreshed STATIC by having the contents of memory words rewritten. Dynamic RAM refresh RAM is handled automatically by some microcomputer systems; other microcomputer systems require external refresh logic when you use dynamic RAM. Static
costs more, but once data have been written into
it,

RAM
is

the data

will

stay there as long as

power

being input.

Once

again, as a

microcomputer

user,

you

will

be very interested

in

memory addresses have been

dresses translate into

assigned to read-write memory. This

is

knowing exactly which because memory ad-

RAM

chips.

An
is

extra byte of data

memory may

require eight

new RAM
chips

chips, which, multiplied by 10,000,

expensive.
will

Because, as a microcomputer user, you

relate to

be constantly concerned with

will

how memory

memory

addresses,

memory addresses
larger

take on a significance that differs markedly

from the world of mini and

computers.

Specifically,

every

memory address may be

bits.

visualized as consisting of chip select bits and

word address

The chip

select bits select

one

or

more chips

that constitute a

memory module.

The word address

bits identify

one memory word within the selected memory module.

3-7

Suppose

8-bit

bits will select

memory words are implemented on eight separate memory chips. The chip select an eight-chip memory module. The word address bits will identify one memory

word, as follows:

16-bit

memory address

The number of word address bits required by a memory module will depend on chip size. For example, a chip contains part or all of
if

SIZE OF

MEMORY
ADDRESS

256 to memory words, then the word address

digits:

will

consist of eight binary

Smallest word address

Largest

= 00000000 = 00 16 = 00 10

word address
part or
all

1 1

FF, 6

= 255,
will

iarger

memory

chip

may have

of

1024 10 memory words: then the word address

consist of ten binary digits:

Smallest
Largest

word address = 0000000000 = 000 16 = 000 10

word address

1 1 1

111.1111

= 3FF 16 =

1023,

Notice that ten binary digits create three hexadecimal digits as follows:

these two

10 binary digits

binary digits
are implied

TLr
Hex

00 bb
digit

bbbbbbbb
Hex
digit

Hex
digit

3-8

The number

of chip select bits will be a function of the microSIZE OF computer's architecture; but concatenating the number of chip CHIP SELECT select bits with the number of word address bits generates the microcomputer's maximum memory capacity. For example, the microcomputer can address 65,536 10 (FFFF 16 memory words, 16 binary digits will be required to express the largest
if
)

allowed

memory

address:

1111111111111111
F

T"
digits,

Now

if

1024-word memory chips are used, the word address consumes ten binary
in

which

leaves six binary digits for the chip, select;

memory modules,

with 1024 10 words per

maximum memory will consist of 64 module, and the 16-bit memory address must be inother words,

terpreted as follows:

16 binary digit

memory
*

address
^

ssssssbbbbbbbbbb
6 binary
, . ,

digit

chip
'

cpippt
,

10 binary digit word M ' address, holds values

,

selects

one

from0to3FF lb

of40 16
(=64 10
)

Mn UUZdl

1fi

memory
modules

The important thing to remember

of

is that the microcomputer sets the TOTAL number binary digits; how they are split between chip select and word address depends on the type of memory chips used it is entirely up to the logic designer.

memory address

bensik

again at

how

a total
is

word address
01 10101
is
1

is

created
l6

in

a real case.

If,

as illustrated
is

earlier,

the

word

address within the chip

binary digit

10 2 (1AE

)and the chip select

0001

(07 16

),

then a 16

word address

created as follows

chip select

word address
\

1
Total

A
t
1
1

A
>
1 1 1
1

word address =

There

is

no reason

at zero

For example, a

ing 8 -bit

four bits

memory addresses need to be continuous, or even need to start microcomputer system may include one ROM chip implementwords and a RAM module made up of two RAM chips, each implementing of an 8 -bit word.
available

why

3-9

If the ROM chip has a chip select of 000001 2 and a capacity of 1024 10 then allowed ROM memory addresses will be 0400 16 through 07FF^:

memory bytes,

chip select
\
First
1

word address
A
2

ROM

address

=000001000000000
4
0,fi

chip select

word address
K
^

A
t
t

n 2

Last

ROM

address

=0000011111111111

Observe that 1024 10 bytes of memory

will
.

now

have addresses

1024
If

through 2047 10 or 0400 16 through 07FF 16

We

refer to this range of

ADDRESS SPACE
the ad-

memory addresses
the two

as the

memory module's address

space.

RAM

module has a select of 0001 1 2 and each chip holds 256 x 4 bits, then RAM chips constitute a memory module, and provide 8-bit RAM memory words with
.

dresses 1800 16 through' 18FF 16

chip select

word address

First

RAM

address

=0001 10000000000
1

0,r

chip select
t n

word address

r
1

^
2

Last

RAM

address

=000110001111111

Addresses

in

the range 1800 16 through 18FF 16 constitute the

RAM

module's ad-

dress space.

INTERPRETING THE CONTENTS OF MEMORY WORDS A memory word consists of a number of binary digits; therefore, binary digits are the
only form in which information can be stored
in

word

of

memory.

An

contain 256 (2 8 ) different patterns of 0's and 1's. The pattern of zeros and ones within a memory word may be interpreted in any one of the following ways:
8-bit
1
)

memory word can

Pure binary numeric data that stand alone.

Binary numeric data that must be interpreted as one part of a multiword data
unit.

2/

3-10

3)

data code; that interpretations.

is,

a bit pattern subject to

some

arbitrary predefined set of

4)

An

instruction code; that is, a bit pattern which is to be transmitted to the microcomputer. The microcomputer will decode the bit pattern and interpret it as an identification of those operations which the microcomputer logic must immediately perform.
is

This

the only important concept to understand at this time:

Upon examining the contents of any word of memory, it is impossible to determine whether the memory word contains numeric data, a code, or an instruction.
Chapter 4 you will learn how a microcomputer memory word may be interpreted in a number of interpretation of a memory word.
In

takes care of the fact that the contents of any

different ways. But
first

we

will

describe each

STAND ALONE, PURE BINARY DATA

Consider
It

first

pure binary data, subject to no special interpretations.

is

important to understand that you can represent pure binary data, on paper, as a binary

num-

number; the choice is purely a question of reader convenience and has no impact whatsoever on the data word. Here is an example for an 8-bit data word:
ber,

an

octal

number

or a hexadecimal

E-^
1
1 1

Hexadecimal

10
1 1

0-< Binary
-<
Octal

01001 110 2
Here
is

116 8

4E 16

an example

for a 16-bit data

word:

B-<

Hexadecimal

110110111000101

1-* Binary
Octal

15
The choice
data interpretation;
it

6
2

3-<

1101 1011 1000101

155613 8

= DB8B 16
memory word's contents is not same thing on a piece of paper.

of binary, octal or hexadecimal representation for a

is

merely an alternative

way

of writing the

3-11

INTERPRETED BINARY DATA

The contents
of a memory word, interpreted as pure binary data, may stand alone, or may be part of a larger numeric unit. For example, an 8-bit memory word standing alone can to 255 > A 16-bit memory represent numeric values ranging from
1(

word, on the other hand, can represent numeric values ranging from

to

MULTIWORD
BINARY

65,535 10 There

is

no reason

why 8-bit memory words

the contents of each 8-bit

be interpreted
will

in pairs.

Now

should not memory word

digit

DATA

be interpreted as the lower-half or the upper-half of a 16 binary

One

16-bit

word

10
One
Upper

10
8-bit

1111
v~

word.

One

8-bit

word

half of a

Lower

half of a

16-binary digit

16-binary digit

number.

number.

There is, in fact, no limit to the number of memory words that may be concatenated to generate very large numbers. Here is an example of a 48-bit number:

One
(

48-bit

word
"\

100111011101111010100110001110110101101100101101
byte 5

byte 4

byte 3

byte 2

byte

byte

Suppose

above. Normally, these

memory words are required to represent a single numeric unit, as illustrated six memory words would be contiguous; that is. they would have memory addresses adjacent to each other. However, there is nothing in the logic of a microcomputer that demands the many bytes of a multibyte number be contiguous; contiguous multibyte numbers are easier to process; that makes contiguous organizasix 8-bit

tion desirable.

What about multibyte arithmetic? Numbers that occupy many memory words can be added, subtracted, multiplied or divided
using the rules described
2 about the
if

in Chapter 2. Nothing was said in Chapter number of binary digits associated with any number. Thus a 16-bit number is stored in two adjacent 8-bit memory words, binary addition rules described in Chapter 2 would still be used, but the 16-bit numbers would have to be added in two steps as

MULTIBYTE BINARY ADDITION

follows:

word

word
10000110 11010100

10011101
carries

from word

and word

+00101010
1

=11001000
step 2

01011010
step
1

3-12

The

carry,

if

any. from each step

is

added

to the
to

low order

digit of
in

the next step.

The logical extension of the above example words is self-evident. Here, for example, is words, would be added in four steps:

numbers stored

three, four or

more memory

how two numbers, each occupying four 8-bit

2

word 3 10110100 01111010 00101111

step 4

word

word

word
11011010 00111001

+ =

110
00111111
step 3

10000101 10111010

01101011 01000010
1

10101110
step 2

00010011
step
1

There

is

a catch to subtracting multibyte

numbers. Recall from Chapter 2

MULTIBYTE

twos complement of the BINARY subtrahend and adding it to the minuend. Consider two 16-bit numbers SUBTRACTION stored in 16-bit memory words. The logic associated with subtracting one 16-bit number from another is very straightforward and may be illustrated as
that binary data are subtracted by taking the

follows:

23A6 16 - 124A 16 = 115C 16 23A6 16 =

0010001110100110 1110110110110101
j
1

Twos complement

of

124A 16 =

Answer =

0001000101011100

Now consider the same subtraction where

bit

the numbers are stored

in

two adjacent

8-

memory words.

The subtraction may be

directly

reproduced as follows:

word
23 16

word
10100110 10110101
1

ones complement

of 12

16

=00100011 = 11101101
00010001

= A6 16
twos complement
of

4A 16

01011100
5

11
step 2

step .1

Notice that only the low order byte of the number is twos complemented. The high order byte is ones complemented. While this may seem confusing at first, it really is not. If you visualise a multibyte number as a single numeric unit, then it is self-evident that when the twos complement of the multibyte number is generated, will be added to the low order byte of the multibyte
1

number

only:

Twos complement

of

124A 16 = 1110110110110101
1

1110110110110110

Twos complement
Ones complement

of of
1

4A 16
"

16

^i

i^

11101101

10110101
1

Twos complement

of

124A 16

11101101

10110110

3-13

very useful

numbers would not be negative numbers? Here, for the first time, we get into the question of interpreting binary coded data. A very effective industry convention interprets the high order bit of a number as a sign bit. If this bit is 1 the number is negative.
microcomputer
that could only process positive

What about

SIGNED BINARY

NUMBERS
If

this bit

is 0,

the

number

is

positive:

Obbbbbbb

represents a positive. 7 -bit

a negative. 7 -bit

number
number

Ibbbbbbb represents

Table 3-2 gives the interpretations for 8 -bit signed binary data. Observe that negative numbers
are

coded as the twos complement

of their positive counterparts.

Here are some examples:

+02, 6 = 00000010

-02,

11111101
1

110

+6A,

01101010

-6A,

10010101
1

10010110

When

eight binary digits are being interpreted as a signed number, the range of
1
.

numbers

is

from

-128,0 1 + 27 10 When sixteen binary digits are bers must fall in the range -32768, to +32767.
.

interpreted as a signed binary, number,

num-

Table 3-2.

S gned Binary Numeric Interpretations

EQUIVALENT

BINARY

DECIMAL

HEXADECIMAL
80
81

10000000
10000001

-128
-127

10000010
10000011

-126
-125

82

83

11111110
11111111

-2
-1

FE
FF

00000000
00000001
1

00000010
00000011

2 3

2 3

01111101

01111110
01111111

+ 125 + 126 + 127

7D
7E
7F

3-14

to represent signed numbers is that it calls for no arithmetic operations. Providing an arithmetic operation does not generate an answer which is too large to fit in the available space, you can ignore the sign of a number until you wish to interpret an answer; at that time, examining the high order bit of the answer indicates whether it is positive or negative. If the high order bit of the answer is 1, then the answer is negative and by taking the twos complement of the answer, the pure binary, positive representation of the answer is created. Here are some examples:
special logic

The beauty

of using this

scheme

when performing

63, 6

-3A 16
=29 16

-01100011 >-1 1000101

DO 10 1001

ones complement

of

3A,

A
2

Answer = +
This

29, 6

indicates a positive result

3A 16
63 16
=29 16
This
1

00111010 10011100
1

ones complement

of

63 16

indicates a negative result.

1010111

Take the twos complement:

00101000
1

00101001

Answer = 29 ie

Now

consrder the above example, rewritten as represented by the twos complement of + 63 16

(3A.,
.

-63 16 )=( 29 16

).

( 63 16

will

be

63 16 =01100011 ones complement

of

63, 6 -63 16

= 10011100 = 10011101

Therefore:

3A, 6

00111010
10011101

+(-63

1fi )

=(-29, 6
This
1

indicates a negative result

11010111

00

000
1_

Taking the twos complement of the answer generates the positive

representation

Observe that using twos complement notation to represent signed binary numbers, 3A, 6 63 16 and 3A 16 + ( 63 16 have identical binary representations, which is only to be expected of a via)

ble

scheme

for representing negative

numbers.

3-15

Multiword signed binary numbers generate no special problems so long as you understand that operations must be performed one word at a time. This is illustrated below for the simple case of 6bit, signed binary data, which generates the same results when handled as single 16-bit words or as two 8-bit words.
1

MULTIWORD
SIGNED BINARY

NUMBERS

one
sign
bit

16-bit

word
n

&
r.

01
8-bit

v~

100101 1000010 /v
srv

'

word

8-bit

word
is

Consider the subtraction of two

16-bit.

signed binary numbers., where each number

stored
in

in

two

8-bit words.

As

for

unsigned multiword addition, signed multiword addition proceeds

two

steps, as follows:

word

word

1A2C 16 0810

0Q011010
11110111

00101100
1 1 1

1fi )

T0000

121C U

sign

bit

Observe that

0810 16

is

generated by taking the twos complement of 0810 16 as follows:

0810 16
ones complement

twos complement

= 0000100000010000 = 1111011111101111 = 11110111111 10000

digits. Four
1

It is

possible to code decimal

numbers using binary

to F 16
,

BINARY

binary digits can represent values from

or from

to

10

By

ig-

CODED

noring binary digit combinations above 9, decimal numbers can be coded, DECIMAL two digits per 8-bit memory word, or four digits per 16-bit memory word. Table 3-3 identifies the combinations of four binary digits that may be interpreted as decimal numbers. AA/hen binary digits are being used to represent decimal numbers, the result
is

called Binary-Coded"

Decimal (BCD) data.

since

Signed binary number rules cannot be applied to BCD data, BCD demands that binary data be interpreted in 4-bit units:

NEGATIVE

BCD DATA

nnnnnnnnnnnnnnnn
digit digit

digit
1

digit

Each
8-bit

4-bit digit can have one of the bit patterns shown under the BCD column of Table 3-3. An word uses the high order bit for all numbers in excess of 79 10 the high order bit is needed
.

If

to represent decimal digits 8 or 9, then

it

cannot be used to represent a

sign.

3-16

Table 3-3.

Binary Representation of Decimal Digits

BINARY

HEXADECIMAL

BCD

0000
0001
1 1

0010
0011

2 3

0100
0101

4
5 6
7

4
5

0110
0111
1000
1001

6
7

8
9

8 9
Illegal Illegal Illegal

1010
1011

A
B

1100
1101

D
E
F

Illegal Illegal
Illegal

1110
1111

The sign of signed BCD numbers is therefore represented using a special "control" word which must precede the first data word of a multiword BCD numbers There are no common rules for control word format, but here is a simple example and a complex
example'.
First

the simple example:

Decimal data
.

in

BCD form

ri
Now
the complex example:
Control

most

T
significant
digits

least significant
digits
for positive

Control word,

is is

0000
0001

for

number, negative number.

Decimal data

in

BCD form

Word,
TTTTm
sign

bit

= =

for
1

+
J

nn
A maximum
decimal point
of

for

Total data words 0000 means 1111 means 16

1

H
| |

assumed here

7 post-decimal

words allowed

Total post-decimal

A maximum

of 16 data words-allowed

data

words
7

000 means 1 1 1 means

3-17

data cannot be added and subtracted using straightforward binary addition and subtraction rules. Here are some examples of the errors that could result:

BCD

Decimal

BCD

Decimal

BCD

23

+47

= =

00100011 01000111

54

-26 =28

= =

01010100 11011010
00101110 *-~ y~
2
Illegal

=70

01101010
6
Illegal

Note that
In

101 1010

is

the twos

complement

of the binary representation of 26.

order to perform

carry out of

BCD arithmetic, special rules must be applied, and the each BCD digit must be recorded. Consider the addition:
97

BCD
ARITHMETIC

+68

= 165
It

is

insufficient to record the fact that there

was

a carry out of the high order digit addition.

Any
ex-

intermediate carry out of the low order digit addition must also be recorded. Here are

some

amples showing the status

of the carry (C)

and the intermediate

carry

(IC):

C
1

IC
1

C
i

IC
I
1

C
1
1

IC
I

C
I
1

IC
1
1

21

29

91

97

+32

+32
=61

+32

+68

=53
Conceptually,
1)

=123

= 165

BCD

addition

is

performed as follows:

Add

the

two numbers.
invalid digit, starting

2)

Serially

add 6 to each

with the low order

digit. (This

"jumps over" the

six

invalid bit

combinations to yield the correct

BCD
0101

representation.)

For example, 25!o + 19io

= 0010
0001
0011

1001

1110

add

6:

0000
0100

0110 0100
==

44

This
of a

method

is

rather
is

BCD number,

subtracts those sixes

1)

clumsy to computerize. The following process, as described for two digits more efficient: adds 6 to each digit, then based on the carry statuses, which were not heeded:
it

Using binary addition, add 66 16 to the

first

number (the augend).

2)

Add
this

the

second number

(the

addend)

to the

sum generated
digit.

in

step

The

carry generated

in

step reflects the true carry to the next higher

3-18

3)

Using binary addition, add a factor to the

sum from

step

2.

The

factor to

be added depends

on the carry

(C)

and intermediate carry

(IC)

stratuses as follows:

IC

Factor

9A, 6
1

A0 16
FA 16
oo 16

re are

some

addition examples:

23

29

92

87

+32 =55 Augend =

66 16
Step
1

+34 =63
00101001 01100110
10001111

+32

+79

= 124
10010010 01100110 11111000

= 166
10000111

00100011 01100110
10001001

01100110
11101101

sum = sum =
C/IC

Addend =
Step 2

00110010
10111011

00110100
11000011
1

00110010

01111001

00101010
1

01100110
1 1

=
10011010 10111011 01010101
5 5

= Step 2 sum = Answer =

Factor

10100000 11000011

11111010 00101010

00000000 01100110 01100110

6
1

01100011
6 3

00100100
2
1

=
(from Step 2)

=
is

BCD
1)

subtraction
the twos

performed for two digits of a

of the subtrahend (the
from).

BCD number
in this

via

these two steps:

minuend

Add
(the

complement
digit.

number being

subtracted) to the

number being subtracted

The

carry generated

step reflects the true carry to

the next higher

Recall that

when
is

subtrahend
2)

multiword numbers are subtracted, only the lowest order word twos complemented. Higher order words are ones complemented.
for

of the

Perform step 3 as described

BCD

addition.

Here are

some

subtraction examples:

75

71

25

21

-21

-28
+43
00101000 11011000 01110001
01001001
.1

-71

-78 -57
01111000 10001000 00100001
10101001

+54
Subtrahend

-46
01110001 10001111 00100101
10110100
1

Twos

= = Minuend = Step sum =

compl.
1

00100001 11011111 01110101

01010100
1 1

C/IC
Factor

=
=

00000000 01010100
01010100
5
1

11111010 01001001

10100000 10110100

10011010 10101001 01000011

4
3

Answer =

01000011
4
1

01010100
5

=
C
(after

AC)

3-19

When

performing

BCD

subtraction, a negative result

is

indicated by a final carry of

(as for binary

subtraction), but in

keeping with the decimal representation of numbers, the numeric value of the
tens

negative answer

is in

complement
is is

form, not

in

25

-71

appears as 54, which

100 -46. and the 100

twos complement form. Thus the answer final carry is 0. Similarly, the answer
final carry is 0.

to
to

21-78

appears as 43, which

57,

and the

CHARACTER CODES
A
of binary digits, or

computer would not be very useful if it required data to be entered as a sequence if answers were output in one of the uncoded or coded binary formats. It must be possible for a computer to handle text and other nonnumeric infor-

mation.
If

we

in

bear in mind that the combination of binary digits within any memory word can be re-used any number of ways, then all the binary codes which have been used to represent numeric

data, as described

so

far,

can

all

be re-used to represent

letters of the alphabet, digit characters,

or

any other special printed characters.

a

So long as

program correctly
arise.

interprets the binary digits of a

memory

word, then confusion and

ambiguities cannot

For example,

if

you as the programmer decide

to

use

memory words
it

with addresses

0A20 16
in

through

0A2A 16

to hold binary-coded decimal data, then

is

up

to you, the

programmer,
errors.

your

subsequent

logic, to

remember

that the binary data

as binary-coded decimal digits

Likewise,
if

in

these

memory words must be

will

interpreted

and any other interpretation

cause

memory words 12A4, 6 through 12A6 16

as binary-coded decimal words
is

be interpreted as character codes, then the

digit pattern

fact that character

terprets the contents of

rectly interpret the

memory words, errors contents of memory words, then program

which are to codes have exactly the same binary irrelevant, So long as program logic correctly incannot arise; and program logic does not corare reserved to hold binary data
if

logic

is in

error

and must be

cor-

rected. In

order to handle text, a complete and adequate set of necessary characters

in-

cludes:

26 lower case letters 26 upper case letters approximately 25 special characters 10 numeric digits

CHARACTER
SETS
(e.g.

(+/@!#,

etc.)

The above character set adds up to 87 characters. A six binary digit group allows 64 combinations of and 1 binary digits (2 6 which is insufficient to represent 87 characters. A seven binary digit group allows 128 possible arrangements of and binary digits, which is sufficient for our needs.
),

The 8-bit byte has been universally accepted as the data unit for representing character codes. The two most common character codes, listed in Appendix A, are known as the American Standard Code for Information Interchange (ASCII) and Extended Binary Coded Decimal Interchange Code (EBCDIC). ASCII is used by all minicomputer and microcomputer manufacturers.
Eight binary digits are used to represent characters

where seven

binary digits suffice. This being

is

the case, the eighth binary digit

referred to as a parity
in
bit;
it

is

frequently used to test for errors, and

1

is

set to

or to 0, so that the

number

of

bits

PARITY

the byte

is

either

always odd or always even.

3-20

If odd parity is selected, then the parity always odd. Here are some examples:

bit will

be set or reset so that the

total

number

of

bits

is

Parity Bit

10000000 00000001 11001011 11011111 01010100

Number Number Number Number Number

is

of of
of of of

bits bits bits bits

bits

= = = = =

5
7

If

even
1

parity

is

selected, then the parity bit

set or reset so that the total

num-

ber of

bits will

always be even. Here

are

some examples:

Parity Bit

00000000
10000001 01010101 10010101 11111111

Number Number Number Number Number

of of of

bits bits bits bits bits

of
of

= = = = =

4 4 8

The
no
1

parity bit

is

used

to

ensure that between the creation

If,

of a character byte

and reading
even

it

back,
of
is

bit

was erroneously changed.

is

for

example,

parity

is

odd, then

whenever an even number

Similarly,
if

bits

detected

in

a character byte, clearly the byte of bits are

must be

in error. in

parity

selected, then

whenever an odd number

detected

a character byte, the byte

must

be

in

error.

an example of how a message might be stored words using ASCII character codes with even parity: Here
is

in

sequence

of

contiguous

memory

blank

1100010111101110 01110100 01100101 01110010 00100000

few comments regarding

parity

and

error

codes would be useful

at this point.

the high order bit of a byte can be used as a parity bit only when the byte contents are being interpreted as character codes. the contents of the byte are being inClearly,
If

terpreted as any form of binary data (coded or uncoded), then the high order
specified as an integral part of the byte's data contents; therefore, this
parity
bit,

bit

has already been

bit

cannot be used as a

so coded and uncoded binary data cannot have parity checked.

elaborate schemes are used, not only to check that sequences of binary digits contain no errors, but further to detect what these errors are and to make appropriate corrections. These error correction codes have nothing in particular to do with

Many

minicomputer or microcomputer concepts; therefore, they are not discussed

book.

in this

Microcomputers that have word sizes other than eight bits still use the byte to represent character codes. A 16-bit microcomputer will pack two bytes into each memory word as
follows:

1
1 1 1

16-bit

memory word

>
1
1 1

V,

Y
High order
byte

J^.

Y
Low
order
byte

3-21

microcomputer that uses 12-bit words

will

store the character

code

in

the lower eight of the 12

bits

and

will

waste the higher four

bits

as follows:

12-bit

mem ory
i i i

word
A

r~
i i i i
i i

v_

V
unused
bits

-v

V
character

byte

4-bit

microcomputer creates a byte out of two contiguous memory words:

Word
r
1 1

Word

V
1

1
1

" 1
-

Character
byte

microcomputers may actually be better suited to BCD applications such as hand held calculators. These applications treat 4-bit data units as unique entities one BCD digit per 4-bit data unit: the 8-bit byte is not significant, so the fact that the 4-bit microcom4-bit

puter always handles data

in

4-bit units

can greatly simplify programming.

INSTRUCTION CODES
Memory words have so far been interpreted as data of one form or another. The contents of a memory word can also be interpreted as a code, identifying an operation which is required of the microcomputer.
Consider the simple example of binary addition. Assume that the contents of the memory word with address 0A30 is to be added to the contents of the memory word with address 0A31, and the sum is to be stored in the memory word with address 0A31. Program steps to accomplish this binary addition may proceed as
follows:
Identify the address of the first

1)

memory word

to be added.

2) 3)

Transfer the contents of this

memory word

to the microcomputer. to be added.

trans-

Identify the address of the second

memory word
to the

4)

Add the contents

of this

memory word

memory word which was

is

ferred to the microcomputer in step 2.

5)

Identify the address of the

memory word where the sum

to be stored.

6)

Transfer the

sum

to this

memory word.

3-22

Program

logic specifies that the

memory words

with addresses

0A30 and 0A31

are to contain

pure binary data:

Address of

Memory

memory word

0A2F
0A300A31
0A32'
Let us

word

Assumed

to contain

pure binary data

assume

that the six

will

program steps are

to

ing at 0400;

we

create

some

instruction

be stored in memory words with addresses startcodes to implement the six-step binary addition.
will

The

instruction

code which

identifies

memory addresses

occupy three

bytes, as follows:

10011100

9Ci6.

when

interpreted as an

instruction code,

causes the next

to

two memory words

interpreted as a data

be read and

memory address
program as follows:

We

can

now
of

start to create a

Address

Memory
I

memory word

word 9C
Read the contents of the next two memory words. Interpret them as a data memory address.

T
0400
0401

0A
30

0A30

is

the data

memory address which

the

CPU

0402

will read.

0403
0404
Step 2 requires the contents of the addressed

memory word

to

be read and interpreted as

data.

no need for the instruction to specify what kind of data the memory word contains. You, the programmer, must remember what kind of data the addressed word contains, and not try to do anything incompatible with the data type. So far as the microcomputer is concerned,
Note that there
is

data

is

pure binary data

nothing more, nothing

less.

Let us

assume

that the binary code:

II

[III!

01000000

3-23

if

interpreted as an instruction, causes the contents of the addressed data

memory word

tb be

read and interpreted as data. Our program

now becomes:

Address

of

Memory

memory word

word

0400
0401

9C

OA
30

Step

0402

0403 0404
Step 3
is

40

Read contents of addressed data word (0A30 from step and interpret as pure binary data
1
)

a repeat of step

1,

only a different data

memory

address (0A3

16

needs to be

specified.

Our program now becomes:

Address
of

Memory

memory word

word

0400
0401

9C

OA
30

>
|i

Step

0402

0403 0404
0405

40

!
1

Step 2

9C

OA
31

> )

Read 0A31. as ReadO

a data

memory address

into the

0406
0407

CPU C

Step 4
data

is

a variation of step 2;

however, instead of simply reading the contents of the addressed

memory word, the data memory word is added, using binary addition, to the data memory word that was previously read: assume that this operation is identified by the instruction code:
1 1 1

10000000
Our program now increases one step as
Address
of

follows:

Memory

memory word

word

0400
0401

9C

OA
30

Step

0402

0403 0404
0405 0406 0407

40

Step 2

9C

OA
31

Step 3

Add

contents of addressed data

data

0408
0409

word

currently stored in the

memory word CPU

to

3-24

Step 5

is

a repeat of step

3;

the address of the data

memory word where

(in

the

sum

is

to

be stored,

0A31 16

is

the data

memory word most

recently addressed

step

3).

so the instruction need not

that the binary word:

be repeated

for step 5. Instead

we

will

proceed to step
III llll

6,

and assume

01100000

when interpreted as an instruction code, causes data to be output data memory word. The complete program now looks like this:
Address of

to the

most recently addressed

Memory
word 0400
0401

memory word

9C

0A
30

Step

0402 0403 0404 0405 0406 0407 0408

40

Step 2

9C

0A
31

Step 3

80 60

'

Step 4
Store data

word

in

CPU

in

0409
Providing the microcomputer can be told

addressed by data

memory word memory address

codes

in

some way
,

that a

sequence

of instruction

will

be found beginning at<memory word 0400 16 then the fact that each of these memory words may have a pattern of 1 and binary digits which is also valid binary data, or ASCII characters, is
irrelevant.

Notice that the program .creates

contain pure binary data.
that these
It

memory addresses which

that you, as a

identify

is

assumed

microcomputer programmer,
If. by

memory words assumed to will make sure

in

memory words do

indeed contain binary data.

mistake, instructions elsewhere

your program store .charaetereades mihese

to

same memory words, then upon being commanded

do

so, the. microcomputer will

the strange results which are created

add two character codes as though they were binary data. Only will alert you to the fact that a mistake has been made.

Illustrating
is,

the concept of a microcomputer of course, just a beginning.

program

via this six-step binary addition

How does the microcomputer perform the operations required by the instruction code? That question will be answered in Chapter 4.
What does
Chapter
5.

the microcomputer demand of external logic in order to complete the operations specified by an instruction code? That question will be answered in

How do you write a microcomputer program? Chapter 6.

We

will

address that question

in

3-25

Chapter 4 THE MICROCOMPUTER CENTRAL PROCESSING UNIT

The
logic of a
in

microcomputer

is

implemented on one
.

or

more

chips. Chips are

pins, but

packaged
The one

DIPs, as was

illustrated in Figure 1-1

Most microcomputer DIPs have 40

other pin counts, ranging from 28 to 64

thing

may be

found.

you can say for sure is that one of your DIPs will conis referred to as a Central Processing Unit, or "CPU"; this is the DIP commonly called a "Microprocessor". Whatever else a microcomputer has, or lacks, it must have a CPU.
tain logic that

CPU

MICROPROCESSOR

logic that constitutes a CPU can differ wildly from one microcomputer to the next; underlying these variations there are certain necessities, however. Our purpose in this chapter is to identify these necessities.

The

Recall

from Chapter 3 that the contents of a

memory word may be

interpreted

in

one

of the

following ways:
1)

As pure

binary data binary data

2)

As coded As

3)

a character

code

4)

As an

instruction code.

These four ways of interpreting the contents two major categories: data and instructions.

of a

memory word can be

broadly separated into

Pure binary data, coded binary data, and character codes have one thing
data.

in

common: they
in

are

all

The contents

of data

memory words can be

operated on, or can be used

conjunction

with the contents of other data words.

codes are input to the CPU as a means of identifying the next operation which you want the CPU to perform. A sequence of instruction codes, stored in memory, constitute a proInstruction

gram.

Consider the six-step binary addition program described at the end of Chapter 3. Let us examine, in the following paragraphs, the logic that the CPU must contain to perform this binary addition.

CPU REGISTERS
The CPU must have one or more registers in which data ACCUMULATOR that have been fetched from memory can be stored; we will call these registers Accumulators. Since the majority of microcomputers use an 8-bit word size, that is the word size we will adopt and assume an 8-bit

Accumulator:
7

6 5 4 3 2

10

Bit

number
(A)

TT
4-1

Accumulator

To keep things simple, cumulator in the CPU.

The data fetched
Accumulator.
in

we will,

for the

moment, assume that there

in

is

just

one Acthe

step 2 of the binary addition program described

Chapter 3

is

stored

in

The CPU usually operates on the contents of an Accumulator, rather than accessing memory words directly. Does this make sense? Remember, the Accumulator is a register
within the logic of the CPU:

CPU
Accumulator

Since data

is

permanently stored

in

external

memory, you may argue

instruction

that operating

on data

in

CPU

register forces

programs to define a three step

sequence:

CPU
Step 2

Accumulator

Step

Step 3

Memory

where one step would

do:

4-2

Unfortunately the
quire

"One step" illustrated above does not always work. Some CPU operations two memory words' contents to be fetched from memory:

re-

Word A

ADDWord B
Sometimes the CPU operates on
a single word:

-> Word C

Word A

Ones Complement-

-Word C

Or we can look at the One step operation negatively: must we always spend time fetching data from memory, then returning results to memory? The answer is no. Every memory access takes time and logic. By having a few data storage registers in the CPU, we can have one memory access for every
for
is better than two memory accesses which the one step sequence requires. Therefore nearly all microcomputers have Accumulators, or Accumulator type registers in the CPU.

five

CPU

operations (approximately): and that

every

CPU

operation,

In order to access a data memory word, either to read its conDATA tents or to store data into the memory word, the data memory COUNTER word address must be identified; this address is held in a register which we will call the Data Counter. The size of the Data Counter will depend on the maximum amount of memory that the microcomputer can address. Here is a 16-bit Data Counter, which can address up to 65,536 words of data memory:

T
"i

Accumulator
i

(A)

r~i

r
Data Counter (DC)

A microcomputer's CPU can have one or more Data Counters. To keep things simple, we will, for the moment, assume that the CPU has only one Data Counter.
Referring again to the binary addition program described
in

Chapter

3,

the data

memory

ad-

dresses
In

0A30 16 and 0A31

16

would be held

in

the Data Counter register.

order to access a

of the

word of data memory, the CPU needs an Accumulator to store the contents accessed data word, and a Data Counter to store the address of the data word being ac-

cessed.
Similarly, in

order to handle instruction codes, the

CPU

is

going to need a register to store instructhe instruction

tion codes,

and

a register to store the address of the

memory word from which

code

is

going to be fetched.

The
will

instruction code is stored in an Instruction register; the CPU always interpret the contents of the Instruction register as an instruc-

INSTRUCTION REGISTER

tion code.

The address

of the memory word from which the instruction code will be fetched is provided by a register which we will call the Program Counter.

PROGRAM
COUNTER

The Program Counter is analogous to the Data Counter, but the Data Counter is assumed to always address a data memory word, while the Program Counter is assumed to always address a

4-3

program memory word.

We now

have the following four

registers:

Accumulator

(A)

Data Counter (DC)

Instruction Register
(I)

Program Counter
There

(PC)

one important conceptual difference between the Data Counter and the Program storing instruction codes in sequential memory words, the problem of creating instruction code addresses in the Program Counter is resolved. All that is after accessneeded is to find some way of Ipading an initial address into the Program Counter. ing a memory word to fetch an instruction code, the contents of the Program Counter is incremented by 1, then the Program Counter will be left pointing to the memory word containing the
is

Counter.

By

If,

next instruction code.

The Data Counter, on the other hand,

cesses. Only

is

not

likely to

have long runs of sequential memory acor data tables are held
in

when

data are stored

in

multiword

units,

contiguous

memory words, will the Data Counter be required to access sequential memory locations. Even when the Data Counter is required to access sequential memory locations, is not clear whether the Data Counter should start at a low memory address and increment, or start at a high memory address and decrement. Therefore, CPU logic is going to have to provide the microcomputer user with a great flexibility when it comes to setting addresses in the Data
it

Counter.

HOW CPU
In

REGISTERS ARE USED

order to fully understand how microcomputer CPU registers are used, we will step through the binary addition program of Chapter 3, showing how the contents of the four registers change. We will, from here on, refer to each step of the INSTRUCTIONS program as an Instruction, since in reality, each step, as illustrated, merely identifies an instruction's binary code.
Initially the Program Counter (PC) contains 0400 16 the address of the first instruction word in program memory; the contents of other registers is unknown. We assume, to complete the illustration, that data memory words 0A30 16 and 0A31 16 initially contain 7A, 6 and 2F, 6 respectively.
,
,

Address

of

Memorv Word
f
0400
0401

Memory Word
I

9C

A DC
I

0A
30

Instruction

0402

0400
Instruction 2

PC

0403
Program

40

0404

9C

Memory

0405
0406 0407

0A
31

V
)

Instruction 3

80
60

Instruction

0408

Instruction 5

I 0409
(

0A30

7A
2F

Data

Memory

\
j

^
0A31

4-4

The CPU loads the contents

thus ensuring that the

of the memory word addressed by PC into the Instruction register memory word contents will be interpreted as an instruction code. The CPU
(I),

then increments the contents of PC:

Address of

Memory Word
0400
0401

Memory Word
I

9C

A DC
PC

0A
30

>
)

Instruction

9C
0401
|

0402

0403
Program

40

Instruction 2

0404
0405 0406
0407

9C

Memory

0A
31

V
)

Instruction 3

80
60

Instruction 4 Instruction 5

0408 0409

0A30
Data

7A
2F

0A31

Memory

0A32
in the Instruction register, causes CPU logic to implement two steps. memory word addressed by PC is fetched from memory, but is stored in Data Counter (DC). The CPU then increments the contents of PC:

The code 9C, appearing

First,

the contents of the

the high order byte of

Address

of

Memory Word

Memory Word
9C

0400
0401

0A00
Instruction
1

A DC
PC

0A
30

V
)

9C
0402

0402 0403
Program

40

Instruction 2
)

0404 0405 0406 0407

9C

Memory

0A
31

>
1

Instruction 3

80
60

Instruction 4

0408

Instruction 5

0409

7A
Data

2F

Memory

4-5

Next, the contents of the

the low order byte of DC. Again the

memory word addressed by PC is fetched from memory and CPU increments the contents of PC:

stored

in

Address of

Memory Word
0400
0401

Memory Word
9C

0A30
Instruction
1

A DC
1

0A
30

>
)

9C

0402 0403
Program

0403
Instruction 2

PC

40

0404 0405
0406
0407 0408 0409

9C

Memory

0A
31

V
)

Instruction 3

80 60

Instruction

Instruction 5

0A30
Data

7A
2F

0A31

Memory

0A32
1

Execution of Instruction

is

now

complete. Observe that the contents of

LITERAL,

OR

and 0402 16 have been loaded' into the DC register. even though these two memory words are in program memory, and are addressed by the Program Counter (PC). The important concept here is

memory words 0401

16

IMMEDIATE

DATA

that the instruction

code requires data

to follow

it,

immediately. Non-instruction codes, required

in

by and appearing immediately

after instruction

codes

program memory, are

called Literal, or

Immediate data.
1, memory words 0401 16 and 0402 16 contain the immediate data code 9C, fetched from memory word 0400 16 identifies the way in which the immediate data 0A30 16 must be interpreted by the CPU. /

For example,
.

in

Instruction

0A30, 6 The

instruction

4-6

Let us

now

continue to Instruction

tents of the

2. Upon completion of Instruction 1, the CPU fetches the conmemory word addressed by PC, then increments PC. Having been given ho other

specific instructions, the contents of the fetched

word

are stored

in

the

register, to

be

in-

terpreted as an instruction code:

Address

of

Memory Word

Memory Word

0400
0401

9C

0A30
Instruction
1

DC
I

0A
30

40

0402 0403
Program

0404
Instruction 2

PC

40

0404 0405

9C

Memory

0A
31

Instruction 3

0406
0407

Instruction 4

0408 0409

60

Instruction 5

0A30
Data

7A
2F

0A31

Memory

OA32
code causes the CPU to fetch the contents memory word into the Accumulator (A):
of the

This instruction

memory word addressed by DC

and to load

this

Address

of

Memory Word
0400
0401

Memory Word
7A 9C

A
0A30

DC
PC

0A
30 40

^
J

>

Instruction

40

0402 0403
Program

0404
Instruction 2

0404 0405
0406 0407

9C

Memory

0A
31

> J

Instruction 3

80 60

Instruction 4

0408 0409

Instruction 5

0A30
Data

7A
2F

0A31

Memory

0A32

4-7

Notice that neither

DC
is

contents nor PC contents are incremented. PC contents are not increnot immediate data;
is
it was fetched from data memory. DC contents are no guarantee that data words will, in the normal course of events,

mented because 7A

not incremented since there

be referenced sequentially.
Instruction 2 has

now completed
instruction

execution, and

PC addresses the next program memory word,

which contains the

Instruction 3
is

code

for Instruction 3.
1,

a repeat of Instruction
1,

except that the

literal

data

0A30 16

has been replaced by

0A31

16

As

for Instruction
1

CPU

registers

undergo changes
I

in

three steps

when

Instruction 3 ex-

ecutes; step

fetches the instruction code to the

register:

Address of

.Memory

Memory Word

Word
7A

A
0A30

r
-

0400
0401

9C

DC
I

0A
30

>

Instruction

9C

0402

0405
Instruction 2

PC

0403
Program

40

0404 0405
,

9C

Memory

0A
31

>

Instruction 3

0406
0407

80
60

Instruction 4
Instruction 5

0408

I 0409
,

0A30

7A
2F

Data

i
(

Memory

^
0A31

Step 2 fetches
chance, that
is

0A

from word 0405 16 and stores it in the high order byte of the DC register; by what the DC register contained, so no change appears in the DC register:

Address

of

Memory Word

Memory Word
7A
I

A
DC
I

f 0400
1'

9C

0A30
>
Instruction
1

040
0402 0403
Program

0A
30

9C

0406
Instruction 2

PC

40

0404
'

9C

Memory

0405 0406
0407

0A
31

>

Instruction 3

80 60

Instruction 4

0408

Instruction

5.

I 0409
/

0A30 0A3
QA32

7A
2F

Data

<
(

Memory

4-8

Step 3 changes the low order byte of DC:

Address

of

Memory Word
0400
0401

Memory Word
7A
9C
0A31
Instruction
1

A
DC
PC

0A
30 40

9C
0407

0402 0403
Program

Instruction 2

0404 0405
0406 0407 0408 0409

9C

Memory

0A
31

Instruction 3

Instruction 4

60

Instruction 5

0A30
Data

7A
2F

0A31

Memory

0A32

Instruction 3 has

now completed
into
I:

execution, and execution of Instruction 4

is

ready to begin. As

with the previous instructions, the

ry

CPU

automatically starts by loading the contents of the

memo-

word addressed by PC
Address of

Memory Word
0400
0401

Memory Word
7A
9C 0A31
Instruction
1

A
DC
I

0A
30 40

80

0402

0408
Instruction 2

PC

0403
Program

j
*

0404 0405 0406

0407

9C

Memory

0A
31

Instruction 3

Instruction 4

0408 0409

60

Instruction 5

0A30
Data

7A
2F

0A31

Memory

0A32

4-9

The

instruction

and to add

this data

code 80 requires the CPU to fetch the contents of the data word addressed by DC word to the contents of the Accumulator (A):

Address

of

Memory Word
0400
0401

Memory Word
A9
9C

0A31
>
Instruction
1

A DC
I

0A
30

80

0402 0403
Program

0408
Instruction 2

PC

40 9C
)
J

0404 0405 0406

0407

Memory

0A
31

Instruction 3

80
60

Instruction 4 Instruction 5

0408

I 0409
0A30
0A31

7A
2F

Data

J
I

Mem0ry

0A32

Instruction 4 has
If

now completed

execution.

the

sum

in

A were

being returned to any

memory word

other than

0A31

16

we would now

have to execute another variation of Instruction 1 to load a data memory address into DC. But the Accumulator contents are to be stored in memory word 0A3T 16 and that is the memory word
,

currently addressed by DC, so a "load data

memory

address" instruction

is

unnecessary.
into data

We conmemory

tinue directly to Instruction

5,

which stores the contents of the Accumulator

word 0A31
Step
1,

16 via

these

two

steps:

fetch the instruction

code

in

the usual way:

Address

of

Memory Word

Memory Word

A9

A
0A31

0400
0401

9C

DC
I

0A
30

>

Instruction

60

0402

0409
Instruction 2

PC

0403
Program

40

0404
0405 0406 0407

9C

Memory

0A
31

>

Instruction 3

80 60

Instruction 4 Instruction 5

0408

L 0409
..

0A30
0A31

7A
2F

Data

Memory

{
I

4-10

Step

2,

store the

Accumulator contents

into the

memory word addressed by DC:

Address

of

Memory Word

Memory Word
A9
9C 0A31
Instruction
1

0400
0401

A DC
PC

0A
30

60

0402

0409
Instruction 2

0403
Program
.

40

0404

9C

Memory

0405

OA
31

Instruction 3

0406
0407

Instruction 4

0408

60

Instruction 5

0409

0A30
Data

0A31

7A A9

Memory

OA32
completed execution, and the program
is

Instruction 5 has

done.

THE ARITHMETIC AND LOGIC UNIT

CPU are handled by a group of discrete logic components referred to collectively as the Arithmetic and Logic Unit (ALU). An ALU must be capable of operating on binary data in memory word increments; in other words, an 8-bit microcomputer's ALU will operate on 8-binary digit data units. The ALU must have logic to perform the following operations:
Actual data manipulations within the
1

Binary addition

2)

Boolean operations

3)
4)

Complement
Shift a data

a data

word
bit to

word one
logic

the

right, or to

the

left.

Any more complex

up from these few

data manipulation operation required of a Central Processing Unit

may be

built

elements of the ALU.

THE CONTROL UNIT

the Control Unit (CU) that sequences the logic elements of the ALU in order to implement any required operation. The Control Unit, in turn, is driven by the contents of the
It is
In other words, the Instruction register contents are decoded by the Control response to the bit pattern of the instruction code, the Control Unit generates a sequence of enable signals to flow data appropriately through the ALU and to enable ALU logic modules at the proper time The microcomputer CPU that results is illustrated in Figure 4-1.

Instruction register.

Unit. In

4-11

The "Buffer register" holds data that are transiently in the CPU. For example, when two data bytes are added (as in Instruction 4 of the binary addition example), the data word which is fetched from memory, to be added to the Accumulator contents, will be stored in the Buffer
register.

ARITHMETIC AND LOGIC UNIT

r
STATUS FLAGS
. '

"~

"J

fe

<->
1

ACCUMULATOR
SHIFTER

DATA COUNTER
i

**

PROGRAM COUNTER
COMPLEMENTER

ADDITION

AND BOOLEAN
LOGIC

3 m < < a _

w
\

\v

-J

,-r-,

CONTROL UNIT

1 '

BUFFER REGISTER
,

**
Logic control paths are represented by:

Figure 4-1.

Functional Representation of a Control Unit

STATUS FLAGS
A CPU must
a status
flag.

or reset to reflect the results of

have a set of single binary digit logic gates which are automatically set ALU operations. Each binary digit logic gate is called

We have already encountered two status flags in Chapter 3: the

Carry and
arithmetic,

Intermediate Carry.
the Carry status, so that
it

In

order

to

perform

multibyte

CARRY STATUS
memory words:

any carry out

of the high order bit of

two data words must be

into higher order

recorded

in

may be propagated

High order
-

Low

order

word

word

10 110 11 10 10
1 1

10
1 1

10
status from
bit of

MJ_0J__0__ Carry

1-*-

high order

10

10

10
bit

10

10

low order word

High order

position

The

Carry status
6.

is

also useful

when

performing multiword

shift operations,

as described

in

Chapter

4-12

In

order to perform

BCD

arithmetic,
bits of

it

is

also necessary to record

unit,

any carry
in

INTERMEDIATE

out of the low order four

an 8-bit

since,

as described

CARRY STATUS

Chapter

2,

each

4- bit unit of a byte

encodes

a separate decimal digit.

There are some additional statuses which may also prove useful when performing various types of data manipulation or decision making operations.

A Zero status flag may be set to 1, to indicate that a data manipulation operation generated a zero result; this flag will be reset to otherwise. A word^of caution is required at this point. Most microcomputers and minicomputers have a Zero status
flag.
It

is

universally accepted that the

Zero status

flag will

be set to

if

data manipulation operation generates a zero result, while the status flag
is

ZERO STATUS

set to

for a

non-zero

result. In

other words,, the Zero status flag

is

universally set to the

complement

of the result condition.

Another important point shoufctTtoe made concerning the Zero status flag, and most other status flags?^Wiose instructions which set or reset

WHEN
STATUSES ARE MODIFIED

status flags, and those which do not, are carefully selected by microcomputer designers.

Consider the very obvious case of multibyte addition, as illustrated above. The low order words of two 2 -word numbers are added, and the Carry status is set or reset to reflect any carry out of the high order bit of the low order words. The carry must be added to the low order bits of the two
high order words of the two-word numbers. This means that the Carry status must be preserved while the two high order words are loaded into CPU registers. Clearly it would be disastrous to

program

logic

if.

when

word

of data

was loaded from memory,

generate a
carry.

the Carry status

was

cleared to

reflect the fact that the load operation did not

At

this point,

it

is

only important to

remember

that every instruction will not affect every, or for

that matter any, status flags; moreover, the

in which status flags are set or reset is very immost carefully thought out feature of any microcomputer CPU design. In other words, status flags do not necessarily represent conditions within the CPU now; they may

way

portant and

is

one

of the

well represent the results of selected key operations the

last

time these operations were per-

formed.

The use
is

of the high order bit of a memory word as a sign bit, when performing signed binary operations, gives rise to two^status flags. First, there is the Sign status, which

simply the contents of the sign

bit (or its

Sign status flag allows tests to be

made

for positive or negative

complement). The numbers

SIGN STATUS
or multiword:

when memory words

The
sign
bit is

are being interpreted as signed binary data.

bit of

always the highest order

any number, single word

One multiword number

A
(

^
highest

order

word

lower order words

-A.

X
/

-\

sign

bit

To the microcomputer, however,

Program
logic

the high order

bit of

every byte

will

be treated as a sign
to interpret
it.

bit.

must decide when

to ignore the sign. status

and when

4-13

Then there CPU is going

tion.
If

is

the overflow status.

generated

Recall that the

to treat every binary addition alike

is

microcomputer

OVERFLOW
STATUS

as a pure binary addi-

a carry

when

adding two lower order words of two

is

multiword numbers, then the carry

the sum. This
is

legal

illustrated for the addition of

and simply reflects a carry into the next higher word of two 4-word numbers, with eight bits per word:

Magnitude
Sign
bits

of

number

A
00100011 00011101 01000001
of

First number Second number

Valid carries

^
if

01011011 10111001
00010101

^
a

11001011 11011000

10111100 11000111
10000011
a single

\*
numeric enwhether is in
it

Sign

vy

10100100

The microcomputer CPU has no way

tity

knowing whether

memory word

is

or part of a multiword

numeric
far

entity and,
of the

part of a multiword

numeric

entity,

the middle of the

result of

word
is,

or at

one end

an addition

so

word. This being the case, a carry generated as the as the microcomputer logic is concerned, always perfectly valid.

When
in

the high order bit of a data word is being interpreted as a sign bit. any carry out of the penultimate bit will represent an error overflow, that is, a result that will not fit
the allocated space. Consider a single, 8-bit data word, being interpreted as signed binary data:

Sign

bit

5A

+ D3 = -3B?

+ 01101011 =1 10 10
kJ A carry

f~ 110 10

High order data

bit

10
1

out of the high order data

fit

bit

represents a result too big to

into the

allowed data space.

We
(-2)

must devise
a
carry

a strategy for identifying erroneous results of signed binary addition.

bit

Does

out of the high order data

always signal an error? Indeed no: consider

Sign
bit

+(-2) =(-4):

rHiqh order data

(-2)

bit

+ (-2) = (-4)

11111110 11111110 1111110

is

There
data

a carry out of the high order

bit

Although there is a carry out of the high order data bit, the result is 4, which is correct. We will use the symbol C s to represent a carry out of the sign bit and C p to represent a carry out of the high order data bit. What if C s and C p are both 0?
2

+2 =4

10 10
Q c n =o-~ c s =o
1

4-14

11110100

(-0C)

+ 00001001 = 11111101
C
s

+
.

09

=(-03)

=0
zero, the

C
p

=0
is

So long as both C s and C p are

answer

always

correct.
1

Now

consider some examples where C s and C p are both

10 10 + 01111001
1 1

(-75)

U C

10

+ 79 = + 4)
(

'J

(Recall that

10001011 is -75, 6 because +75, 6 twos complement of which is 10001011.)

is

01 110101. the

10 10
1

(-28)
1

+ 59 = (+31)

,w
110
+

111
1

(-39)

1110
1

110 10 10 110 u
c

+ -1A)
=(-53)

When C s and C p are

both

1.

the
is.

answer

is

always correct.
or the other, but never both are
1.

When C s and C n differ,

that

either

one

the answer

is

always

10

10
1

110
10 10 l
i

111
10

45 67
?

=(-54)

10 10 10 10 10 10

(-6E)

JO

110 110

+ (-5C) = +36

4-15

Our strategy
clear.

for setting

and
1),

resetting the

Overflow status
bits are
will

is

therefore

OVERFLOW
STATUS SET STRATEGY

When

carries out of the sign

and penultimate
will

the

same

(C

and C s are both

these two carries
the

or both
differ,

the Overflow status

be set
1.

to zero.

When

the Overflow status

be set to
is

indicating that

answer overflowed the answer space and

therefore wrong.

Stated another way. the

Overflow

will

be the Exclusive

OR

of the carries out of the sign

and penultimate

bits:

OVERFLOW =
The

C,

Parity status is the only other status which is worth mentioning at this time. This flag, if present, is set to 1 each time a data transfer operation detects a data byte with the wrong
parity. Clearly this status
.

PARITY

STATUS
'

"

contents of a

memory

be ignored most of the time, since it is only meaningful word is being interpreted as a character code.
will

when

the

INSTRUCTION EXECUTION
We
a microcomputer CPU may interpret the contents of a memory word as an instruction code. But this leaves a number of unanswered questions. What maximum or minimum number of logical events constitutes an instruction? What occurs within the CPU during the course of an instruction's execution? And what external support logic does the CPU demand?
In answering these questions, we introduce a very critical microcomputer concept, and one of the key differences between the minicomputer and the microcomputer.

have described

how

tion set

the world of minicomputers, the most important feature to look for in an instrucis the versatility of operations performed by the CPU in response to each instruction code. This is reasonable for minicomputers; minicomputers are frequently called upon to perform varied and varying tasks, and programming may be an ongoing, major expense.
In In

the world of microcomputers, this question

of external logic?

is far

more important: what does the

CPU demand
Complex

instructions usually demand complex- logic external to the CPU. This is of no concern to the minicomputer user, who buys CPU plus all external logic, packaged in a single box. This is of great concern to the microcomputer user, who must interface his logic, often directly to the CPU. If a microcomputer costs somewhere between $5 and $100, the entire economics of using the microcomputer will evaporate unless the interface logic demanded by the microcomputer CPU is also inexpensive.

Let us therefore examine how an instruction is executed, and then return, at the of this chapter, to the differences between -minicomputer and microcomputer.

end

INSTRUCTION TIMING
As with
microcomputer CPU are controlled by a which may vary from as little as 100 nanoseconds to as much as a microsecond. We will refer to this clock signal using the symbol
all

digital logic, operations within a

crystal clock, with a period

Clock Signal

.TLTLnLTL
Period

4-16

While the

crystal

must be

external to the

CPU

chip, the logic

which generates the clock

signal

may

or

may

not be on the

same

chip as the CPU. Moreover, depending on

how

the

CPU

has

been designed, the timing signal may be a straightforward single signal, as illustrated above, or it may consist of a more complex interaction of signals. Here is one possible combination of two
signals, identified

by the symbols $, and

<j> 2

_n

ji
Period

The simple

signal provides

two edges and two

Edge
1

states per period:

Edge 2

State

2-p
1

^~ State

=
The more complex
signals provide four

|*Penod-*-J

0=0
period:

edges and three states per

Period

State

1:

01 0,
(J),

State 2:
State
3:.

= = =

2
(j)

2 2

(j)

= = =

In this

chapter

we

will

use the simple signal

(J).

INSTRUCTION CYCLES
The execution of every
instruction,

two

parts: the instruction fetch

by any microcomputer, may be divided into and the instruction execute. This was illustrated
starts

earlier in this

chapter for the six-step binary addition example. Recall that every instruction

with the instruction code being loaded into the Instruction register.
as an instruction fetch.

We

will refer to this

operation

During the instruction fetch,

CPU
along

logic

outputs the contents of the

appropriate
control
signals

Program

Counter

register,
is

with

INSTRUCTION FETCH
this
is

specifying that external logic

to return the contents of the

memory word
is

addressed by the Program Counter. So

operation.

far as external logic

concerned,

simply a read

4-17

The contents
register,

of the

memory word, when

received by the CPU.

is

stored

in

the Instruction

and thus gets interpreted as an

logic
is

instruction code.

CPU uses its own internal logic to Program Counter. The Program Counter now points to the memory word following the one from which the current instruction code was fetched.
responding to the instruction fetch, the

While external
1

add

to the contents of the

Once the instruction code is in the Instruction register, triggers a sequence of events controlled by the Control Unit; this sequence of events
it

INSTRUCTION EXECUTE

constitutes the instruction execution.

Two

tion fetch, the next will

clock periods will be used to execute an instruction; one will time the instructime the instruction execute:

Instruction

Instruction)

Fetch

Execute

One

Instruction Cycle

Next consider the signals via which the CPU will communiCPU PINS cate with external logic. The 40-pin DIP, being the most popular AND SIGNALS among today's microcomputers, is the one we will adopt which means that 40 signals may be input and/or output, including the clock, power and ground.

The way

in which the 40 pins of the DIP are used constitutes one of the ble features of microcomputers, but they all begin along these lines:

most

varia

Vdd
Power and ground
Vss

Vgg
.clock

4-18

Vdd
Vss

is

the current drain connection, or the current source, or ground.

the gate voltage;
will
it

power

input.

is

Vgg

is

is

not required

in all

LSI devices.

Many

devices

show power connections much more

simply,

in

one

of

POWER
SUPPLIES

the following ways:

+ 5v+ 12v-

Gnd-

In this

case the device requires two power supplies, + 5v and + 12v, plus

GROUND

a single ground. Frequently a single

power supply

will suffice:

+ 5v-

Gnd-

The
is,

first

step,

in reality,

when executing any instruction, is the instruction fetch; that memory read. requires a memory address to be output,
It

and a data word to be input

If

in

response.

INSTRUCTION FETCH SIGNALS AND TIMING

re-

the

memory address can range from

one
for

quired,

each binary

digit of

to 65,535, sixteen address pins will be the address:

Vdd

Power and ground < Vss

'

2 3

Vgg
(])

w clock

AO
A1

A2 A3 A4 A5 A6
A7
Address
-<

A8
A9

A10
A11

A12 A13

A14 A15

4-19

All

data

will

A READ

enter and leave the microcomputer CPU via eight bi-directional signals. control signal, indicating that data must be input to the CPU, completes the

requirements for the instruction fetch:

Vdd
Power and ground
v
clock

DO
D1

Vss

Vgg

D2

D3 D4 D5 D6 D7

>Data

AO
A1

A2

A3
A4 A5 A6

READ

A7
.

Address <

A8

A9
A10
A11

A12

A13 A14
A15

The following timing diagram defines the by the CPU:

instruction fetch sequence, as controlled

AO

to

A15-

ADDRESS
STABLE

X
E

XDATA Y "
STA

DO

to

D7
Instruction

Fetch

4-20

We will nOw turn

our attention to the requirements for instruction execution.

Consider the six-step binary addition program which was described at the end of Chapter 3. There are four separate and distinct types of instructions within the program. They are:
1)

Load a memory address into the Data Counter (Instructions

and

3).
it

2)

Fetch the contents of the data word addressed by the Data Counter and store in the Accumulator (Instruction 2).

3)

Fetch the contents of the-data wordiaddressed by the Data Counter, add it to the contents of the Accumulator, and store the result in the Accumulator (Instruction
4).

4)

Store the contents of the Accumulator

in

the

memory word addressed by the

in-

Data Counter (Instruction, 5).

Let us examine how each of these four instruction types are executed, in terms of struction cycles and control signals output fiqe-and input to the CPU
Instruction 2
Like
all

is

the simplest, so
it

we

will begioi

witrHt.

MEMORY READ
SIGNALS AND TIMING

instructions,

begins with an instruction fetch.

The Control Unit decodes the instruction code 40 16 and in response causes a data word to be fetched from memory. In reality, sine the data is in a memory word on a memory device, all the CPU can really do is generate. signals at its pins-ilogic external to the CPU must respond to these
.

signals

if

the data fetch

is

to

be accomplished.

As seen by
generated

external logic, signals generated by the

CPU

to fetch data are identical to signals

for the instruction fetch.

Thus timing for a

Memory Read

instruction

is

as follows:*

AO

to

A15

V A

INSTRUCTION

ADDRESS

Y A

DATA
ADDRESS

Y A

DO

to

D7

MU3L
Instruction
I

Data
Fetch

Fetch

Memory Read
Instruction

4-21

These are the only differences between the

1)

instruction fetch

and the data fetch

cycles:

During the instruction fetch cycle, the address output on AO - A 15 is the contents of the PC register; during the data fetch cycle, it is the contents of the Data Counter. During the instruction fetch, data input
fetch,
it

2)

is

stored

in

the Instruction register; during the data

is

stored

in

the Accumulator.
If

scheme demands very little of the external logic. READ is when is high, then memory circuits must decode AO A 15. The selected memory module must extract the contents of the addressed memory word and make sure is at the microcomputer data pins when
This simple

EXTERNAL
LOGIC

high

REQUIREMENTS

it

is

low.

What

the microcomputer
is

CPU demands

of external logic during a read operation

is

standard, sim5,

ple logic that

part of

continue with
In

CPU

any memory device; but we will defer this discussion signals and timing for the ADD instruction.

to

Chapter

and

order to perform an add, the

it

word, exactly as

did for a

CPU fetches the contents of a memory Memory Read instruction; however, for the
added
to the contents of the

ADD
OPERATION SIGNALS AND
TIMING

Add

instruction, the fetched data are

Ac-

cumulator; by contrast, data fetched during a

are deposited
in

Memory Read
is

instruction

the Accumulator unchanged.

As seen by
Instruction

external logic, therefore, there

no difference between the signals

generated for an Add or a

Memory Read

instruction.

memory word addressed by

Write instruction

4 causes the contents of the Accumulator to be stored in the the Data Counter; this is called a Memory

As seen by

external logic, the only difference

MEMORY WRITE SIGNALS AND TIMING

(J)

sequences for a Memory Read and a Memory Write is that a WRITE signal must go high, instead of a READ signal, when We must therefore add a WRITE signal to our CPU device:
signal

between the

is

high

(Vdd
Vss

DO
D1

2 3

Vgg
fc_

D2 D3

rlnrk

>

Data.

AO
A1

D4

D5
D6

A2

A3
A4

D7
R

READ.
WRITE

A5 A6
A7
.Address
<

A8

A9
A10
A11

A12

A13 A14 A15

4-22

Timing

for a

Memory Write

instruction

is

as follows:

AO

to

A15

INSTRUCTION

ADDRESS

V ^

DATA
ADDRESS

/^

DO

to

D7

MjQL
Instruction

Data
Store

Fetch

Memory

Write

Instruction

Instruction 1 loads a memory address into the Data Counter. This instruction occupies three memory words, one for the instruction code and two more for the memory address.
Notice that the Load Data Counter instruction
ry reads, with these differences:
1) is

LOAD DATA COUNTER SIGNALS AND

TIMING

equivalent to

two memo-

Both Load Data Counter

trast,

the 40 16

memory reads are specified by one 9C, 6 instruction code. By Memory Read instruction code triggers just one memory read.
instruction fetches data

con-

2)

The Load Data Counter

data

from the Program Counter. For a

Memory Read

from memory words whose addresses come instruction, the Data Counter provides the

memory

address.

3)

Data read from

memory by

the Load Data Counter instruction

is

stored, in the

upper and
is

lower halves of the Data Counter. For a

in

Memory Read

instruction, the fetched data

stored

the Accumulator.

4-23

The differences between the Load Data Counter and the Memory Read

may be

instructions

contrasted as follows:

MEMORY READ

LOAD DATA COUNTER

While the logic operations internal to the CPU are completely different for the Load Data Counter and the Memory Read instructions, the external timing and signal sequences are remarkably similar. A very smart microcomputer CPU could execute the Load Data Counter instruction in three time periods, as follows:

AO

to

A15

INSTRUCTION

INSTRUCTION

ADDRESS

ADDRESS +

INSTRUCTION ADDRESS +2

DO

to

D7

I^XJQLJGEL
InstaEtiiun
I

First half

Second
of
j

half

Fetcrr

of

Address
Fetch
I

Address
Fetch

Three time period Load Data Counter instruction

4-24

not try to be so clever. In order to simplify CPU logic, the Program Counter contents are only output, as an address, during the first clock period of an instruction. The Data Counter contents, likewise, are only output during the second clock period of an ininstruction. This simpler CPU will require six clock periods to execute the Load Data Counter

Some microcomputers do

struction:

_r
AO tn A 5 ttuluM,J
1

I
V
V

Y INSTRUCTION A * ADDRESS

INSTRUCTION ADDRESS +1

INSTRUCTION

V
J\

ADDRESS

+ 2

,_T~L
DO
to

D7

_A2LA_
Instruction
1

XE$
First half
|

X^L
!

Second
of

half

Fetch

of

Address
Fetch

|
|

Address
Fetch
I

Six time period Load Data Counter instruction

HOW MUCH SHOULD AN

Let us

INSTRUCTION DO?
in this

made

now consider ways in which the instructions described simpler or more complex.

chapter

may be

The Load Data Counter

instruction loads the two 8-bit words which follow the instruction code into the Data Counter. This instruction could be broken up into two instructions, one to load the low order byte of the Data Counter, the other to load the high order byte of the Data Counter. Let us compare the two forms of the Load Data

Counter

instruction:

9C

9D
Load 0A30 16 into the Data Counter

Load

0A 16

into

Data Counter

OA
30

OA
9E

High order byte

Load 30, 6

into

Data Counter

30

Low

order byte

One

three-byte Load Data Counter instruction

Two

two- byte Load Data

Counter Instructions

4-25

The three-byte Load Data Counter instruction's possible signals and timing have been The two 2-byte instructions could each execute in two time periods or in four
ecuting
in

illustrated.

time periods. Ex-

two time

periods, signals

and timing

for

each instruction would be as follows:

AO

to

A1

INSTRUCTION

ADDRESS

INSTRUCTION

ADDRESS +

V"
i

INSTRUCTION

ADDRESS

INSTRUCTION

ADDRESS +

I
I

I I

_r
DO
to

I
"

D7

L
i

lM-J^^_lKl^Ei
1

T
| I '

First
|

First half

Second
Instruction

Second
of
|

half

'

Instruction

of

Address
Fetch

Address
Fetch

Fetch

Fetch

Timing and

signals,

when

executing

in

four time periods,

would be as

follows:

J
i0 to

I
VinstructionV ftADDRESS + lA
I I

AIR

"VinstructionV ADDRESS A
ft
I

VinstructionV | ADDRESS ^
I

Vinstruct'IonV"

XaDDRESS + i'X
I
I

READ-J

DO

to

D7
First

JO.
First half

Second
Instruction

Second
of

half

Instruction

of

Address
Fetch

Address
Fetch

Fetch

Fetch

simplify the

Breaking the three-byte Load Data Counter instruction into two 2-byte instructions does not demands placed on external logic by the CPU: but it does make the microcomputer's

Control Unit simpler, as ming.

we

will

demonstrate

later in this

chapter

when

describing microprogram-

4-26

Now

consider combining the Load Data Counter and

Memory Read

instructions as

follows:

41

Load

into the

Accumulator the contents

of the of this

memory
three-word

OA
30

word addressed by the next two words

instruction.

As

tion;

Memory Read instrucmemory word whose contents is to be read into the Accumulator. Instructions that specify the memory address to be referenced, as this DIRECT three- byte Memory Read instruction does, are said to have direct memory
illustrated

above. 41

16 is

the instruction code specifying this three-byte

OA30 16

is

the address of the

addressing.
Signals and timing for the three-byte

ADDRESSING
Memory
Read instructions could take one of

many

forms.

Here

is

the most

compact

possibility:

A0

to

A15

DO

to

D7
j

Instruction

III'
j

Fetch High

Fetch

Low

Fetch Data

Fetch

Order

half of

Order

half of
J

Data Address

Data Address
Instruction
I

Three-byte

Memory Read
Execution

To

Memory Read

a minicomputer designer, combining the Load Data Counter instruction with the is obvious. or with any memory reference instruction

To the microcomputer designer, the automatic

virtues of direct addressing are not so obvious, for the immediately apparent reason that direct addressing instructions require more complex Control Unit logic; this will be illustrated later in this chapter
is

when microprogramming
But there
is

described.

immediately apparent reason why direct addressing is not obviously desirable; whereas most minicomputer programs are stored and executed out of RAM, most microcomputer programs are stored and executed out of ROM; that means direct addressing can only be used when the data address will hot change.
less

4-27

Consider an elementary instruction sequence which receives data input from an external device, then stores the data into a

REFERENCING

number

DATA TABLES

of consecutive

memory words:

From

External

Device

RAM
dress.

data

memory words in the above illustration constitute a "data table." The 0A10 16 has been arbitrarily selected; any other address would do as well.
.

beginning ad-

Ignoring, for the

ble,

moment, the question of how the following instruction sequence would

Arbitrarily

many
fill

data words are to be stored

in

the data ta-

the data table:

selected

Program

addresses

Memory
9C

0280
0281

0A
10

Load the address 0A10 16

into the Data

Counter

0282

0283

08
60
E3

Input a byte from an external device to Accumulator

0284
0285 0286 0287

Store Accumulator contents

in

memory

Increment Data Counter

Reset Program Counter to 0283

BC
83

straightforward Load Data Counter instruction, stored in program memory 0281 16 and 0282 16 loads the address 0A10 16 into the Data , Counter; this is the address of the first word in the data table.

words 0280 16
instruction

The

code 08 16

in

program memory word 0283 16 causes a byte

,

of data to

be input

to

the Accumulator from an external device.

instruction code 60, . in program memory word 0284, , is a simple Store 6 instruction; it causes the contents of the Accumulator to be stored in the data memory word addressed by the Data Counter; initially that is the first word of the data table, with

The

Memory

address 0A10, R

The next two instructions, located in program memory words 0285, 6 0286, 6 and 0287, 6 increment the Data Counter contents (to address the next word of the data table), then change the value in the Program Counter to 0283, 6 execution now returns to
, . ;

PROGRAM
LOOP
the instruction which

brings the next data

program loop
task

have established a a group of instructions that continuously get re-executed; a slightly different
is

word

into the

Accumulator from the external device.

We

is performed on each re-execution, because the Data Counter contents each pass.

incremented on

4-28

Four instructions, occupying five length of the data table may be!

memory

bytes, can

fill

a data table, whatever the

Using direct addressing, this program loop could not be executed.

Program

We would

have:

Memory
0280
0281

08
61

Input a byte from an external device to Accumulator

0282

0A
10

(Store Accumulator contents

in

data

memory word
bytes

raddressed by the second and

>

third instruction

0283 0284
0285 0286

Increment what?

tlata table is addressed by the second and third bytes of the memory-storewith-direct-addressing instruction. This address cannot be incremented if it is going to reside in ROM! Minicomputers have a solution to this problem, of course (we shall see what the solution is in Chapter^), but the solution adds complexity to microcomputers and the complexity may bring with it more cost than savings.

The

Two of the new instructions

point.

in

the program loop need to be described-further at this

The Increment Data Counter

of the Data
logic external to the

instruction simply causes the contents

1;

Counter to be increased by

following the instruction fetch,

CPU OPERATE
INSTRUCTIONS

CPU

is

idle:

AOto A15

Y A

INSTRUCTION

* bpRESs

V A

DO

to

D7
Instruction

CPU
operations

Fetch

CPU
Operate Instruction

4-29

The instruction in program memory words 0286 16 and 0287 16 actually changes the contents of the Program Counter, and
thus changes the sequence in which instructions are executed. This is referred to as a Branch or Jump instruction.

BRANCH
INSTRUCTION

JUMP
INSTRUCTION

Branch instructions have many variations. A two-word version is illustrated in the program loop; the contents of the second instruction word is loaded into the low order half of the Program Counter as follows:

0285 0286 0287

E3

ABSOLUTE BRANCH

BC
83

0285
0286 0287

E3

BC
83

The problem with this variation of the Branch instruction is that it will not work if the Program Counter high order byte
gets incremented. For example, suppose
in

the program loop

was

stored

BRANCHING AT PAGE

memory

as follows:

BOUNDARY
Program

Memory
02FC
9C
\
J

02FD
02FE
02FF

0A
10

Load Data Counter

1
}

08

Input from External Device

0300
0301

60
E3

Memory

Write

j
)

Increment Data Counter

0302

BC
FF
j

0303

Branch to FF

Branch to FF 16 would branch to 03FF 16 not to 02FF 16 because the high order byte gram Counter got incremented between the input and memory write instructions.
, ,

of the Pro-

There are two ways around this problem.

we can have a three-word Branch instruction which changes both halves of the Program Counter.
First,

Second,
struction
it

we

word

interprets the

can add the contents of the second Branch into the Program Counter, designing the CPU so that second Branch instruction word as a signed binary numprogram
loop, after the

PROGRAM
RELATIVE

BRANCH
this value to

ber. Referring to the

Branch instruction had ex-

ecuted, the Program Counter would normally contain

5

0288 16

to

change

0283 16

must be subtracted. The twos complement

of 5

is:

111110

11

4-30

8FB 16 This is the value that would be stored in program memory word 0287 16 Adding an value from memory to the 16-bit contents of the Program Counter using signed binary arithmetic is not a problem; CPU logic simply propagates SIGN the sign bit through the high order half of the value to be added PROPAGATION to the Program Counter. In this case we have:
or
. .

bit

Program Counter
Value added

(old)

0.0.0

.1.0

1:

1tflJ^J_1111011

Program Counter (new)

Sign

bit

propagation

Sign

bit

Adding 5

to the

Program Counter contents would proceed as follows:

2

Program Counter Value added

(old)

Q.

0.1.0

10

:i:^::^::^:-6:::0::Qx0:p

10 10

Program Counter (new)

Sign

0000001

0T

0001 101
Sign
bit

bit

propagation

This

is

referred to as a Program Relative branch.

MICROPROGRAMMING AND THE CONTROL UNIT

Let us

now examine how the

Control Unit decodes instruction codes.

A microcomputer CPU may be illustrated functionally, as in Figure 4-1, but in reality, the CPU consists of a number of logic elements, activated by sequences of
enable signals.
The Complementer,
ing
for

example,

is

latently able, at

eight data latches within the logic of the

complementer

any time, to complement the contents of circuits. A single enable signal, emanat-

from the Control

Unit, will activate this logic

sequence.

We

However, complementing eight data latches within the Complementer serves no useful purpose. want to complement the contents of the Accumulator, and that means moving the contents returning the of the Accumulator to the Complementer, then, after enabling complementer logic,
results to the

Accumulator.

4-31

Complementing the contents of the Accumulator therefore requires these five steps: Move the contents of the Accumulator to the Data Bus: 1)
ARITHMETIC AND LOGIC UNIT
STATUS FLAGS

ACCUMULATOR

\
\
\ 1
\
I

H*
H
i

-t^_
DATA COUNTER

COMPLEMENTER

PROGRAM COUNTER
INSTRUCTION REG

ADDITION

AND BOOLEAN
LOGIC
:

d
CONTROL UNIT

BUFFER REGISTER

>-u

DATA BUS

2)

Move

the contents of the Data Bus to the Complementer:

ARITHMETIC AND LOGIC UNIT

r~

STATUS FLAGS

K*n
ACCUMULATOR
DATA COUNTER

COMPLEMENTER

*c

10110101

Kr
'

PROGRAM COUNTER
INSTRUCTION REG

ADDITION

AND BOOLEAN
LOGIC

*-<D

CONTROL UNIT

BUFFER REGISTER

4-32

3)

Activate

Complementer

logic:

ARITHMETIC AND LOGIC UNIT

n
ACCUMULATOR

r*H"

STATUS FLAGS

-*[
COMPLEMENTER

DATA COUNTER
PROGRAM COUNTER
INSTRUCTION REG

ADDITION

AND BOOLEAN
LOGIC
I

-h

^0

CONTROL UNIT

BUFFER REGISTER

4)

Move

the contents of the

Complementer

to the Data Bus:

ARITHMETIC AND LOGIC UNIT

*W

STATUS FLAGS

|< >
ACCUMULATOR
DATA COUNTER

h: *c
J.

COMPLEMENTER

K-r
ADDITION

PROGRAM COUNTER
INSTRUCTION REG

AND BOOLEAN
LOGIC
I

"XD
,

CONTROL UNIT

BUFFER REGISTER

4-33

5)

Move

the contents of the Data Bus to the Accumulator:

ARITHMETIC AND LOGIC UNIT

r-C

STATUS FLAGS

COMPLEMENTER

ACCUMULATOR
DATA COUNTER

-c
-o
i

PROGRAM COUNTER
INSTRUCTION REG

ADDITION

AND BOOLEAN
LOGIC

0'
CONTROL UNIT

BUFFER REGISTER

Each of these five steps is referred to as a microinstruction. Each microinstruction is enabled by a signal from the Control
Unit. By outputting the appropriate sequence of control signals, the Control Unit can sequence any number of microinstructions, to create a macroinstruction, which is the accepted response of
the
In

MICROINSTRUCTIONS

MACROINSTRUCTIONS
MICRO-

CPU

to

an assembly language instruction code.

order to complement the Accumulator contents, the Control Unit must contain five binary codes, each of which triggers an appropriate control
signal (or signals). This

PROGRAMS
that are stored within

sequence

referred to as a microprogram. Generating the

the Control Unit

is

referred to

codes within the Control Unit is sequence of binary codes as microprogramming.

of binary

There is a close gramming.

parallel

between microprogramming and assembly language

pro-

4-34

A
bly

microprogram
language

is

stored as a sequence of binary digits stored as a sequence of binary

is

in

the Control Unit.

An assembly

language program

is

digits, usually in a

program
initiates

referred

to

as

macroprogram.

memory. The assemEach instruction code of the

in

ROM

macroprogram

execution of an entire microprogram, as stored

the Control Unit:

EXTERNAL DATA BUS

ROM
1

DATA

ALU

Z> - OQ

< 1<
CU DATA

\^
1
1

3.-rr
:
:

JVBCRDP.R(QGRAW:::

CPU
each macro- instruction code causes one entire microprogram to be executed

RAM

microprogram stored

in

the Control Unit has a data

memory, which consists

for variable data:

of the

CPU

registers, plus a data storage internal to the Control Unit.

A macroprogram

has a data area, which

consists of

ROM memory

for

constant data, plus

RAM memory

r
i

EXTERNAL DATA BUS

,
1

*
:

yy-mM-yyco

y:+\
*
:-x::-:
:

A
DC
: :
:

::::::::::::

ALU

< < Q
i

: :

PC

L.J
'.

<

3 u

" "
."

y0A &&?A: MICROPROGRAM

'

.'..':

CP U

Microprogram
data area

o cc Q_ o cc u < 2
ROM

RAM
\

W T:A
;;:;::

RAM
IV

acroprograrn

d ata area

microprogram implement a small logic sequence within the logic of the macroprogram cause an entire microprogram to be executed, thus implementing a whole sequence of operations within the CPU.
Individual instructions of a

CPU.

Individual instructions of a

4-35

of operations associated with any MACROa direct function of the size of the INSTRUCTION microprogram whose execution the macroinstruction initiCOMPLEXITY ates. There are no logical breakpoints or levels at which a microprogrammer must terminate the microprogram which will be executed in response to any macroinstruction code. Of course, complex microprograms require large Control Units. A simple microcomputer may have a small Control Unit and therefore may be forced to execute very simple macroinstructions. Some large computers have no assembly language, but in response to a single macroinstruction code, execute complex sequences of events involving logic throughout the computer system

The complexity
macroinstruction

is

The Control Unit

of every

microcomputer

is

in

reality

MICRO-

nothing but a microprogram. If you, the user, are able to PROGRAMMABLE create or modify the microprogram within the Control Unit, MICROCOMPUTER then the microcomputer is said to be "microprogrammable". If the Control Unit microprogram is designed by the microcomputer logic designer, and then becomes an unalterable part of the CPU chip, the microcomputer is not microprogrammable.
In this book we are going to describe these two separate and distinct classes of microcomputer product:
1
)

The microprocessor based microcomputer which gives you access

to a Central

Processing Unit, but not to the Control Unit. You sequence CPU logic using macroinstructions. referred to collectively as an Assembly Language instruction set. You cannot microprogram this class of microcomputer product; nonetheless, a basic understanding
of

microprogramming

will

help you understand the tradeoffs that every microcomputer

putting together an instruction set.

designer must evaluate

when

The "microprocessor
blocks",

slice"

or

microcomputer. Here you

which you must
tie

are presented with

"macrologic" based CPU "building

MACROLOGIC
MICRO-

together with a microprogram.

PROCESSOR
SLICE

MICROPROCESSOR BASED MICROCOMPUTERS

First

we

will describe

microprocessor based microcomputers.

Let us identify an arbitrary set of control signals, as illustrated in Figure 4-2. Our microcomputer Control Unit will generate these control signals to implement macroinstructions. Tables 4-1, 4-2 and 4-3 describe these control signals.

When compared
make
real

to the ingenuity of real chip slice microinstruction codes. Tables 4-1, 4-2
inflexible

and

4-3 represent a somewhat simplistic and

chip
logic designer

CPU

logic organization. Nevertheless, they will

clarifying the goals that the chip slice

slice architecture easier to

understand by

must

attain.

signals described in Tables 4-1, 4-2 and 4-3 do not allow the Control Unit to perform all of the operations which will be needed to support assembly language instructions. For example, nothing has been said about how the READ and WRITE control signals will be generated, or how the four status latches C (Carry), (Overflow), S (Sign) and Z (Zero) will be handled. One primitive scheme for handling these problems is to trap microinstructions that attempt to set both CO and C to this is an impossible condition, since specifies data moving on and off busses simultaneously. If CO and C1 are both 1, they will
1 1
;

The control

it

be output as

0, and the remaining signals, C2 through C8, will be interpreted as specifying the following five different classes of internal Control Unit operations:
1)
If

C2 through C8

are
in

all

0,

then the status latches

Z, S,

and

C, in the

ALU,

will.

have

their

condition recorded

the

CU DATA

buffer.

4-36

AO

A1

A? A3

A4

m 1
\c
1

M
AH A/

z K^=j>

cc

DATA COUNTER PROGRAM COUNTER

en

c6

n <

A8 A9 A10
A11

c7 ALU LATCHES
cARITHMETIC

A1?

A13
A14 A15

AND
BOOLEAN
LOGIC
ft

BUFFER REG

f
Dl

if
Accumulator -Bata Counter (HI) Data Counter (LO) Program Counter (HI) Program Counter (LO)
-

D2

D3
D4

D5 D6
D7

I
__7TTT
I I l

-Instruction

WRITE

Status
-Shifter

READ

Compl

ALU
-Buffer
Data Register

1
I

^Jc^
Figure 4-2.

Data Counter to ADDR Program Counter to ADDR Data to Buffer

Control Unit Signals For a Simple Microcomputer

Table 4-1.

Control Unit Signals

SIGNAL
CO. CI

FUNCTION
C0=0. C1 =0; No data moved onto, or off Data Bus or Address C0=1. C1=0; Data moved onto Data Bus. or AddressRegister Data moved off Data Bus. or Address Register CO =0, C =
1 1
;

Register

C0=
C2.C3.

1.

C1

= 1;

Microinstruction will be trapped within the Control Unit (see

Table 4-4)

WhenC0=1 C1=0, orC0=0C1=1.

These three
4-3.

these four signals are decoded to select Table

C4.C5
C6.C7.C8

specific data flow, as specified in Table 4-2.

signals are

decoded

to select ALU operations as specified

in

WRITE.

Direct connections

from the input pins to two

CU data

bits.

READ
Clock signal input to

CU
connected to four

c.o.sz

Four status

bits, directly

CU

data

bits.

4-37

Table 4-2

Data Flow Select

When CO=1

Or C1 =1

FUNCTION
Accumulator

Data Bus select

Data Counter high order byte

Data Counter low order byte

Data Bus

select

Data bus select

Program Counter high order byte Data Bus select Program Counter low order byte Data Bus select
Instruction Register

-Data Bus

select

Status Register
Shifter

Data Bus select

Data Bus select

Complementer

Data Bus select

ALU ALU

latches

Data Bus select

select

Buffer

Data Bus

Data Register

Data

Bus select

Data Counter

Address Register select

Program Counter -Address Register select

Data Register

Buffer Register

Not Used

Table 4-3.

ALU

Select Signals

c8
1

c7

c6

FUNCTION
Select shifter logic
Select complementer logic

Select addition logic* Select

1

AND logic*

OR logic* Select XOR logic* Increment ALU latches No ALU operation

Select

"Operation

is

performed on contents of
in

ALU

latches

and Buffer

register.

Result appears

ALU

latches.

4-38

If

C2 and C3
S.
if

are

and

0.

then C5. C6. C7 and C8

respectively.
If

will 0,

be interpreted as corresponding to the

in

Z,

and C statuses,

C4

is

the status conditions

the

ALU

are

referenced:

C4

is 1.

the status conditions stored irrthe

for a
1

DATA

buffer are referenced. C5, C6,

C7 and C8
will will

will

each be checked
If

value.

If

is

found, then the corresponding status

1, then the next microinstruction be skipped. This use of the nine controls C through Cg may be illustrated as follows:

be checked.

the corresponding status has a value of

Cfi

Cj Cr Ct C 4 Ct Co Ci Cn

.Skip next microinstruction

.0
1

on status = = ALU status settings specified = CU DATA buffer status settings specified
1

,Z
_S Status selected, and should be tested
for setting of
1

.0

X
If

Do

not test this status

C2 and C3 are and 1, then the logic of condition 2 described above will be repeated; however, corresponding status flags will be checked for values as the condition which forces the next microinstruction to be skipped.
If

C2,

C3 and C4

are

1,

and

0, respectively,

then C5, C6, C7 and C8 specify the status of

output at chip pins.

four control signals which the Control Unit

may

We
C8

have only described

specifies the condi-

two

control signals thus

far:

READ and WRITE.

We

will

assume

that

tion of

READ and C7
may be
Ct;

specifies the condition of

WRITE. This use

of the nine controls

Cq

through C 8

illustrated as follows:

C 8 C 7 Cc

C 4 Ct C? Ci Cn

1111
.Output control signals
.Not currently specified .Not currently specified

.WRITE assumes

value of this

bit

.READ assumes
5)

value of this

bit

When

C2,

C3 and C4

are

all

1,

then C5 through C8

will

be decoded

internally to specify

one

of 16 logical operations internal to the Control Unit.

We will

not attempt to define what these

operations might be.

will now create some microprograms. Let us begin simply, by creating an instruction fetch microprogram. Recall that every instruction's execution starts with an instruction fetch; therefore, the instruction fetch microprogram must precede every microprogram which implements an instruction's execution. The instruction fetch microprogram is shown in
Table 4-4.

We

Before analyzing the instruction fetch microprogram, microinstruction-by-microinstruction, a few general comments must be made.

Each microinstruction becomes nine binary digits within the MICROControl Unit. The 8 -bit (or byte) unit was selected as the word INSTRUCTION size for the microcomputer because this word size is useful BIT LENGTH when representing characters and numeric data, in addition to representing instruction codes. The Control Unit microprogram does not represent numeric data or instruction codes; therefore, the microinstruction bit length is arbitrarily set to whatever the microcomputer needs in this case nine bits. Since there
'

4-39

Table 4-4.

An

Instruction Fetch

Microprogram

Instruction

MICROINSTRUCTION

CODE
C 8 C} C5C5C4C3C2C Co
1 1

Number
1

FUNCTION
Move Program Counter
Set
to

110 110

Address Register

2 3

0001
1

READ Control
Data Bus to

signal true.

WRITE

false

10

10
11

Move, Program Counter low order byte

to Data

Bus

4
5

110
1

Move

ALU

latches

6
7

8 9
10
11

10 10 10 10 10 10
1 1 1

Increment
1

ALU

latches

Move ALU latches to Data Bus Move Data Bus to Program Counter low Move Program Counter high order Move Data Bus to ALU latches
Skip next microinstruction
if

order byte

byte to Data Bus

110
10

11

10
1
1

carry status

Increment

ALU

latches

12 13

110

10
1

Move ALU Move Move

Move

latches to Data Bus

1110

Data Bus to Program Counter high order byte Data Register to Data Bus Data Bus ^Instruction Register

14 "5

111010 110101
in

are 15 microinstructions
required,

the instruction fetch microprogram,

s total

of

135 binary

digits will

be

a 9

15 binary digit matrix, to hold the instruction fetch microprogram

tion fetch,

Notice also that a sequence of 15 microinstructions are executed during the instrucwhich must occur during one period of clock 0. The Control Unit will the cock therefore internally split the clock signal into 16 subdivisions. In other words has a oenod of one microsecond each microinstruction must execute withm 62 5 nanoseconds Since the average CPU chip consists of densely packed n MOS or p MOS logic, this time oenod is
f

reasonable

Now
The and

consider, in detail, the 15 steps of the~instruction fetch

microprograms
CO and
it

first

two

bits of

the

first

microinstruction's C
will

nit

code, representing

C1. are set to

into the

0. respectively,

they indicate that data

he moved onto the Data Bus. or

1

Address

10 1; they specify that is the contents of The next four bits are set to the Program Counter which must be moved to the Address register (see Table 4-2). Since no
register (see Table 4-1).

simultaneous

ALU

operations are to take place, the

is

last

three bits are

all

set to

(see Table 4-3)

The

creation of this microinstruction

illustrated as follows:

C 8 Ct C b C 5 C 4 C 3 C 2 C. Co

hhl'|i|o|i|i|ohl
Move
.4
.

data onto Data Bus or Address register (see Table

1) is

Program Counter

source (see Table 4-2)

3)

.No ALU operation (see Table 4

you have any
difficulty
:

If

some

of the other microinstructions in detail, to

1.

understanding the crea" on of the first microinstruction, you should study see how they are also created from the informa-

tion m. Tables 4-

4-2 and 4-3

4-40

Microinstruction

moves

the contents of the Program Counter to the Address register, thus mak-

ing the 16-bit contents of the

Program Counter appear

at

the 16 address pins. Instruction 2 sets

the contents of which are to
is,

the

WRITE

control signal false

and the

READ

control signal true; this tells external logic that pins

AO through A15
be placed
to
at pins

provide the address of an external

memory word,

DO through

D7. External logic has 687.5 nanoseconds, that

13, in

the time

it

takes

execute microinstructions 3 through

which

to fetch the requested data.

is

Microinstructions 3 through 13 increment the contents of the Program Counter, as

required

during every instruction fetch. Since the Program Counter

is

16 bits long, while logic within the

in

CPU

is

only 8 bits wide, the Program Counter has to be incremented

7

two

steps. Instructions 3
in

through

increment the low order

(in

half of the
only),

Program Counter.

If

this

increment results

the

carry status being set

the

ALU

then the high order

half of the

Program Counter must also be incremented. If the carry status is not set, then the high order half of the Program Counter must remain unaltered. Microinstructions 9 through 13 handle the high order half of the Program Counter. These microinstructions parallel microinstructions 3 through 7; however, microinstruction 10 specifies that the Carry status (in the ALU) is
if

STATUS
MICRO-

IN

PROGRAMS
0,

^^~

then microinstruc-

1, which actually performs the increment on the contents of the ALU latches, be skipped. Thus the high order half of the Program Counter is only incremented if the Carry status was set when the low order half of the Program Counter got incremented.

tion

in its

Note that Control Unit logic must be very specific about when it records statuses CU DATA buffer and when it does not. Use of the Carry (C) status as a means of conthe Program Counter increment
in
is

trolling

only valid

if

the Carry status

is

not permanently
in

recorded
the
buffer,

the Control Unit.

time.

In

other words, the Control Unit can reference the status latches
instructions-reference the statuses stored
in

ALU any

Assembly language
in

the

CU DATA
buffer.

never the statuses

if

the

ALU
in

latches. Microinstruction

code 0000001
in

must be executed

by the Control Unit

the statuses

the

ALU

latches are to be saved

the

CU DATA

consider the five steps needed to complement the contents of the Accumulator. during the 15th step of the instruction fetch microprogram, the code loaded into the Instruction register is a Complement Accumulator instruction code, then Control Unit logic will
If,

Now

COMPLEMENT
MICRO-

PROGRAM

branch to the microprogram

In

shown

in

Table 4-5.

order to

complement
one period

the Accumulator, a 45-bit microprogram

in

these five microinstructions can be executed

must be executed. Even though 312.5 nanoseconds, system synchronization de-

mands
time

that

of clock

be set aside for instruction execution; therefore, the remaining

will

be wasted.

Let us
or
tion

now consider the tradeoffs associated with

having simple

complex instruction sequences. With

reference to the binary addi-

ASSEMBLY LANGUAGE
INSTRUCTION MICRO'

word

program which was described earlier in this chapter, recall that a of data can be loaded from memory into the Accumulator in one of

the following ways:

1)

PROGRAMS
instructions,

Issue

two separate

each of which loads

half of the

Data Counter with half of the

data

memory

address for the data

third

memory word whose

contents must be loaded into the

Accumulator. Then issue a

instruction to load the contents of the

addressed data

memory word
2)

into the

Accumulator.

Use one instruction to load into the Data Counter the entire data memory address for the word whose contents is to be read into the Accumulator. Then issue a second instruction to

move
3)

the contents of the addressed data

memory word

to the Accumulator.

Have a single direct addressing instruction which loads the data the Data Counter, then loads the contents of the addressed data cumulator.

memory word address into memory word into the Ac-

4-41

Table 4-5.
Instruction

A Complement Accumulator

Microprogram

MICROINSTRUCTION

CODE
C8C7C6C5C4C3C2C1C0
1
1

Number
1

FUNCTION
Move Accumulator
to

10

Data Bus

1110
1 1

110
10 10
1

Move

Data Bus to Complementer

3 4 5

100000000
1

Execute Complementer logic

10 10
phase

Move Complementer to
Move
Data Bus
to

Data Bus

Accumulator

The

instruction execution

of

each

instruction, for the three

in

ways

in

which data can be

loaded into the Accumulator, are

shown

Tables 4-6, 4-7 and 4-8.

Table 4-6.

Three-Instruction

Memory Read

Instruction

MICROINSTRUCTION

CODE
C8C7C8C5C4C3C2C1C0
Fetch (Table 4-4)

Number
1

FUNCTION
Repeat microinstructions
1

through 14 of Instruction

14
15

1110
half of

10

10

Move Data Bus

to Data Counter,

low order byte

(A)

Load low order

Data Counter

Instruction

MICROINSTRUCTION

CODE
C 8 C7C e C 6 C4C3C2C ,Co
Fetch (Table 4
4)

Number
1

FUNCTION
Repeat microinstructions
1

through 14 of Instruction

14

15

11110
half of

10

Move Data Bus

to Data Counter, high order Dyte

(B)

Load high order

Instruction

Data Counter

MICROINSTRUCTION

CODE
C8C7C6C5C4C3C2C1C0

Number
1

FUNCTION
Move
Set

1110
10
1 1

110
10
1 1

Data Counter to Address Register

Control signal true.

READ
1

WRITE

false

10 10

Include

no operations

to give external logic

more

time to fetch data

14
1 1

15 16

111110
1 1

10

10 10
1

Move Move

Data Register to Data Bus Data Bus to Accumulator

(C)

Load Addressed Data Memory Word Contents

Into

Accumulator

4-42

Table 4-7.

One

Instruction

To Load

16-Bit

Address

Into Data

Counter

Instruction

MICROINSTRUCTION

CODE
FUNCTION
Repeat micromstrucions
Fetch (Table 4-4)
1

Number C8C7C6C5C4C3C2C1C0
1

through 14

of Instruction

14
15
1
1

10 10
1

10
c

Move

Data Bus to Data Counter, low order byte

16 17

Timing

filler
1

Repeat microinstructions Fetch (Table 4-4)

through 14 of Instruction

30
31

11110

10

Move

Data Bus to Data Counter, high order byte

Table 4-6(C) provides second step for Table 4-7.

Table 4-8.
Single Instruction, Direct Addressing.

Memory Read

Instruction

MICROINSTRUCTION

CODE
CSC7CQC5C4C3C2C-1C0

Number
1

FUNCTION
Repeat microinstructions Fetch (Table 4-4)
1

through 14 of Instruction

14 15
1
1

10 10 10

10

Move

Data Bus to Data Counter, low order byte

16
17

Timing

filler
1

Repeat microinstructions
Fetch (Table 4-4)

through 14 of Instruction

30
31

11110
1 1

10

Move

Data Bus to Data Counter, high order byte

32 33 34

1110
10
1 1

10

Timing

filler

110

Move
Set

Data Counter to Address Register

control signal true.

10 111

READ

WRITE

false

35

10 10

Include 12 no operations to give external logic

more

time to fetch data

46 47

111110
1 1

48

10

10 10
1

Move Move

Data Register to Data Bus Data Bus to Accumulator

briefest glance at Tables 4-6, 4-7 and 4-8 shows that microprograms are going to have a lot of duplicated microinstruction sequences. The very first thing a microcomputer designer will do is try to eliminate this duplication by re-using frequently needed microinstruction sequences.
Also, a

The

microcomputer designer

is

going to develop some simple means of giving external logic

time to respond to a

READ

request, rather than having 12

no operation microinstructions, using

up 108

bits of

the Control Unit storage space.

These are the complications which forced the early microcomputer designers to keep microcomputer assembly language instructions simple. There are many ways in which microprogram sequences can be re-used, and time delays can be implemented; we left 16 microinstructions free for just this kind of operation. Precious Control Unit storage is used up solving these complications, and the more complications there are within a single instruction, the more complex this extra

Control Unit logic gets to be.

4-43

CHIP SLICE BASED MICROCOMPUTERS

quently this

based microcomputer will not meet your needs; frehappen because the microprocessor is not fast enough. You are now a candidate for "chip slice" or "macro logic" based microcomputers, which let you design and build your own CPU, with any CPU architecture (within limits), and any, or no assembly

Suppose

a microprocessor
will

language instruction

set.

Before we examine what a chip slice product must consist of, a word of caution. This discussion of chip slice products is something of a tangent within the context of products discussed in this book.

CPU logic that will to this point we have been describing microprocessors be implemented on a single chip, or may be part of a single chip. Chapter 5 describes additional logic which supports microprocessor based microcomputers.
Up
As compared
to microprocessors, chip slice products take a wholly different philosophical direction:
build chips with less logic, where each chip provides building blocks of any CPU; then we justify less logic

We

chips

one of the fundamental and therefore more

with increased performance.

Thus, you could use chip slices to build the equivalent of any microprocessor. You would then have a product with perhaps ten chips instead of one, but it would execute instructions ten times
as
fast.

Describing chip slices at the end of Chapter 4 implies that chip slices are essentially
blocks.

CPU

building

That is the frame of reference in which we choose to describe chip slices; however, when you have finished reading Chapter 5, you will realize that chip slices could be used equally well to build the equivalent of any support logic device, excluding ROM or RAM.
If

we

are to create

CPU

building blocks,

how

should

CPU

logic

be divided

so that the resulting pieces are very general purpose?

CHIP SLICING

We

cannot impose instruction set

will

limitations;

if

blocks

not be general purpose. Therefore,

we do, the CPU building we begin by separating

PHILOSOPHY

control unit logic from the rest of the

CPU:

All

A-

Registers

N ^

Status flags,
Shifter

C/5

C
t7)

o c n
Ji

Complementer, A. ^r Arithmetic and Boolean logic

CD

CC

TO

Buffer Register

A-

N V

::::::

: i
:

: :

: :

&<kFiftSf::SS;

Data

I;:.;,;,

Uoit

:.:-:
: :

: :

% ..

_in/0u

implement
separately

4-44

Now

if

you

refer

Control Unit,

in reality,

back to our discussion of microprogramming, you will see that a consists of a microprogram stored in Read Only Memory:

Control Unit (CU)

jMILflOPflOGRAM

The shaded area marked "microprogram" contains quences illustrated in Tables 4-5 through 4-8.

microinstruction

sequences

just like the se-

CU DATA

represents a small read /write

memory work space needed

by the Control

Unit.

What we have

ignored, so far,

around the microprogram

ROM concatenating short

is

the logic which will allow you to pick your

way

microinstruction sequences,into any

macroinstruction's response microprogram:

> MICROPROGRAM

The illustration above arbitrarily shows four separate microinstruction sequences (shaded), which must be executed in order to enable the logical sequence of events required by some undefined macroinstruction. The broken line identifies the order in which macromstruction sequences must
be executed.

Our Control Unit must have microprogram sequencer logic which allowsit to pick its way around the microprogram ROM, as illustrated above by the broken line. Let us look at some of the functions that our Microprogram Sequencer Logic must be
able to perform:
It

MICRO-

PROGRAM
SEQUENCER
LOGIC
a defined
first

must access

microinstruction,

contiguous sequence of microinstructions, beginning with and continuing for- a fixed number of microinstructions:

=-^
Fixed length,

sequence

of

4-45

2)

It

must be able

to

branch to another contiguous microinstruction sequence:

3)

It

must be able

to

branch to

a frequently

access, then return to the point from

used microinstruction sequence, such as branched: which

it

memory

4)

It

must be able
fixed

to continuously re-execute a single microinstruction,

such as a No Operation,

some

number

of times:

Defined
start

>

"n" re-executions of

3E

w'

a single microinstruction

4-46

The Control

Unit, in reality, will

become a microprogram

ROM

and associated

microinstruction sequencing logic:

All

Registers

Status flags.
Shifter

Complementer.
Arithmetic and
n logic

$=t

Buffer Registei

>=*

T
Data In/Out
Control signals
creation logic

1
ROM

n
Microinstruction

Microinstruction
Microinstruction

sequencing

logic

CONTROL UNIT

REGISTERS, ARITHMETIC AND LOGIC UNIT CHIP SLICE Now in practice, it is easier to implement Control signals creation logic as
the Registers, Arithmetic and Logic Unit:

part of

Status llaqs
Shilici

Registers.

Complementer
Arithmetic

and

s=s
*
*

Arithmetic

and Logic
Unit

Book-.in logic

Buffer Register I

In

/Out

Comroi

stgrtate
li-.(]ic

cif.-jlicn

r
ROM

Jl.
Microinstruction

Microinstruction

sequencing logic
Microinstruction

CONTROL UNIT

We

will

begin our discussion of chip

will slice

slice

products with the Registers, Arithmetic and Logic

Unit,

which

we

up

into

segments.

4-47

up this logic, it is imperative that we place as few restrictions as possible on the number and organization of registers. Also, we cannot limit CPU word size; even though we talk consistently about 8-bit microcomputers, it would be very short sighted to assume that an 8-bit word size is going to last forever. Within the microcomputer inIn dividing dustry you measure "ever"

wili therefore slice up our registers, in months, not years. arithmetic and logic unit into identical vertical slices, such that slices may be stacked to form a CPU with any word size:

We

2-bit

CPU

We

will refer to

each
size

slice as

an

ALU

slice.

ALU SLICE
is

2-bit

ALU

slices

and 4-bit
is

ALU

slices are

commonly seen. So
superior, since
it

long as your

word

a multiple of 4, the 4-bit slice

requires

fewer

chips.

registers and ALU logic is to be sliced up, each slice must be able to interface If the combined with an identical neighbor on either side, in addition to a Control Unit.

organization, such as illustrated in Figure 4-1, presents a lot of problems. The innumerable data paths converging on the Data Bus are going, to become even they are to be general purpose, cannot be predefined or more complex, since the registers, to idenlimited in number, as shown. You would have to construct impractical microinstructions

Any simple ALU

if

tify

ALU

the innumerable valid data path combinations. Therefore we will reorganize our registers and sucwith an eye to streamlining the data paths, while maintaining flexibility. Remember, a end product. cessful chip slice makes no assumptions regarding the architecture of the

Now
the

there are a very large

number

of microprocessor-based

microcomputers on the market and

slice products.

number

constantly increases; but there are very

few chip

Therefore

we

will

reorganize the registers and ALU portion of Figure 4-1 to generally conform with the organization of 2900 and 6700 series 4-bit chip slice products which are described in Volume II. Figure 4-3 illustrates this reorganization. 3000 series 2-bit chip slice prosimilar, and represent the predecessor of 2900 and 6700 series pro10800 chip slice products represent the next generation the logical evolution of 2900 and 6700 series products.

ducts are conceptually very

ducts.

Figure 4-4 illustrates the concept of a "chip slice"; the figure

8-bit

shows two

>

-bit slices

creating an

ALU.
in

Let us look at Figure 4-3

overview.

must be specified within the Registers block. 16 registers are selected, since a 4-bit select code can address one of the 16 registers.
of
registers

Some

fixed

number

REGISTER

BLOCK

The Registers block has two output ports. AA and BB, plus one input port, ZZ. Having three ports, the register block needs three sets of register select logic one for each port. Select logic identifies the register which is effectively connected to each port at any point in time. can get by with two sets of register select logic by combining input ZZ select logic with either output port

We

AA

or

BB

select logic.

We

will arbitrarily

choose

to

combine ZZ and BB

select logic. This

means

any point in time the same both the ZZ and BB ports.

that at

register in the register block will

be effectively connected to

Thus the chip slice DIP needs four register select pins:

port register select pins and four B port

Select -Register
for Port

A0
A1

A2

A3
BZ0
BZ1

Select Register
for Port

B or Z

BZ2

BZ3

4-BIT

ALU SLICE

Now

and the

ALU block. The ALU block requires two input ALU operations require two inputs
PP can receive
a

consider the data paths between the Register's block

ports,

DATA PATHS

to create one output.

marked PP and QQ, since a number of RR marks the output.

Input port
register.

XX marks

Registers block output AA or BB, or it can receive contents of the Buffer three-way junction whence input PP is derived.

Input port

QQ

can receive either Registers block BB output, or external data.

way

junction

whence

the

QQ

YY marks

the two-

input

is

derived.

4-49

terface

Let us examine the external signals that will be required to support the inbetween the register and ALU blocks. If we assume that an addiis

ALU INPUT
IDENTIFIED

tional option

to input

at ports

PP

or

QQ
BB

then the following input

combinations are allowed:

QQ:
PP:

BB

AA
as
-

BB

VV
it.

AA

BB BB

BB

Dl

Dl

Dl

Dl

VV

AA

BB

VV

BB

is

the

same

BB, so ignore

Since AA and BB can have the same value, ignore BB - BB which can be AA; ignore Dl -BB which can be made equivalent to Dl -AA.
-

made

equivalent to

BB

is

ignored since an

ALU

operation

will

never require two

inputs.

We will

use three input pins to identify the remaining eight possible PP-QQ input combinations. These three input pins will become the low order three bits of a 9bit microinstruction code and will be interpreted as shown in Table 4-9.

DATA
4-bit

IN

wide

16 x 4-bits of

unassigned
Register Block

wide Complementer, Addition and Boolean logic (ALU Block)

4-bit

4-bit

wide

shifter

4-bit

wide

Buffer Register

Figure 4-3. Register. Arithmetic

And
Slice

Logic Unit

From

Figure 4-1, Reorganized

To Meet

The Needs Of A Chip

4-50

Table 4-9.

ALU Sources As Defined By The Low Order Three Microinstruction Bits

MICROINSTRUCTION
12
11

ALU INPUTS

|0

QQ
BB BB 00 00 00

PP
vv

AA
VV

o
1

AA
BB BB

DD DD DD
Bits 0,1,2.3

VV
00

Concatenated
chip slices

Bits 4,5,6.7

Bits 0.1,2.3

Bits 4,5,6,7

Figure 4-4.

Two

4-Bit

ALU

Slices
8-Bit

Concatenated

To Generate An
4-51

ALU

The Registers block-ALU

interface also requires four data data input to YY. Our DIP therefore looks like this:

in

pins supporting the

AO
A1

DIO

Select Register
for Port

DM
DI2 DI3

A
f

A2

Data

in

A3
BZO
BZ1

<

Select Register
for Port

B or Z
j

BZ2

BZ3
10

Select

ALU

inputs
1

II

4-BIT

12

ALU

SLICE

Now move

on

to the Arithmetic

and Logic

Unit.

CHIP SLICE
leaving behind comple-

Notice that the shifter has been

moved

ARITHMETIC

out,

menter, addition and Boolean

logic.

Moving

shifter logic

out allows the

AND LOGIC
UNIT

option of shifting data within a short recycle path through the Buffer
register
its

(RRSSUUVVXXPP)

or

we

can

shift a final

ALU

operation result on

way back

to the Registers block

(RRSSTTZZ).
it

The Buffer
quires

register in Figure

4-3 does not serve the same purpose that

did

in

Figure 4-1.

In

Figure 4-1 the Buffer register provides the second

two inputs. In Figure 4-3 the ALU inputs PP and Q'Q. In Figure 4-3, the Buffer register has become
results of

ALU input whenever an ALU operation recome from the two Registers block output ports
a holding location for intermediate

ALU

operations.

We

CHIP SLICE will assign the next three bits of the microinstruction ALU OPERATION code (13, 14, 15) to define the ALU operations which are to IDENTIFICATION be performed. There are only five isolated operations: ADD, COMPLEMENT, AND, OR, XOR. We could add increment and decrement to the list; instead we generate the equivalent by providing an external carry
in:

4-bit

wide Complementer,
Block)

Addition and Boolean logic

(ALU

Output RR

results

from inputs PP,

QQ

and Carry

in.

4-52

Combining the two

input, options with the carry

illustrated' in

in

and the

five

ALU

operations allows us to

generate the ALU. operation codes

Table 4-10.

Our 4-bit ALU

slice

DIP

will

need three more microinstruction inputs, plus a Carry

A0
010
DI1

Select Register
for Port

A1

A2

DI2

Data

in

A3
BZO

DI3
CI

Carry

in

Select Register
for Port

BZ1

B or Z

BZ2 BZ3
10

Select

ALU

inputs
-J

11

12

4-BIT

Define

*"
(

13 14
15

ALU

SLICE

ALU

Operation

Only the ALU destination remains to be specified; three microcode bits for this specification.

we will

use

CHIP SLICE

ALU
block out-

These are the three possible destinations

put
1)
:

for

ALU

DESTINATION

2) 3)

The The

Buffer register, via

Registers block, via SS,

via

SS and UU. TT and Zl

Data out.
its

SS and TT.

Data on

way

to the Buffer register or the Registers block

may

optionally be shifted

loft

or right
all

bewildering variety of output options could be selected since data can be output to any or

of

Table 4-10.

ALU

Operations Specified By Middle Three Microcode

Bits

MICROCODE
15

FUNCTION
General
Carry In =

14

13

Carry

In

=
-

QQ

PP

QQ
PP
if

PP

QQ
is <s

PP

QQ
PP

Increment PP

i'

QQ =
;

QQ
1

if

Increment
1
if

DD

PP

QQ
iPP

(PPi

QQ
QQ
is

PP

PP

QQ
if

is

the

Ones complement PP

Tvvos complement PP

ones complement
of PPi
1

QQ
in

is

QQ OR PP QQ AND PP QQ XOR PP
1

Carry

plays no part

in

Boolean operations

currently

|
1
1

unassigned

4-53

three destinations, with shifting occuring along

a chip slice product quite extensively,
useful.
it

two

of the destination paths. Until you have used

will

not be clear which of the output path options are

Table 4-11.

ALU

Destinations Specified By

Last Three Microcode Bits

BUFFER REGISTER
18 17 16

REGISTER BLOCK
Data Out
Shift

Shift

No
1

Left

Right
1

Yes Yes Yes

No No No No
No
Yes

No No No No No
Left

Right

No

Yes Yes Yes Yes

Yes Yes Yes Yes Yes Yes Yes Yes

Bear

the temporary data in mind that we really have two types of ALU output which is heading for the Buffer register and permanent answers which are heading back to the Registers block. Based on this concept. Table 4-1 1 illustrates one way in which destinations could be specified.

The only subject

left

to discuss

is

status.

The Zero, Overflow

let

CHIP SLICE

and Sign status flags are easy to generate, so these three first.
Every chip
slice will

us look at

STATUS
SIGN

be

built

assuming

that

it

can be the high order

slice in

the ALU. Every slice

will

therefore have logic which

bits of

assumes

that the data

STATUS

out lines represent the four high order

high order
line will

the eventual
bit:

ALU

word. The

therefore represent the sign

Sign Status

High order sign

bit

We
will

can generate the sign bit directly from the high order data out line of every single chip slice. Only the high order chip slice's Sign bit will be used; other chip slice sign bits
be ignored.

4-54

The overflow status can be generated from the two high order
lines of

OVERFLOW
STATUS

every chip slice data out, just

line:

as the sign status

was gener-

ated from the high order

Exclusive

OR

of

these two carries

becomes

the

overflow status

^W-^
2,

As described

in

Chapter

the overflow status represents the Exclusive

data word.

OR

of carries out of the

penultimate and ultimate

bits of a

OVERFLOW LOGIC CAN THEREFORE ONLY

BE

GENERATED WITHIN THE ALU.

Generating a zero status is also quite straightforward. For every chip slice we will output NOT OR of the four data out lines:

ZERO STATUS

DO.
Zero Status

DO
By tying the Zero statuses of
status:
all

chip slices within the

CPU

together you can create an overall Zero

etc

Overall Zero Status

Chip
Slrce
1

Chip
Slice 2

etc

4-55

Carry and shift statuses are not nearly so straightforward. First of three sets of statuses: mr*^ Data In

all,

we

need

RS3

BSO

Data Out

But the statuses illustrated above

slices

will

not always work efficiently, since chip

must work

in parallel.
shift,

Consider a simple. 8-bit

created using

two chip

slices:

HRS3

LRS3

Uilt

Ultt
HRSO

Vrm
D7 D6 D5 D4
High order
slice
If

Wm
Low
order
slice

D3 D2 D1 DO LRSO

the shift illustrated above is to occur as a single, parallel must become the high order slice shift in (HRSO).

step, the

low order

slice shift

out (LRS3)

4-56

If LRS3 and HRSO are both connected to DIP pins, these two pins and an 8-bit shift is created:

all

we

have to do

is

connect

HRS3

t t t t t

1*

t t.

\
D7

}) D6 D5
v
slice

D4

r H )))
so

D3 D2 D1

DO

LRSO

High order

Low

order

slice

But

when

it

comes

to binary addition, the problem

shift
is in

is

less straightforward.
is

When
at

shifting,

LRS3

is

created while the

progress.

When

adding, the carry out

generated

the end of the addition.

Here

is

a simplified illustration of this timing problem. For a

shift,

we

have no problem:

CLOCK

D0,D1,D2,D3

LRS3

D4,D5,D6,D7

For binary addition,

we

have a problem:

CLOCK

D0,D1,D2,D3

CARRY

D4.D5.D6.D7

4-57

We

could perform the binary addition

in four-bit
in

increments,
could

starting with the least significant four bits;

and

this case, carry

CARRY STATUS

simply be rippled from one 4-bit

slice to the next:

whole purpose of using chip slice products to gam instruction execution speed. We must therefore add logic which allows the ALU to forecast whether a binary addition is going to create a carry, or propagate one coming in.
But rippling binary addition defeats the

CARRY LOOK AHEAD

The

rules for carry creation

and propagation are simple enough.

If

First consider carry propagation.

tion,

there

is

a carry

in

to binary addi

then there
:

ded

will

be a carry out so long as no two

digits are

being ad

CARRY PROPAGATION

and thus breaking the propagation chain:

Two

digits

10
No
Carry

<
-^

'

Carry

in

propagated

10 10
1 1 1

11
1

Carries propagated

If

Pj

and Qj represents binary

will

digits entering the

if:

ALU

via ports

PP and

QQ

respectively,

we

con

elude that a carry

(P

propagate

OR Q

AND

(P,

OR

Q,)

AND

(P 2

OR Q 2 AND
)

(P 3

OR Q 3 =
)

order to determine whether a new carry will be generated, we must start at the high order end of the 4-bit unit and work back to the low order end. Both high order digits must be one or one high order digit must be with a carry propagated from the penultimate
In
1 1

CARRY GENERATION
digits:

XX X X
--

XX X X
--

XX---

XX--

Oxx
1>

Oxx
0*
1

Carry:

1>
1

0*

If

C,

represents the carry out of

bit

position
))

i,

then

if

C,

1.

generating a carry,

(P 3

AND Q 3 OR
)

(C 2

AND

(P 2

OR Q 2 =

For

C2

to

1.'

the
)

same

relationship applies, with

(P,

bit

positions shifted

down:

(P 2
In this

AND Q 2 OR (C, AND

fashion the

OR

Q,))

ALU

can be provided with logic that predicts a carry generation.

4-58

Finally, this is

the

way

pins

must be assigned:
DIP

-<

>
I

Select Register
for Port

Dll

DI2 DI3

Data

in

<

J
-Carry
in

Select Register
for Port

B or Z

-Carry -Carry

out

generated
in

--Carry propagated
Select

ALU

inputs

cz
^

Buffer shifter carry

4-BIT

-Buffer

shifter carry

out
in

ALU

SLICE
poo
DPI

Registers shifter carry

Define

-Registers

ALU
Select

Operatio

-c

"!
J

shifter carry out

ALU

Destination

D02 D03

Data out
|

Power Ground
Clock

slices;

Zero status Overflow status

Sign status

Carry generate logic will usually be provided on a separate carry generate device. This device receives Carry Propagate (P) and Carry
Generate (G) signals, in the proper sequence, from the 4-bit generates and returns the correct Carry in (C) to each chip

CARRY GENERATE
DEVICE

ALU
slice:

it

ALU
3

c;

ALU
2

C2

ALU

C!

ALU

G 2>

P2

'

G '1

ph

P3
Carry Look

GO
Ahead

W
G3

^PO

THE CHIP SLICE CONTROL UNIT

The ALU
tion,

slices, as we have described them, are driven by a 9-bit microinstructogether with binary data input and various status/control signals.

The control

unit

must provide the

9-bit microinstruction code;

it

it

could also provide

the input status /control signals but typically

does
in

not, tor

reasons

we

wilf

soon discuss.

We

are going to store the microinstruction

code

a very fast Read Only

in

dressing logic which accesses microinstructions

the proper sequence.

Memory and create adThe Control Unit

logic,

then consists of the microinstructions

earlier in this chapter.

ROM

and

its

addressing

as discussed

We

can gain a

lot of insight into

desirable Control Unit addressing iogic features by looking back

4-59

at the

microprocessor microinstruction sequences which were developed

in

Tables 4-5 through

4-8.

quentially Therefore,

Under normal circumstances microinstruction codes are accessed sethe Control Unit addressing logic must have a Microprogram Counter (MPC), the equivalent of a Program Counter which can be incremented after every microprogram access to
reference the next sequential microinstruction:

MICRO-

PROGRAM
COUNTER

nn ^

MPC
D11
rf

Incrementing
Logic

We arbitrarily assume a
a

2-bit

width
in

for the Control Unit address logic

the

implying

maximum

of

4096 in microinstructions

ROM.

Any microinstruction sequence is going to begin at some initial address; therefore Control Unit addressing logic must be able to initialize the Microprogram Counter. Consider two
possibilities:
1)

Every macroinstruction object code is going to be implemented by a microinstruction sequence with its own initial address which must be loaded into the Microprogram Counter. We will therefore provide direct data access to the Microprogram Counter:

^ mi ^
2)
It

nn

MPC

Incrementer
Logic

would be

highly desirable to have

some

general purpose microprogram origins to handle

special circumstances, or alarm conditions that

individual instruction.

may have

nothing to do with execution of an

We
w

will therefore provide a register

where some

such per-

manent address may be

DO
D11

stored:
Incrementer
Logic

MPC
t

R0 Keg
Rii
fe.

Recall that the Control Unit addressing logic

of times. In
trol

must be able

to re-execute

one

instruction a

number

our example, a "No Operation" instruction was re-executed simply to keep the Conwill therefore add an increment inhibit Unit synchronized with external timing.

We

control to the Microprogram Counter:

DO

MPC
D11
> .

Incrementer
Logic

R0
R11
Finally,

Increment
Inhibit

recall that there are frequently used microinstruction sequences which perform operations such as memory read or memory write. We can handle this situation in
of

one

two ways.
4-60

First

consider having a

number
-

of address registers plus a

Microprogram Counter

Buffer:

MPC Buffer
nn
D11

^
w

t
MPC
Incrementer
Logic

<
Register

A
A

no
=

A
Increment
Inhibit

Register B
E =

Register
E =
.

As
logic

illustrated

above,

the

address

of

the
in

first

microinstruction
B,

for

four

frequently

used

mrcroinstruction sequences

may be

stored
in

Registers A,

C and

can save

prior

contents of

MPC

the Buffer, then load

The Control Unit addressing the contents of one register:

D.

MPC
<

Buffer
\

\
}
Incrementer
Logic

DO-^-..

MPC
D1
i

s J "

<
i

7'
'

RO

Register

The
last

Register B

/
i

Increment
Inhibit

Register

microinstruction

in

the frequently used sequence causes the Buffer contents to be

MPC
i

Buffer
i

nn^
mi M
Register
= =

MPC
i

^ ' *J

Incrementer
Logic

1
Increment
Inhibit

Register B

Register
.

4-61

Another approach requires

Microprogram Counter:

external logic to provide the starting address of each frequently

In this

used microinstruction sequence.

case,

a stack of Buffer registers

will

back up the

Buffer

Stack

The

access another frebuffer stack allows one frequently used microinstruction sequence to is a common quently used microinstruction sequence. This is sequence nesting. The stack microcomputer feature and is described in Chapter 6.
This
tion
1)
is

how

the Buffer stack

B.

would work

for microinstruction

sequence

A
C:

accessing microinstruc-

sequence

which

in turn,

accesses microinstruction sequence

Microinstruction

sequence

accessed. The current sequence

dress
is

reaches the point where microinstruction sequence B must be A address is saved on the stack, then the sequence B adBuffer

input:

Stack

Address

X /
Incrementer
Logic

Starting

address

MPC

Register

Increment
Inhibit

4-62

2)

Microinstruction

sequence B reaches the point where microinstruction sequence C must be

1

accessed. Step

is

repeated:
Buffer

Stack

Address B Address

N s
-*

Starting

address

DO

*-

<
[D11 -

MPC

Incrementer
Loaic

*J

RO
R11

>
Register

Increment
Inhibit

>
C completes
execution, so the saved Address B
is

3)

Microinstruction sequence

returned to

MPC:
Buffer

Stack

N
Address B

Address

DO

*
*

MPC

Incrementer
Logic

D11-*
RO
R11

*-

>
Register
*>

Increment
Inhibit

4-63

4)

Microinstruction

sequence

B.

in

turn,

completes execution, so the saved Address

is

returned to

MPC:

Buffer

Stack

Address B

Address A(

y
1++
Incrementer
Logic

DO-*-

MPC

Register

Increment
Inhibit

additional control signals will be needed: one will push the contents of MPC into the stack, as illustrated in Steps 1 and 2, the other will pop the top stack address into MPC, as illustrated in Steps 3 and 4. Our Control Unit address logic DIP pin assignments will now be as follows:

Assuming

that our Control Unit addressing logic has a Buffer stack,

two

RO

Ground
Clock

^, ^.
DO
Dl

R1

R2 R3 R4 R5 R6
R7

D2 D3

Register
Input

D4
snal

D5
<

R8

dress

D6 D7 D8 D9

R9
.R10

Bus

R11

D10
D11
Inhibit

._

Push

Pop

>.

4-64

COMBINING ARITHMETIC AND LOGIC UNIT WITH CONTROL

UNIT
Conceptually

slices

we are going to build a Central Processing Unit by combining ALU with Control Unit addressing logic and a microprogram in Read Only
as follows:

Memory

ALU

Slices

Control Unit

Microprogram

Address Logic

ROM

a very considerable amount of additional external logic will be required before the simple configuration illustrated above can perform as a Central Processing Unit. For example, nowhere have we addressed the problem of receiving or transmitting control signals. What about the microprocessor Read and Write
In practice

control signals?

would have been possible to add logic to the Control Unit that automatically senses and creates CPU-type control signals. However, that assumes chip slice products are going to be used as CPU building blocks only. The assumption is unwarranted.
It

By describing chip

slice

products

in

Chapter

4.

a chapter

cast chip slice products as

CPU

building blocks,
in

devoted to Central Processing Units, we which makes them conceptually easy to undersis

tand only because of the sequence

.

which information

being presented
Control Unit
set. But.

in this

book.

Excluding control signal processing logic from the chip

slice

work and

extra logic

restrictions are

must surround the chip slice and Control Unit imposed on the way these products are used.

means a lot of extra at the same time, no

In terms of our current discussion, therefore, we must conclude without demonstrating the equivalent of an instruction fetch or a typical instruction's execution,

because the type of information which would have to be covered before necessary external logic could be adequately treated is beyond the scope of this book.

4-65

Chapter 5 LOGIC BEYOND THE CPU

In this

CPU

in

chapter we are going to identify the additional logic that must accompany a order to generate a microcomputer system that is comprehensive enough to

be useful.

We

must separately identify the logical components of a microcomputer system (e.g., CPU, RAM memory, ROM memory, etc.) but there is no fundamentally necessary correlation between logical components and individual chips. As you will see in Volume II, there can be wide variations between the type of logic which one microcomputer manufacturer will put on a single chip, as comby function
pared to another.

PROGRAM AND DATA MEMORY

External memory is the first and most obvious addition needed to support the that was described in Chapter 4.

CPU

READ-ONLY MEMORY (ROM)

Interfacing

ROM
in

to a

CPU
3,

is

very simple.
words
of

As described
word.

Chapter

entire

memory

are

implemented on

a single
bit

ROM

chip.

By

contrast, read-write

memory (RAM) may

require a separate chip for every

of the

memory

The
1)

signals required by a

ROM

expect, a

ROM

device
of the

will require

device are quite elementary. As one would logically the following input signals:
being accessed.

The address

memory word
tells

2)

read control signal which

the

ROM

device

when

to return the contents of the ad-

dressed
3) 4)

memory word.

clock signal so that the

ROM

and CPU

will

be synchronized.

Power and ground.

signals which the ROM device must have are eight data lines (for an which the contents of the addressed memory word may be transferred back to the CPU. Figure 5-1 illustrates a hypothetical ROM device. This ROM device is connected to the CPU as illustrated in Figure 5-2.

The only output

8-bit word), via

Before describing a ROM access in detail, let us consider features of a microcomputer system.

some

of the non-obvious

Were

CPU and one ROM. EXTERNAL two devices could be directly connected. Since it must be DATA BUS possible for more than two devices to be present in a microcomputer system, signal connections are made via an External Data Bus, which may be likened to a common signal highway connecting chips of the microcomputer set.
a microcomputer system to consist of just the
pins from the

5-1

(Vdd
Vss

AO
A1

2 3

Vgg
Clock $
'

A2 A3

DO
D1

A4 A5
A6
A7 A8

>-

Address Select

D2

D3
Data
-<

D4
D5

A9
SO
S1

D6
D7

READ

S2
> Chip Select.

S3

S4
S5

Figure 5-1.

Read-Only

Memory

Chip Pins and Signals

Notice that the 16 address signals of the CPU become ten ROM DEVICE signals and six device select signals at the SELECT ROM. This distribution of the address lines implies that the ROM has 1024 (2 10 words of memory, and a 6-bit select code. Providing the high order six address lines coincide with the 6-bit device code of the ROM, the ROM will decode the

word address

low order ten address

lines as representing
true,
If

one

of

its

1024 memory words. Then,

contents of the addressed

READ

control signal

at the data pins

DO

D7.
will

goes

ROM

logic will place the

when the memory word

the six high order address lines do not coincide with the

ROM

select

code, then the

ROM

ignore current events.

Frequently a ROM chip will have no chip select logic; then there will be a single chip select signal, which must be generated by external logic. It is also very common for a ROM device to have two select inputs. For the ROM to be selected, one input must be low while the other input is simultaneously high.
If

the

ROM

chip has
If,

its

own

chip design.

for

example, a
into the

have been burned

code is a permanent feature of the ROM ROM chip has the select code 001 100, then this select code will ROM chip when was created, with the result that the ROM chip will
select logic, then the select
it
:

respond only to

memory addresses 3000i6 through 33FF 16

Select

Code
,

Lowest memory address

V /

001

1000000000000
Highest

Select

Code

memory

address

110
3 3

1111111111
F F

5-2

S
<<<<<<<<<<wSmo)woi

<h*
<Hfr

<Mt
^^+^

OOQQQQQQ>

cr

>>> w <<<<<<<<<<<5<<<
~o
</)

en

H*-

P o5>
t,

a>

en

5-3

In

other words, a

ROM
is

chip with one device select code must be looked upon as differing from

an identical
If

ROM

with a different device select code.

external to the

device select logic

ROM

chip,

then the device select code

will

feature of the

ROM; merely
illustrated

modifying the external device select logic

is not a permanent change the range of

addresses within which the

logic

ROM

device responds to

memory

accesses. External device select

may be

as follows:

A1

A? A3 A4 AR
Afi

Word
Address

Memory Address
w.

Memory
Address from CPU

A7 AR A9

to

ROM

Device

w.

A10
A11 A1?
n-of.-64

w Select
Select

.Device
Select

w Select 2.
>.,

A13 A14
AlfS

Logic
Select n.

Device selects to other ROM and /or RAM devices

is internal to a ROM chip will never be of any concern to you, as a microcomputer user. The way in which the ROM chip selects or deselects itself, the way in which responds to read control signals, the way in which extracts necessary data and places the data at pins DO D7. are all completely irrelevant since there is nothing you can do about

Logic that
it

it

it.

Consider a
in

memory
4,

read instruction; timing for this instruction

is

reproduced here, as
it

it

appeared

Chapter

but with the keying symbols

(/y and (b)

to link

to Figure 5-2.

AO

to

A15

INSTRUCTION

DATA
ADDRESS

ADDRESS

INSr

CODE

DO

to

D7
Instruction

Data
Fetch

Fetch

Memory Read
Instruction

5-4

Recall that so far as logic external to the

CPU

is

concerned, there

is

no difference between an

instruction fetch operation or a data fetch operation.

<& rising (at at this time the CPU outputs an address on the and at the same time sets READ high. The ROM receives these signals via the External System Bus. If the high order six address lines (A 10 A 15) coincide with the ROM select code (SO - S5), then the ROM chip logic fetches the contents of the memory word addressed by
);

Each operation begins with clock

lines,

address

A0

A9, and places

<t>
-

this

data at

DO

D7.
),

By the time
data on

DO

goes low and READ goes low (at (B) D7; data must stay on these lines until

ROM
<J>

logic must have placed the requested goes high again.

RAM logic must System Bus and place this data in an addressed memory word; in addition, RAM logic must be able to extract data from an addressed memory word and place this data on the External System Bus data lines. Also, most RAM is implemented using a number of RAM chips, with each chip supplying one or more bits of the data word.
than

READ-WRITE MEMORY (RAM) RAM interface logic is more complex

be able to take data

ROM

interface logic.

off the data lines of the External

Using a number of chips to support a single data word

is

a simple

enough concept;

it

means

that

each chip
lines,

will

only have

one data

pin.

and

this pin will

be connected to one of the eight data

DO

D7.
for

As described
select

ROM,

RAM

interface logic will partition the address lines

A0

A15

into a

device

code and a memory address. However, there may be eight RAM chips (for an 8-bit word), each of which has the same device select code, but is connected to a different data line on the External System Bus. Figure 5-3 illustrates a single RAM chip with on-chip device select logic, and Figure 5-4 shows one way in which RAM memory may be added to the ROM-CPU
combination
illustrated in Figure 5-2.

Vdd Vgg
(J)

A0
A1

Power and ground < Vss

*

3 4

A2

___^. clock
-

A3 A4
A5 A6
A7
Address Select

Data

A8 A9
SO
S1

_^

READ

S2
Chip Select.

.^WRITE

S3

S4
S5
Read-Write
special

Figure 5-3.

Memory Chip

Pins

And

Signals

Some microcomputers have

refresh dynamic

RAM

interface logic devices.

These devices may

and/or provide device select logic. The Fairchild F8 needs special RAM interface devices because of its unique logic distribution. Figure 5-5 illustrates RAM controlled by a RAM interface device.
5-5

RAM

Q-

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<

o m

cc

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3 o

10

T3

5-6

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is
5 o CC

SgsKsas

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Q Q O ^

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<

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1

<

<

<
f

i'

Q S s

o:

r> Q_

II

>

&c <
f

< < <

<

< < < < <

<(

< < < < <

1 T
< <
4.

.1

< < <

<

;?ssasss
u
<cc
CC LU \-

> >

>

c2

Q Q Q

SSoMSS ssss
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<

<
1

r ST 2 5 2 5 < < < <

< <

o 2 3 4 5
RAM RAM RAM

III

RAM
:
:

ra

E ^

5-7

TRANSFERRING DATA BEYOND THE MICROCOMPUTER SYSTEM

(INPUT/OUTPUT)
The
transfer of data
is

between

logic that is part of the

is

microcomputer system and

logic that

beyond the microcomputer system

generally referred to as In-

put/Output

(I/O).

We
in

system,

boundary of the microcomputer been specifically designed to operate conjunction with the CPU. We will classify all other logic as
will

include, within the

logic that has

MICRO-

all

external.

COMPUTER SYSTEM BOUNDS

The interface between the microcomputer system and external logic must be clearly defined; it must contain provisions for transfer of data, plus control signals
that identify events as they occur.

There are many ways in which data transfer between the microcomputer system and external logic can be accomplished; but they all fall into the following three categories:
1)

PROGRAMMED

I/O.

In this

case,

all

data transfers between the microcomputer system

or,

and external logic are completely controlled by the microcomputer program being executed by the microcomputer CPU.
There
will

more

precisely,

by a

be some well defined protocol whereby the microcomputer system gives

evi-

been placed in a location where external logic can access or, alternatively, the microcomputer system will indicate in some predefined way that it is waiting for external logic to place data in some predefined location from which it can be input to the microcomputer system.

dence
it:

that data being output has

The key
2)

characteristic of

programmed I/O

is

that external logic

does as

it

is

told.

INTERRUPT
nal logic.

I/O. Interrupts are a

it

means

for external logic to force the

in

microcomputer

system to suspend whatever

is

currently doing

order to attend to the needs of the exter-

3)

DIRECT

MEMORY ACCESS.

This

is

form

of data transfer

which allows data

to

move
data

between microcomputer memory and

transfer logic.

external devices without involving the

CPU

in

The

physical requirements for each type of I/O will be described

in turn.

PROGRAMMED
Data are transferred between a either direction, via an I/O port.

I/O
logic, in

microcomputer system and external

5-8

An I/O port will consist of an I/O Port Buffer, connected to the data lines of the External System Bus and to pins which access external logic:

I/O

PORTS

CO ^ Other
/Control

CN

; Lines

WRITE

READ
<

>

D7

Data

AO

f Lines
)

\ Address

^5/ Lmes

LU
LILI-

CO

When

external logic transmits data to the

microcomputer system,
in

it

does so by presenting the

data at the I/O port pins,

whence

the data are stored

the I/O buffer.

The

binary value

001001

10 would be transmitted as follows:

DO
D1

D2 D3 D4 D5 D6 D7
I/O Pins

Data Lines

- .*

<
-*

.4

From

external logic

<
-

^
I/O Port Buffer

The I/O Port Buffer cannot be constantly communicating with the data lines of the External System Bus, as illustrated above, since the data lines of the External System Bus may be carrying data to or from memory. If the I/O port were permanently communicating with the data lines of the External System Bus, then every time external logic presented data at the l/O'pins. this data would be propagated down the shared data lines with unpredictable consequences. The microcomputer CPU will therefore select an I/O port and read the contents of the I/O Port Buffer, in much the same way as data gets read out of memory. This parallel between reading data out of I/O Port Buffers and reading data out of memory is appropriate, since most microcomputer systems transfer a great deal of data to and from external logic; therefore, they have more than one I/O port.

5-9

We

can develop a parallel I/O device with one or more I/O where the I/O Port Buffers have addresses, just as memory words have addresses. A simple scheme would be to take
ports,
line
is 0,

PORTS ADDRESSED
I/O

USING

the high order address

that

(A15) and design microcomputer logic such

a

MEMORY
ADDRESS

LINES ~ ~~ ~~" memory addresses of 7FFF 16 and below will access memory words, whereas memory addresses of 8000 16 and above will access I/O Port Buffers. Using the READ and WRITE control lines, Figure 5-6
this line
is

whenever
is
1,

memory module
is

selected, but

whenever

this line

an I/O Port Buffer

selected.

In

other words,

~~

il-

lustrates a parallel I/O device with

one

port.

Vdd
Power and ground
Vss

DO
D1

Vgg
..clock

3 4

D2 D3

A0
A1

D4
D5
D6
D7
,

Data^_

-Microcomputer

System

A2 A3

A4 A5
A6
Address

W
R

WRITE

READ

I/O0
1/01

A7

JA 15 must
1

be

A8 A9 A10
A11

I/02

to select)

I/03

>l/0 Por
I/04 I/05 1/06
1/07

A12 A13 A14

A15
Figure 5-6.

Single Port, Parallel I/O Interface Device

The device

in

Figure 5-6

is

referred to as a parallel I/O device

because data

is

written and read

in

eight, simultaneous, parallel binary units.

I/O device should have only one I/O port. The is purely a function of the number of pins that are economically available on a dual in-line package. The device illustrated in
is

Note that there

no reason

why an

number

of I/O ports that a parallel I/O device has

pins as follows:

Figure 5-6 uses

1)

its

Sixteen pins are connected to the address lines of the External System Bus and provide the information needed to determine if this I/O Port Buffer has been selected.

2)

System Bus and are used to transfer information from the External System Bus to the I/O Port Buffer, or from the I/O Port Buffer to the External System Bus.

Eight pins are connected to the data lines of the External

3)

Two

control lines,

READ and WRITE,

System Bus

Buffer to the External

(read), or

determine whether data will flow from the I/O Port from the External System Bus to the I/O Port

Buffer (write).

5-10

4) 5)

Three pins are required

for

power and ground.

One

pin

is

required for the clock signal.

pins,

That sums to 30
I/O device

which only leaves ten pins

available for I/O ports. Therefore, the parallel

port.
parallel

illustrated in Figure

5-6 can only support one I/O

There
15
)

is.

of course,

an obvious way to increase the number of I/O ports on our

is

I/O

device. Having 16 address lines implies that the microcomputer system

(2

going to address 32768

I/O ports and that

is

unlikely.

about reducing the number of address lines to ten? Now 16 pins are available for I/O ports and our parallel I/O device can have two I/O ports, as illustrated in
Figure 5-7.

How

Powe ,(

Vdd
Vss

Vgg
<D

Ground
Clock
_

A0
A1

I/O0
1/01

A2

I/02

A3
I/O Port Address <

I/03

I/O
I/04

Port

A4 A5 A6 A7 A8
I/O Ports Selected

I/05 I/06

PARALLEL
I/O

I/07

External

INTERFACE

I/08

Devices

A15
DO
D1

I/09

I/O10
1/011

>l/0 Port B

D2
Microcomputer _^__^ Data System
<

1/012 1/013 1/014 1/015

D3
D4 D5

D6
D7
Figure 5-7.

W
R
Parallel

WRITE.

READ-

Two-Port,

I/O Interface Chip

The ten address

1)

lines in Figure

5-7

will

be divided as follows:

One

of the ten

address

lines will

be

A 15,

since this line must be

in

order to select an I/O

port rather than a

2)

memory word,

The remaining nine address

if

Address

lines

AO

A8

lines

may be any

nine of the other

5 address lines. For example,

will select

are connected, then addresses

8000 16 through 81FF 16

I/O ports'

A9-A14
are ignored

A0-A8 maximum value

A15 must
be
1

000000 '111111111

In

the unlikely event that this arrangement provides insufficient I/O port addresses, address lines

A9-A14

could be included as part of the address transmitted to another

parallel

I/O device.

The penalty
Buffers,
is
In

paid,

when

that only 32768

the high order address line (A15) is used to select I/O Port 1B rather than 65536 (2 16 words of memory can be ad(2
),
)

dressed.

the world of minicomputers, this reduction of addressable

memory can be

a severe

price to pay, just to simplify I/O Port Buffer selection. In

the world of microcomputers, the

penalty

is

not very significant, since very

of addressable

memory

(or

few microcomputers require 32768 words anywhere close to that much memory). Typically, a
between 1024 and 4096 words
of

microcomputer application

will

require a total of

memory.

Nevertheless, many microcomputer systems use separate addressing logic to select I/O ports. Figure 5 8 illustrates one possible scheme which adds two control lines to the microcomputer CPU. One
control
line,

I/O PORT ADDRESSES

IOSEL, specifies that address lines

if

AO

A7

contain the I/O Port Buffer select code.

The other control line, IORW, high, indicates that the External Data Bus lines contain information which must be read into the I/O Port Buffer. If IORW is low, then the selected I/O Port Buffer contents must be output to the data lines of the External Data Bus.

just

As you will discover in Chapter 7, the two methods we have described for selecting I/O ports are two out of a bewildering array of possibilities. These two methods do, however, broadly cover the most common ways in which I/O ports are addressed.

ternal

Unfortunately, the blind transfer of data between a microcomputer system and exlogic will not always provide sufficient I/O capability. The following necessities are missing:
1

The microcomputer system must be able

been placed
in

to

tell

external logic

when

data has

an I/O buffer and is therefore ready to be sampled. Conversely, external logic must have means of indicating to the microcomputer system that it has placed data in an I/O buffer and the data can now be read.
2)

The microcomputer system, and external logic, must each have some way of informing the other as to the nature of the data placed in an I/O buffer. Clearly data being transferred between the microcomputer system and external logic is subject to various
interpretations. For example,
it

may be

pure numeric data; but on the other hand

It

it

may be

code
all

identifying operations to

be performed, or already accomplished.

may

also be part, or

of

an address.

When

the microcomputer outputs signals to external logic as a I/O CONTROL means of identifying events or data, these signals are referred to as I/O controls. The same information travelling in the opposite direction, that is from external logic to the microcomputer, is referred to as I/O status. The differentia tion of information into controls and status, based upon the direction of the information, is logical since we are dealing with a situation where the microcomputer is at all
times
in

control of events.

In

other words, the microcomputer outputs

I/O

STATUS
interpret

controls to control external logic sequences. External logic cannot control

the microcomputer; and how sees fit.

it

it

can only input status information

for the

microcomputer to

when

Minicomputer systems will usually have a whole set of I/O control and status lines that are separate and distinct from I/O ports. Microcomputers more commonly allocate one or more I/O ports to function as control and status conduits, while separate I/O ports transfer data.
I/O Port A in Figure 5-8 might be used to transfer data, while I/O Port B is used to transfer control and status information. So far as the microcomputer system is concerned, the same instruction sequences are used to handle data flow through either I/O port. It is the way the microcomputer system interprets a data word that determines whether the word is data, control or status information.

5-12

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IORW

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5-13

INTERRUPT
Most microcomputer CPUs have a control

I/O

which external logic can demand the attention of the microcomputer system. This signal is referred to as an interrupt request signal because, in effect, the external logic is asking the microcomputer system to interrupt whatever is currently doing in order to service more pressing external logical needs.
signal via
it

We will
is

begin the discussion of interrupts with an example that too simple to be realistic, but contains all the key features of a meaningful application.

THE CONCEPT OF AN INTERRUPT

Suppose a microcomputer system is being used to control the temperature of shower water, as illustrated in Figure 5-9. A thermometer measures the temperature of the mixed hot and cold water issuing from the shower head and transmits this temperature, as a digital signal, to the microcomputer system. The microcomputer system compares this temperature to a set point, which is supplied by an appropriate control. Depending on the difference between the real and desired shower temperature, the microcomputer system outputs data which must be interpreted as a valve control signal, causing the valve to increase or decrease the hot water flow.
There are a number
of reasons

why

this

simple sounding application

is

is,

in reality, far

from simple.

between the time you adjust a shower tap and the time that the water issuing from the shower head changes temperature. For this reason, a non-trivial program will have to be executed by the microcomputer to ensure that it does not attempt to make ridiculous adjustments. We will call this program ADJUST, and illustrate it residing in program memory as follows:

As experience

will

have taught you, there

some

delay

MEMORY
0400
Arbitrarily

*
ADJUST

Start of

Program

selected

memory addresses
073E
Another program,

End

of

Program

called

RECORD,

will

input data from the temperature sensor, correctly in-

terpreting the data to represent temperature

readings.

The
in

only contact
in

between programs
Our memory

RECORD and ADJUST are that ADJUST memory and RECORD will place the data now looks like this:

will
in

anticipate finding data

a certain area of data

correct format,

that required area.

MEMORY

0080
Start of

Program

Data placed
in

data buffer

by

RECORD

End

of

Program

Data read out

of data buffer,
Start of

Program

by

ADJUST
End
of

Program

5-14

MICROCOMPUTER CON [HOLLER

A\JI
:

TEMPERAti.Jflf

TEMPERATURE

SELECT

DATA

IN

figure 5-9.

Microcomputer Controlling The Temperature

of

Shower Water

5-15

The way

the microcomputer system

which shower head temperatures are read and transmitted to is another feature of this problem which is not as straightforward as might appear. It will take approximately half a second
in

HANDLING AN INTERRUPT REQUEST

for

second may not seem

an inexpensive temperature sensor to record a temperature. Half a like very much time, but a microcomputer can execute approximately a

quarter of a million instructions during this time period.

How

is

the microcomputer going to

If

know when
tries to

transmit?

the temperature sensor simply

likely

the temperature sensor has a new value to send data to an I/O port, the microcomputer
reading can easily get lost
in

system

is

very

not to read the temperature.

One

a quarter of a

million instruction executions.

One way of resolving the problem is illustrated in Figure 5-10. step sequence allows the temperature sensor to microcomputer system's attention as follows:
(T)

three-

INTERRUPT

call

the

REQUEST

The temperature sensor transmits an interrupt request signal (IREQ) to the microcomputer system via an External System Bus control line.
The microcomputer system has the choice
rejecting the interrupt request;
it

<D

of accepting or accepts the interrupt re-

INTERRUPT

ACKNOWLEDGE

quest by outputting (IACK) on an External

an interrupt acknowledge signal

System Bus

control

line.

(D

The external device uses the

interrupt

transmit data to I/O Port A. Also, request signal upon receiving an interrupt acknowledge since, clearly once the interrupt request has been serviced, the external device is no longer requesting another interrupt.
Timing
for this three-step

acknowdge signal as an enable signal, to the external device must remove its interrupt

sequence may be

illustrated as follows:

IREQ.

IACK

DATA
Note that although

we

have been

talking

about the external device inputting data

to

the

microcomputer system, data flow could just as easily be in the opposite direction; in fact, there is no reason why any data flow need follow an interrupt. The program executed following an interrupt could, for example, simply output control signals.

The purpose of the interrupt is to tell the microcomputer that it must suspend whatever it is doing, process the data being input, then carry on with its suspended operations. With reference to programs RECORD and ADJUST, this is what happens:
^U
Interrupt requested!

<og ol

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< < < < < < < < <

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ell

5-17

and cause the interrupt request to be sensed by the microcomputer at above. The microcomputer CPU responds by suspending execution of ADJUST, while executing RECORD (to). While RECORD is executing, the data transmitted by the temperature sensor (in Figure 5-10) is read into the microcomputer system, since program
Refer again to Figure 5-10. Steps

RECORD

has been written to anticipate

arrival of this data.

When RECORD

has completed execution

it

at

execution of

ADJUST

continues at

picking

up exactly where

left off

at

The key feature

There
is

is that it is an unscheduled event. microcomputer system that can predict when or how often program RECORD will be executed. However, there is logic within the microcomputer system that can suspend any program's execution, later restarting execution from the exact point of suspension.

of

program RECORD'S execution

no

logic within the

A MICROCOMPUTER'S RESPONSE TO AN INTERRUPT

At
its most elementary level, a microcomputer CPU could respond to an interrupt request by simply loading into the Program Counter the starting address of the program that external, interrupting logic wants executed. But that begs two questions:

1)

What happens

to the program that

was

being executed?
of the

2)

Where does the microcomputer CPU get the address

interrupting logic

program which the

wants executed?
to the

Consider

first

what happens

program that was being executed.

The

program may have important information in the status flags, the Data Counter and Accumulator; this data is going to be wiped out by the new program, so that when the new program has finished executing, the old program will no longer be able to restart. This problem is resolved by
old

SAVING REGISTERS

AND STATUS
starting to

saving the contents of the

all

CPU
the

registers, including the

Program Counter, before

its

execute

new
is

program.

When

new program completes

was about

execution, the saved Program Counter

value

the address of the instruction that

to

be executed

when

the old program

was

interrupted; so, by merely restoring the saved values into the

CPU

registers, the old

program can

pick

up where

it

left off.

This concept

is

illustrated as follows:

Data

Memory
0060
0061

is the situation when ADJUST is interrupted to execute RECORD (registers contents and memory addresses

This

0062
0063
0064
from Status

have been

arbitrarily

selected)

0065

0060
0061

This

is the situation when RECORD has finished executing and ADJUST must con-

0062

tinue

where

it

left off.

0063 0064

(Registers contents are again

arbitrarily selected.)

0065

C[0|S|Z|

to Status

5-18

until the current instruction has completed executing. This no need to save the contents of the Instruction register, since it contains an instruction code which has been processed. In other words, the interrupt directly precedes the

An

interrupt will not

be acknowledged
is

being the case, there

arrival

of a

new

instruction code.

There are two ways

in

which the

old

may be
be
Unit),

saved, as

illustrated

above, before the

program status flags and registers' contents new program starts execution. One way wouid

execution of a microprogram (stored in the Control which simply writes the contents of CPU registers into a data area of memory which has been set aside for this purpose. A microcomputer designer may be reluctant to use up precious Control Unit space in this way, and instead may require the programmer to write a short program which will do the same thing. Such a program is called an "Interrupt Service Routine."
for the interrupt request signal to initiate

At the end of the

new

program's execution, whatever logic was used to

in

save the old program's registers' contents must be executed

restore the old program's registers

reverse, to

and

status.
in

INTERRUPT SERVICE ROUTINE

we
have discussed

We

will

consider Interrupt Service Routines

in

more

detail in

Chapter

6,

after

programming

more

detail.

Now

consider

of the program

We

will refer

the microcomputer CPU gets the address which the interrupting logic wants executed. to this as the Interrupt Address Vector.
of determining

how

INTERRUPT

ADDRESS VECTOR

There are almost as many ways

which program must be executed following an inshower temperature control problem, there is an easy solution. The shower head temperature sensor is the only external device that can request an interrupt, and there is only one program it can want executed following the interrupt. This being the case, the microcomputer CPU could be built with internal logic that causes one program, origined at one specific memory address, to be executed following an
terrupt request as there are microcomputers. In the case of our

intermpt:

ARITHMETIC AND LOGIC UNIT

STATUS FLAGS

r-K

-*c
*
COMPLEMENTER

ACCUMULATOR
DATA COUNTER

PROGRAM COUNTER

h-

INSTRUCTION REG

ADDITION

AND BOOLEAN
LOGIC

INTERRUPT ADDRESS VECTOR

CONTROL UNIT
BUFFER REGISTER

3*H

/
IREQ

/
IACK
it

Now
1)

to service the interrupt,

every time the Control Unit receives an interrupt request (IREQ) and it does as follows:
interrupt

is

ready

Send out the

acknowledge

signal, IACK.

2)

Save the contents of Status Flags, the Accumulator, the Data Counter and the Program Counter, or else allow the programmer some way of doing the same
thing.

5-19

3)

Move the contents

of the Interrupt

Address Vector to the Program Counter.

A minicomputer programmer would consider this method of responding to interrupts as laughably ridiculous. Who knows when and how the minicomputer may next have to respond to an interrupt? To specify that all interrupts will be serviced by a program origined at memory address 0400 16 (for example) would be an intolerable restriction, because it reduces the minicomputer programmer's ability to be flexible.
tain

microcomputer applications, having fixed interrupt address vectors makes a ceramount of sense. Remember that microcomputers are going to be used as logic components, not as general purpose computers. Most microcomputers are used in
In

dedicated, non-varying situations, where one, or a few specific interrupts will require equally specific responses from the microcomputer system.
Figure 5-11 shows how the parallel I/O interface device and the ROM device from Figure 5-8 could be modified to receive the interrupt request signal IREQ. Each device, as modified in Figure 5-11. contains a 16-bit register, in which an interrupt address vector is permanently stored. Upon receiving the interrupt acknowledge signal IACK. the device transmits an
interrupt address vector to the

CPU,

via

the address lines of the External System Bus. After saving

the contents of status flags and

CPU

registers, the

CPU

loads the interrupt address vector into the

Program Counter.

The

Parallel
its

I/O Interface device, only having eight address pins attached to

interrupt address vector to the
will
is

A0

A7.

will

have to

transmit

CPU

in

two
is,

halves;

and the CPU Control Unit

microprogram
Counter. This

have to load each

half appropriately into the

Program

referred to as multiplexing lines, that

using the

bus

lines to carry signals that

must be interpreted

in

different

same ways at

MULTIPLEXED
LINES

different times.

Notice that we have a problem with the Parallel I/O interface device, as illustrated we have run out of pins. IACK has to be input somehow in response to IREQO. The best way of resolving this problem is to replace the address pins A0 A7 with three chip select

pins CO. CI

and C2. That leaves

halves
Vdd

five

unused

pins,

one

of

which can be assigned

to IACK:

Two

of interrupt

address vector.

r^si
100
101

^^ ^
\

CO
CI
\

Select l,0 Port

"^

or B. or

C2

One

half of interrupt

addr

)SS

<

102

IACK

o o

103 104 105 106 107

00
D1

D2

D3
D4

108
109

'010 cr

\
PARALLEL
I/O

D5
D6

O Q_ O

I011

D7
IQSEL

1012

KD13
1014 1015

INTERFACE

^ IURVV IREQO _ IREQ

in

The
First.

Parallel I/O interface

device changes

two

important ways.

CO, CI and C2 will be the product of additional chip select logic, which receives of the external system bus address lines as inputs.

some

or

all

5-20

Second, the data bus the CPU.

is

now

multiplexed: at different times

it

may

transmit data or an address to

ception

Having external chip select logic is the rule rather than the examong real microcomputer support devices. In reality,
in

SELECTING I/O DEVICES

of

the external select logic frequently does not exist. Since there are very

few I/O devices

a typical

you could create CO as the

microcomputer system, and more than 32K bytes AND of A15 and any other address line:
>-

memory

is

rare,

A1

A? A3 A4 AR
Afi

A7 AR A9

CO
w

A1D
A11 A1?

A13 A14 A1R

Any two of the 14 unused address lines can be tied to CI and C2, in order to select one of the four addressable locations on the Parallel I/O interface device. Consider this example:

AO
A1

C1

C2

A2 A3 A4 A5 A6 A7 A8 A9 A10
A11

A12 A13 A14 A15

Memory addresses may

15 14 13
1

select ports as follows:

7

12

11

10

9
|

I
~~x

Y
l

00

Port

01 =Port B 10 = Interrupt vector upper = Interrupt vector lower 1

Must

all be to be sure no additional device is

simultaneously selected

Must be

to select device

5-21

Thus C000 16 addresses Port A C001 16 addresses Port B

C002 16 addresses C003 16 addresses

routine

Interrupt Vector Interrupt Vector

is

Upper

Lower
it

Multiplexing the data bus

not a

real

problem;

simply means the interrupt service

,

the program executed immediately following the interrupt

read the contents of

memory

bytes as the starting address for

locations C002 16 and C003 16 and the program to be executed next.

acknowledge -- must treat these two data

at the

Having the interrupt request signal arrive at memory or interface devices, rather than CPU, means that for every memory or interface device in the system, a different external device can have its own interrupt service routine identified for
post-interrupt execution. This concept
is

illustrated as follows:

PROGRAM

MEMORY
0200

ROM

device

provides this

interrupt address vector

02A0
Arbitrarily selected

I/O device

provides this

interrupt address vector

memory addresses
031A

ROM

device 2 provides

this

interrupt address vector

^ 04C0

ROM

device 3 provides

this

interrupt address vector

In

the above

illustration, interrupt

request signals arriving at

in

ROM

devices

1,

2 or 3
,

will

always

specify execution of programs stored

.

memory

with execution addresses 0200 t6

031A 16 and
1
.

04C0 16 respectively. An interrupt request signal arriving at Parallel I/O Interface device will always specify execution of a program stored in memory with execution address 02A0 16 Each inis passed on to the CPU as IREQO. terrupt request arrives as a separate and distinct IREQ signal;
it

When
But a

the

CPU acknowledges

with IACK. the

ROM

or I/O device

requesting the interrupt

transmits the interrupt address vector,

which

is

permanent feature

of the

ROM

or I/O device.

than one device capable of requesting an inWhat happens when more than one device simultaneously requests an interrupt? Which device is to be acknowledged, and how do we prevent the other devices from also acknowledg-

new problem arises when more

is

terrupt

included

in

a microcomputer system.

ing?
There are two parts to the answer. First, we must provide devices with a means of identifying themselves; we use select codes for this purpose. Next we must include interrupt priority arbitration logic.

Let us examine these

two concepts.

INTERRUPTING DEVICE SELECT CODES

Consider an improved model of our shower temperature controller, designed to control the temperatures of many showers for motels and hotels. A microcomputer would certainly be fast enough to monitor and control shower head temperatures for 100 or more showers.

5-22

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go

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of
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0/1

iyod

o/i

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it

oo. G5

ro

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5-23

<

>-

D
CD

iii

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B 5 g

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^
CD cj CD

53

i? Q. 3

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5-24

It would not be very economical or practical to require a new memory or I/O interface device to be added to the microcomputer system for every new shower to be

controlled. Many microcomputers will therefore require an external device, when requesting an interrupt, to accompany the request with an identification code. Figure 5-12 shows how an external device may connect directly to the External System Bus, placing its identification code on the data lines of the External System Bus when the CPU acknowledges its interrupt request with IACK. With
reference to Figure 5-12, events proceed as follows:

(T)

External device logic creates an interrupt request signal,

which

it

transmits to the

CPU

as

IREQ.

(2)
(3)

When
Upon

the

CPU

is

ready to service the interrupt request,

it

responds by outputting IACK.

receiving IACK, external device logic places an 8-bit select

code on the data

it

lines of

the External System Bus.

identification code.

The CPU receives

this

data and interprets

as an external device

(4)

Following protocol specified by the microcomputer system, the external device places
data at a Parallel I/O Interface device's I/O port.

its

of having external devices identify themselves with a code, as illustrated in Figure 5-12, makes a lot of sense to a minicomputer user (or designer), but to the microcomputer user it has one elementary flaw: it demands intelligence of the external device. Remember that a minicomputer may cost thousands of dollars and may be part of a system costing tens of thousands of dollars. Very few microcomputers cost more than $100, so we can only justify using a few dollars worth of logic to generate a device select
code.

The idea

have another reason why minicomputers and microcomputers are, and are remain, fundamentally different. The cost of providing external devices with the logic implied by Figure 5-12 may only be a few dollars, which is trivial in the
Here
likely to

we

world of minicomputers. But a ROM device, or a Parallel I/O interface device, also only costs a few dollars; therefore, every demand for dedicated intelligence in external devices is, comparatively, an expensive demand in the world of microcomputers. External device select codes, which are so obvious in the world of minicomputers,

must be justified on a case-by-case basis in the world of microcomputers. Chip costs increase very little with chip complexity, so economics demand that the microcomputer system does as much as possible, and demands as
little

are an expense which

as possible of external

logic.

Consider a simple example.

not easily
really

minicomputers are priced at $3250 and $3640. Options that are compared make the two prices hard to evaluate, in determining which minicomputer is more expensive. one minicomputer system requires that an external device have $10
If

Two

worth of extra logic in order pact on overall economics.

to request interrupts, this extra

expense

will

only have a limited im-

Two

for one very specific application, cost $53 and $61, need $10 worth of extra logic to request an interrupt on the $53 microcomputer system, but not on the $61 microcomputer system, then the $53 microcomputer system may well be eliminated for this single reason.

microcomputer systems, configured

If

respectively.

an external device

will

5-25

INTERRUPT PRIORITIES
What happens when more than one
same time?
priorities,

external device requests an interrupt at the This problem can be resolved in two ways. First, logic within the microcomputer system can have a number of interrupt request lines with ascending

as follows:

Vdd
Power and Ground
Vss

DO
D1

Vgg

D2

Clonk

D3

AO
A1

D4

>

Data.

CPU

D5
D6

A2

A3
A4
A5

D7

W
R

WRITE

READ
IOSEI

A6
^Address <

A7 A8 A9

IORW
IACK
IRFD1

^ ^. ^ ^
^
Prinnty
1

Interrupt request

A10
A11

^ iRrm ^
IRFO?

Priority 2 Interrupt

request

Prinnty 3 Interrupt request

A12

A13 A14
I

A15

A
in

special Interrupt Priority device could

pins.

fewer CPU

do the same job, using Consider the Interrupt Priority device illustrated

INTERRUPT
PRIORITY CHIP

Figure 5-13.

Before discussing how the Interrupt Priority device illustrated in Figure 5-13 works, we will define what is meant by interrupt
priorities.

INTERRUPT
PRIORITIES

AND WHAT
THEY MEAN
interrupt

Suppose more than one external device may request an interrupt. If two or more external devices request interrupts by SIMULTANEOUSLY sending IREQ signals that overlap in time, then WHICH external device gets the
(IACK)
is

acknowledge

determined by interrupt

priority:

Device

IREQ (second

priority)

A
Device

IREQ

(third priority)

MICROCOMPUTER SYSTEM

wrv
p4
Device

IREQ

(first priority)

5-26

Vdd
Power and Ground
Vss

DO
D1

vgg

D2 D3 D4 D5
INTERRUPT
PRIORITY

Clock

4>

>

Data^

10
11

12 13 14 15

D6 D7
IO0
101

16 Interrupt request

lines.

16 17

I02

with 16

priorities (0 highest,

I03
>-

15 lowest)
18
19

I/O Port

I04 I05 I06 I07

110
111

112

W
R

WRITE

113 114 115

READ
IREQO
IACK

Figure 5-13.

An

Interrupt Priority Device

In

the above

illustration,

external devices A.

B and C

all

request interrupts by simultaneously

transmitting IREQ signals to the microcomputer system. By whatever priority arbitration technique the microcomputer system is using, it is determined that Device C has the highest priority, Device

has the second priority and Device B has the lowest IACK, must therefore be sent to Device C.
fact that

priority.

The

single

acknowledge

signal.

Devices A and B did not have their interrupt requests acknowledged does not imply must remove their IREQ interrupt request signals. They can do so they wish. If they do not, they will be acknowledged, in turn, when the microcomputer CPU is subsequently ready to acknowledge interrupts again.

The

that they

if

Refer again to the illustration of Devices A, B and C,

ice.

all

simultaneously requesting interrupt servin

There are three

interrupt service

programs residing

memory, one

for

each device. These

programs may be executed as follows:

Re-enable interrupts

Acknowledge IREQ from Device C

Acknowledge IREQ

Acknowledge IREQ
from Device B

Disable interrupts

5-27

(0) represents the main program which

interrupt service routine gets

is

executing, and which gets interrupted.

First

Device C's

routines get executed at

If

@ and,

executed

at.

Subsequently Device

and B's

interrupt service

respectively.

interrupt service

routines,

andare

to

be executed sequentially, as

illustrated

above,
dis-

then while

is

executing, the microcomputer system's interrupt handling logic

must be
point,

abled, so interrupt requests (IREQ) from Devices

A and

B are ignored. At some

after

completes execution and

is

re-enabled;

now

IREQ from Device

(^has resumed executing, the microcomputer system interrupt logic A is acknowledged. While is executing, the microcomis

puter system's interrupt handling logic

again disabled

until

some time when (m) has resumed

execution. Since Device B

is

still

requesting an interrupt, Qi)

now

gets executed.
in

Special instructions are used to enable and disable interrupt logic

microcomputer systems.
7.

These

instructions,

and

how

they should be used, are described

in

Chapter

Suppose the microcomputer system did not disable its service routines such as and . This is how the

interrupt logic while executing interrupt

interrupts

would be

serviced:

Ths important concept to understand is that interrupt priorities determine which device receives the interrupt acknowledge IACK when more than one device is
simultaneously requesting an interrupt via IREQ.
Interrupt priorities

have nothing to do with whether () can be interrupted by

started executing. Device A has lower interrupt priority than Device however, once Device C's interrupt request has been acknowledged. Device C removes its interrupt request. Device A's interrupt request is still present and is the highest priority interrupt re-

Device

A once has

C;

quest. The instant program enables interrupt logic, it will immediately be interrupted, and program (A) will execute. If you do not want program (5)to be interrupted, then when you write program you must make sure it keeps interrupt logic disable. Instruction steps to do this are

described

in

Chapter

7.

Let us now return to the Interrupt Priority device illustrated in Figure 5-13, and explain how this device works. As illustrated, there are 16 separate and distinct lines via which external
devices can transmit interrupt request (IREQ) signals to the Interrupt
Priority device. Signals
priority,

INTERRUPT
PRIORITY

AND

MULTIPLE

REQUEST LINES

terminate at pins
priority.

10

through

115. 10

has highest

while 115 has lowest

or

When one
device sets

more interrupt requests IREQO high.

arrive at pins 10

115,

logic within the Interrupt Priority

At some future time the

CPU responds

by setting IACK high.

5-28

When

the Interrupt Priority device receives IACK high,

line

it

sets

IREQO low again, then places the

lowest interrupt request

For example,
if

number on DO
15,

D3.

one IREQ

arrives at
16

0101
113,

is

output
is

via

DO

two IREQ
high.

signals arrive, at pins

and

01 10

output

at pins

D3 when IACK is sensed high. DO - D3 when IACK is sensed

If

Timing

is

as follows:

IREQ

IREQO

DO

D3

IACK

Once

the interrupt has been acknowledged, the Data. I/O,

READ and WRITE

signals are used to

transmit data to and from external logic.

External

The data

lines interface the Interrupt Priority

device to the

System

Bus, while the I/O pins interface the Interrupt Priority device with external
in

devices, as illustrated

Figure 5-14.
initially

External devices can use an Interrupt Priority device to

interrupt has

request an interrupt, but once the

been acknowledged, the

external device can transfer data to or from the

microcom-

puter system via the data lines of the External

System

Bus. Of course, this

in this

means

that the external

device

is

selected via

memory

addresses, as described earlier

chapter.

The important point to note is that any programs executed after an interrupt has been acknowledged use the same logic as programs executed before the interrupt was acknowledged. Interrupt logic applies only to the process of requesting and accepting an interrupt. If external devices connect to the microcomputer system
do likewise after the interrupt has external devices connect to the microcomputer system via the data lines of the External System Bus, they will do so before and after an interrupt is acknowledged.
via I/O ports before the interrupt, they will

been acknowledged.

If

there

system only has one interrupt line, or if more than one external device using the same priority interrupt request, then a method called "daisy chaining" must be employed to determine interrupt priorities.
If

a microcomputer
is

INTERRUPT
PRIORITY

AND DAISY
CHAINING

A number of

connect to the same interrupt request line IREQ. The interrupt acknowledge line. IACK, however, will terminate at one external device. This device must have internal logic which passes on the interrupt acknowledge if the device is not requestdevices
in

a daisy chain will

all

ing

an

interrupt,

but traps

it

otherwise. Each external device

in

the daisy chain contains this

same

5-29

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5-30

logic,

except for the

last

device,

which has nowhere

to

pass the acknowledge on

to.

Daisy chain-

ing

may be

illustrated

as follows:

IREO

Device

Device
3

Device
2

Device
1

To Microcomputer System

IACK

There are strengths and weaknesses associated with having separate priority lines, or daisy chains, in microcomputer systems. In either case, the question becomes somewhat academic
since, as described in Chapter 6, a microcomputer system that is being interrupted by a great multitude of external devices is probably being misused. Nevertheless, let us consider some of the strengths and weaknesses associated with separate interrupt priorities, and with daisy chains.

There are situations where separate interrupt priority makes sense, because the microcomputer CPU must attend to one external condition at the expense of all
others.

For example, most minicomputers- have a highest priority interrupt which is activated by a power failure. Whiie this may not at first make a lot of sense, consider what happens when power does go down.
Microcomputers typically use + 5 and/or + 12 volt DC power supplies POWER FAIL which are generated from the normal 110 volt AC power line. Power INTERRUPT failure might be detected when power falls below 90 volts. But may be a few thousandths of a second before power drops so low that + 5 and 12 volts cannot be maintained for the microcomputer. In these few milliseconds, a hundred or more microcomputer instructions may be executed to prepare for power failure in an orderly fashion, now when power comes up again, the power fail interrupted program can restart without loss of data.
it

We

have described one situation where separate sider the limits of daisy chaining.
will

interrupt priority lines

make sense. Next con-

Daisy chaining
the
if

handle a number of devices,

all

of

which require
little

interrupt service, so long as

shower would get needs of the 99 showers that came before in the daisy chain. is quite conceivable that the microcomputer system will be so busy attending to devices situated at the beginning of the daisy chain that the tail-end devices would get little or no attention. The occupant of Room 100 will get scalded or freeze.
not

number does

become

too large. Consider

first

how

service the 100th

the microcomputer system must

It

respond

to the

it

Another problem with daisy chaining is that it demands intelligence of any external device in the daisy chain. Once again, we are dealing with microcomputer economics.
External devices
in

a daisy chain

must

identify themselves,

otherwise the microcomputer system

the daisy chain

has no

way

of
it

went before

knowing how got trapped. So

far

down

the daisy cha,n the interrupt acknowledge signal IACK

we

are back to

demand'ng

that external devices

interrupt
is

in

contain sufficient logic to trap the acknowledge signal

to transmit a device identification

when an

being requested, then

code

to the

implemented
either.

for a

few

dollars,

but

remember

microcomputer system. Certainly this logic could be a microcomputer does not cost too many dollars

order to eliminate the cost of external logic required implement a daisy chain, some microcomputer manufacturers provide this logic on support devices. Consider daisy chain logic on an I/O interface device;
In

DAISY CHAINING

to

WITH

I/O

INTERFACE DEVICES

5-31

Here

is

one possible

Parallel

I/O Interface device configuration:

Vdd
Vss

SO
SI

<-> Device

select

<>
><->

signals

Vgg

$
100
101

'

|^
address vector

DO
D1

D2
Interrupt

CO

D3
D4
D5

<
1
Q-

I02

I03
I04 I05 I06

3 CO < < Q

D6
D7
><->-

<
PARALLEL
I/O

<->

I07

<-> 108
109
CD 1 cc

< IORW > IREQO

<

IOSEL

INTERFACE

IO10
1011

WITH
INTERRUPT LOGIC

IACK
IREQ

O Q. o
-<->

1012 1013

1014
1015

In order to acquire the extra pins for needed signals, we have replaced 8 device select pins (AO - A7 in Figure 5-12) with two pins, SO and S1. For the device to be selected, a low signal must be input at SO. A simultaneous low input at SI will select Port A. A

simultaneous high input

at

S1

will

select Port B.

You can

usually choose

two address

lines

and
is

tie

them
could

directly to

SO and SI,
lot of

thus selecting individual Parallel I/O devices

without using a

external device select logic. This

how you

DEVICE SELECT LOGIC

use the 8 address

devices:

lines illustrated in Figure

5-12 to select four

Parallel

I/O

A7

A6

A5

A4

A3

A2

5-32

What addresses would be

dresses as follows:

assigned to I/O ports

and B of Device 3? You can compute ad-

A7

A6
1

A5
X

A2
1

A1

AO
1

Must be to insure I/O devices 1, 2 or 4

I

are not selected

Could be

or

1.

We

arbitrarily select

Must be

to select device 3

selects Port
1

selects Port B

Thus 45 16

selects device

3, 3,

Port A.

65 16 selects device

Port B.

This device select logic has nothing to do with interrupts we are currently discussing.

which

is

the subject

A number
follows:

of Parallel I/O Interface devices with interrupt logic

would be used as

REQO
I
i i

A
I/O Device

TO

MORE
DEVICES

I/O Device

I/O Device

TO MICROCOMPUTER SYSTEM

'

IA(:k

IACK
IREQ

IACK
IREQ

ACK

IREQ

\
This
1)

f
I

4
device

- External

interrupt requests
is

_/

what happens:
one or more external devices request an
interrupt,

When

they set their IREQ

it

line "true".

2)

When one or more Parallel the common IREQO line.

The CPU receives not know which

I/O devices receive a "true" IREQ, they pass

on

to the

CPU

via

3)

a "true"
is

IREQO

input.

CPU

logic

now knows

that

some

device

it

does

requesting an interrupt.

4)
5)

When CPU
The
"true",
it

logic allows the interrupt to

be acknowledged

it

outputs IACK "true".

If

first Parallel

I/O device

in

the daisy chain receives IACK "true".

it

has received IREQ

via

traps the

IACK
If

signal,

without regard to whether or not

I/O device
2.
in

it

has been selected

the
in-

SO and S1
put,
it

select lines.

the

first Parallel

the daisy chain has a "false" IREQ

first

passes the IACK signal on to I/O device

The

I/O device with IREQ input "true"

traps IACK.

5-33

6)

The I/O device which

this
still

traps

IACK now outputs

its

interrupt address vector

on the data bus;

allows the I/O device to be identified. Note that select logic associated with SO and S1 not involved. The interrupt request/acknowledge logic has
its

own

select logic

is
is

it

part of the logic

7)

which traps IACK or passes

it

on.

Now
used

the interrupt service program takes over.

If

data

is

to be input or output,

SO and S1

are

to select the appropriate I/O device, just as

any other program would do.

Parallel I/O with interrupt logic device introduces a very important concept putting more than one function on a single chip. Parallel I/O logic and Interrupt logic have nothing in common. They happen to be on the same chip, so they share the data bus pins DO D7.

The

MULTI-

FUNCTION
DEVICES

External logic can request an interrupt via one I/O device; then after the interrupt has been acknowledged, the external logic can transmit or receive data via I/O ports of the same I/O device, another I/O device, or via no I/O device.
Following an interrupt, there
device which trapped IACK.
is

no reason

why you must

transfer data via the I/O ports of the I/O

I/O logic

and interrupt logic happen to share a chip; they have no other connection.

DIRECT
The shower temperature
controlling

MEMORY ACCESS
to

microcomputer system will spend a lot of its time simply receiving data from the temperature sensor and storing the data in a RAM buffer.
have described
is

We

how

interrupts

may be used

execute program

RECORD whenever the temat this

perature sensor

ready to transmit data. Let us take another, more careful look

scheme.

Remember

the temperature sensor can transmit approximately

this is

two temperature readings per

second. To the microcomputer system,

equivalent to receiving a temperature reading once

every quarter of a million instruction executions

approximately.

A cheap temperature

sensor is not going to transmit exactly two temperature readings per second. In fact, there could be considerable time period variations between temperature transmittals. As a result, we cannot predict, with any degree of accuracy, the time delay between consecutive ASYNCHRONOUS data transmittals from the temperature sensor to the microcom- EVENTS
puter system. Therefore, data transmittals from the temperature sensor to the microcomputer system constitute asynchronous events:
Readings transmitted by temperature sensor to microprocessor

Microprocessor program execution

Because data transmittals from the temperature sensor to the microcomputer system are somewhat unpredictable (or asynchronous), program RECORD must be executed every time the temperature sensor transmits a data item. Program
will

RECORD

contains the instruction sequence which

buffer; this instruction

move

data from an I/O port to a byte

in

the

RAM memory

sequence

5-34

5-35

cannot be part of program ADJUST, since the logic of program ADJUST cannot detect the arrival of data from a temperature sensor. Any scheme that executes the RECORD instruction execution sequence at fixed time intervals is bound to miss a large number of the

data transmittals from the temperature sensor. Here

is

an example:

Readings transmitted by temperature sensor to microcomputer

@
it

represents normal execution of program

ADJUST.

represents fixed, periodic execution

sequence which records data transmitted by the temperature sensor to the microcomputer system. If transmitted data does not reach the microcomputer system during (R)
of the instruction

may be

missed.

The only safe way of catching all data transmitted by the temperature sensor is to have the temperature sensor request an interrupt when it is ready to transmit a
will
In response to the temperature sensor's interrupt request, the microcomputer system execute the data sensing instruction sequence, characterized in the illustration, above by (R) The illustration must now be modified as follows:

data item.

Readings transmitted by temperature sensor to microcomputer

(A)

Each time the temperature sensor transmits data to the microcomputer system, it notifies the requesting an interrupt. In response to the interrupt request, program logic suspends execution of program ADJUST while executing program RECORD (). Program RECORD reads the data input by the temperature sensor, then program ADJUST continues executing from

CPU by

the point of suspension.

Even This
1

this

method

of recording data transmitted

is

what happens when the CPU accepts an

is

by the temperature sensor is not very efficient. interrupt and executes RECORD:
)

The CPU
and

executing program
it

an interrupt request,
status;

executes

ADJUST in the illustration some instructions which save

(

above.

When

the

the contents of
interrupt.

CPU senses CPU registers

then

it

executes an instruction to acknowledge the

2)

Program RECORD in the illustration above) is executed. This program contains tions which load a memory address into the Data Counter, read data from an I/O port
Accumulator, then output the data from the Accumulator to the
the Data Counter.

instrucinto the

memory word addressed by

3)

Step

is

reversed.

Saved contents

of registers

and status are restored and program ADJUST

continues execution.

Out of

all the instructions that get executed to implement the above three steps, the only change, each time the temperature sensor transmits a reading and (r) is re-

executed,

is

the contents of the Data Counter

in

Step

2.

The contents

of the Data

5-36

Counter

will

be one more than

it

was

last time,

and one
this
is

less than

it

will

be the next time.

trivial

Fifty

microseconds or more are needed

to repetitively

process an otherwise predictable and

se-

quence of events. Before we can decide whether we must ask two questions:
1

a serious or an inconsequential problem,

Are operations
The answer
In fact,
is

like this fairly

it

common,

or

is

this an isolated

and special situation?

a

that

is

not only
it

will a

one of the most common microcomputer spend a great deal

operations performed by

microcomputer.

of time reading data

from an exter-

nal device,

will

spend almost as much time

routinely transmitting data

from

RAM

buffers to

external devices.
2)
If the microcomputer did not spend 50 microseconds every time it input data from an external device (or output to an external device), what else would it do with the time?
is nothing, in which case the wasted time is irrelemicrocomputer application starts to get more complex, the waste of time starts to become more serious. If it takes 50 microseconds to read a data item from an external device, and another 50 microseconds to transmit a data item to the same external device, then one microcomputer system could perform one hundred data transfers per

In

many

simple applications the answer

vant. But clearly, as a

second

but there

would be no time

left

to

do anything

else.

We must therefore conclude that there will be a significant number of applications in

which the time wasted processing interrupts
will

be intolerable.

CYCLE STEALING DIRECT MEMORY ACCESS Direct memory access (DMA) provides a solution. We will create a new device for our
this device we will place a small amount of CPU-type dedicated to the sole task of moving data between I/O ports (or the data lines of the External System Bus) and memory.

microcomputer system, and on

logic,

The

DMA
it

while

device will accomplish its task by suppressing or bypassing CPU logic creates signal sequences that enable the appropriate data transfer.
in

Given the microcomputer system architecture that has been described chapter, the task of designing a DMA device is really quite straightforward.

this

INHIBIT Temporarily suppressing CPU logic is easy, since the CPU is CONTROL driven by an external clock signal. If we can stop the clock signal, we can stop the CPU. Therefore, as illustrated in Figure 5-15, we will add an INHIBIT control line to our External System Bus, and an INHIBIT control pin at the CPU device.
The INHIBIT
signal will normally

be high so that a simple AND-gate within the

,

CPU

chip

will

com-

bine the clock signal with the INHIBIT signal, to generate the internal clock signal which drives

CPU

chip

logic:

INHIBIT-

-CPU $

All

the

DMA

device has to do

is

set the INHIBIT signal

low

in

order to suppress timing clock sig-

nals within the

CPU

chip:

J
INHIBIT

cpu

<t

5-37

Memory

devices and

Parallel Interface

devices have no
the

way

of

knowing where the control

signals

that drive their logic

System Bus while

come from. Therefore, CPU logic is suppressed.

in

DMA

device can take control of the External

Consider Figure 5-15

more

detail.

The

DMA

device, as illustrated, contains the

following three registers:

1

An Address

register which contains the address of the next

memory word

to

be accessed,

either for a read or a write operation.

2)

A Counter, A
Status

which

initially

contains the length of the data buffer which

is

is

to

be

filled

during a

read operation, or out of which data

3)

to

be read during

a write operation.

register, which identifies the direction of data flow, whether the

DMA
few

logic

is

currently active or inactive,

and various other

DMA

options.

We

will

look at a

of these

options

later.

To the CPU, the

registers of the
Initially,

DMA device

memory words.

programmed I/O

may appear as I/O ports or addressable instructions will be used to set values in
is

the Address, Counter and Status registers. Here

an example:

0080
007 F
03
This simple
filled
[

Address Register
Counter Register
Status Register

example

specifies that a data buffer, 7F, 6 bytes long

and ongined

at

0080]5.

is

to

be

with data from an external device, using Direct

register
is

Memory

Access.

The Status

for the

moment

limited to this simple format:

6 5 4 3 2

10
1

Bit

Number

Q3TTTTT
"

( (

= =

Data input from external device. Data output to external device.

logic active. logic inactive.
is

= DMA = DMA

By setting a value of 03, 6 in the Status and DMA logic is activated.

register,

data input from an external device

specified,

A program must be executed by

operation. The program
device registers. There
is

the

CPU

to

initialize

DMA
DMA DMA

DMA
INITIALIZATION

will

have

to load data appropriately into to get into the

no other way for data device Address, Counter and Status registers.
In

order to

initialize

DMA

operation, a

program would be executed by the CPU to

address to the

perform these steps:

1)

Transmit the low order

Transmit the high order

half of the starting

half of

DMA

device.

2)

the starting address to the

DMA

device.

3)

Transmit the buffer length to the Transmit a control code (03 16 as

,

DMA

device.

4)

illustrated

above)

to the Status register of the

DMA

device.

The

control

code must

identify the direction of the data transfer

and must turn the

DMA

device on.

Notice that the

DMA

device has

READ and WRITE

control lines.

The WRITE

control line will be

used by the

DMA

device to write data into

RAM.

5-38

The READ

control line will be

used by the

DMA

device to output data from

of

RAM

or

ROM.

The CPU can,

at

any time, read the contents

DMA
DMA

device

DMA CAUGHT
ON THE FLY

registers. This allows a program to check on

how

far a

operation

has progressed by reading the Address register and/or Counter register

contents.

operation

is

program that adjusts its logic to the current said to be catching DMA on the fry.

level of

completion of a

DMA

Of course, an executing program can turn a DMA operation of f aft any time by simply writing new data into the DMA device's
register to

DMA BEING
TURNED OFF
progress.

Status register. As described above, setting the would immediately stop any DMA data

bit of

the Status

transfer that

was

in

What happens

after a operation has started? Notice that external devices are connected directly to the data lines of the EXECUTION External Data Bus. In addition, the external device has a request signal (DMAREQ) which it pulses high to the device. If data is being read from the external device, the following signal sequence occurs:

DMA

DMA

DMA DMA

D0-D7

WRITF

The

entire

DMA
as the

operation occurs-in one clock cycle.

Events occur as follows:

1)

As soon
edge

DMA

device senses a high pulse on the

(

DMAREQ
is

line,

it

immediately lowers
the second rising

the INHIBIT control signal

of clock pulse
will
(j)

(T) above). The INHIBIT control

kept low

until

to follow ((T) above).

2)

The CPU

suspend operations for one clock cycle because INHIBIT line low ((3) above). The CPU will also apply high resistances at its connections to the address and data busses, effeckeeps the

FLOATING

CPU

(J)

BUSSES

tively

disconnecting

itself

from these busses. This

(

is

referred to as floating the busses.

3)

low and <t> rising above) causes the DMA device to output Address register on the address lines of the External System Bus (above). Also the DMA device acknowledges the DMA request by pulsing the DMACK response control line high (above).

The combination
the contents of

of INHIBIT
its

5-39

The

bit

of the

DMA

Status register determines whether the

DMARW

control line will be

it

high or low.

As

illustrated

above,

it

is

low. indicating to external logic that

data to the data lines of the External System Bus.

DMARW low causes the System Bus {(7) above).

The
bit of

external device to

must transmit The combination of DMACK high and place its data on the data lines of the External

the

DMA

Status register also causes the

WRITE

control

line. All

RAM

interface devices will

DMA device to output a high on the decode the address on the address lines

on sensing the WRITE control high, the selected RAM interis on the data lines of the External System Bus and will write this data into the addressed memory word. RAM interface logic neither knows nor cares where data, address and control signals originated. It simply responds to any situation and one
will find itself will

selected;

face device

take whatever data

which activates

its

internal logic.

As

terminates DMA operations. In reality, some rising edge of scheme would be used, since the one illustrated, though ve ry simp le, would c ause jitter in the leading edge of CPU 0. CPU goes high only because INHIBIT goes high. INHIBIT going high for a s econd goes high because just went high for a second time. Clearly,
illustrated

above, the second

other

(J)

time cannot exactly coincide with

high had to occur and
stabilize:

CPU

(J)

going high, because

in

the middle, INHIBIT going

INHIBIT
,r
!

CPU
Thus, as
practical.
illustrated,

the

DMA read timing diagram

is

conceptually accurate but

realistically

im-

As soon
Bus.
it

as the

DMA

device has output the contents of

register,

its

Address

register to the External Data

will

increment the contents of the

so as to address the next word of the

of
its

RAM

data

buffer.

Simultaneously the
is

DMA

chip

will

decrement the contents

operation:

Counter

register.

Here

the signal sequence for a

DMA write

5-40

Notice that the write operation differs from the read operation only in that the device sets the READ control signal high when it places the contents of its Address register on the address lines of the External Data Bus. This causes the memory module which is selected by the memory address to place the contents of

DMA

DMA

DMA

the addressed

memory word on

the data lines of the External Data Bus.

to read the
its

DMARW,

set high by the

DMA
Once

chip,

causes the external device

contents of the data bus.

again the

DMA
it

device

will

decrement

Counter register and increment

its

Address

register,

so that

is

ready for the next

DMA

operation.

One

of

two

things

may happen when the counter

register

decrements to

zero:

The
is

DMA device may signal the fact that the DMA operation
DMA device may simply start the whole process over again,
Counter register and Address
register,

DMA END
is

rupt
2)

over by sending an interrupt request to the CPU. This inter would be handled according to whatever interrupt processing logic the CPU

using.
origi-

The

by saving the

nal value of the

so that

it

can reload these

original

values and allow operations to proceed endlessly, or

until

stopped by the CPU.

to zero are illustrated as follows:

The two options available when the First the "end of DMA interrupt":
Cycles stolen by

DMA

device counts

down

Last

DMA
Interrupt request follows
last

DMA

stolen cycle

///
Main program executing
Next consider a
length count:

DMA cycle

Continue main program execution

DMA

device with additional storage registers for the

initial

address and buffer

Initial Initial

Address

Current Address
Current Count
Status

Count

When
dress"

"Current Count" goes to

is

0, "Initial Count" is loaded into "Current Count", and "Initial Adloaded into "Current Address": Status remains unchanged (unless modified by the CPU),

and the

DMA

operation starts over, re-accessing the

same

buffer,

from the same beginning.

One

MULTIPLE EXTERNAL DEVICES DMA device can control DMA operations for many external devices. Since a DMA device does not actually transfer any data, does not need any I/O ports
it
it

DMA WITH

through which external devices communicate with the microcomputer system.

The external devices connect directly to the data lines of the External System Bus. This arrangement is very convenient, since allows the DMA device to control DMA access for a number of
external devices.

5-41

hit
CD
i

Hi

>
CD

LO

mi

t-

CD

>

<M

CD

or

<

\fvym u

OQQQQQQQ
in

^
<y)

fc

rs,

CO

5
<.

^r

Ln

<J)

a)

C/)

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00

> > >

< < <

<<<<<<<555

55

5-42

Many schemes

could be devised which allow one

DMA

device to control

DMA

access

for

more

than one external device; Figure 5-16 illustrates just one possibility.

The

DMA

device illustrated

in

Figure 5-16 controls

its

DMA

devices. Each external device has

own DMA

request

line

access for five external (DMAREQ1 through

read-write control

DMAREQ5). Common

DMA

acknowledge (DMACK) and

all

DMA

(DMARW)

lines are

used by

devices.

There are five sets of registers within the

device. Each external device,
setting
its

DMA

device, one set for each external

when

it

is

ready to transmit or receive data, indicates this fact by

own DMA

request

line high.

The

DMA

device logic accesses the correct three data

registers,
3,

based on the

DMA

request received. For example,

DMAREQ3

high identifies Address

this time.

Counter 3 and Status 3 as the registers containing the data to be used

When

the multidevice DMA device illustrated in Figure 5-16 steals a cycle and transfers a data word via DMA. the signal sequence is identical to that which we have already described for a single external device. However, external devices in Figure 5-16 must contain their own select logic. In other words a device which raises its DMA request line must be the only device to respond to DMACK, DMARW and the External Data is Bus; no other device attached to the multidevice DMA device must respond to these lines. the responsibility of the external device, not the multidevice DMA device, to ensure that only one
It

external device considers

itself

selected at any time.

itself

selected for DMA at any time, data transfers. Memory modules merely respond to address and control signals output by the DMA device. Memory modules neither know nor care where this information had its origin. Only the selected external device is active at the other end of the External System Bus, so the two ends of the data transfer are clearly

So long as only one external device considers

is

then there

no possibility of confusion

in

DMA

defined.

Let us consider an
External device 2
is

example

in detail.
it

ready for another data access, so

raises

DMAREQ2

high:

INHIBIT

(to steal cycles)

IREQ

End-of-DMA
interrupt

IACK

DMACK

DMARW
DMAREQ5 DMAREQ4 DMAREQ3 DMAREQ2 DMAREQ1
\f

V
1

If

U V
External

External

External

Device

Device 2

Device

3.

5-43

The

first

thing

DMA device
is

logic will
If

do

is

check the status

is

register associated with

DMAREQ2,

in

this case, register Status 2.

the enable

bit (bit 0)
it

0,

DMA
If

device logic

will

ignore the

DMA

re-

quest. Since
will

DMAREQ2

a pulse signal,

will

go away.
steal a

the enable

bit is 1,

DMA

de vice

logic

acknowledge the

interrupt

on

DMACK
DO
D1

and

CPU

cycle by lowering INHIBIT:

Vdd VSS
Vgo.

Address
Counter

D2

D3
D4

AO
At

Status

Address 2
Counter 2
Status 2
| t

PS
06
"I
|

A2 A3

D7

A4
A5 A6 A7 AS A8

Address3
Counter 3
Status 3

W
R

^"ipman

Address 4
Counter 4
Status 4

Address 5
Counter 5

>-

A12 A13 A14 AI6

Status 5

DMAREQ2 DMAREQ1
1

External

Externa.

Device

Devce

For the upcoming

the data transfer.

DMA

operation, only external device 2 can participate at the external

end

of

DMAREQ2

causes the contents of Address register 2 to be output at the address

pins:

from

DMA chip regtsters

To Address
lines of

JNHIBIT

(to steal cycles!

JREQ
_IACK

End-of-DMA
interrupt

External

Data Bus

:'-'.

u.

Tl
DMA
dress

ft
of

device logic
2.

will

decrement the contents of Counter 2 and increment the contents

Ad-

Since
dress,

DMAREQ2

identifies

no confusion can

result

Address 2 as the DMA register containing the required memory adfrom the fact that four other addresses, in four other address

registers, are present.

5-44

DMAREQ2
and

also identifies Status 2 as the Status register controlling current operations.

control lines are set based
Vdd VSS Vqq
J>

The W. R

DMARW

on the contents of Status

2:

DO
D1
Address
Counter
Status
1

D2

D3 D4 D5 D6
;

AO
Al

^ Data to or from DMA chip registers

Address

A2

Counter 2
Status 2

A3
A4 A5

D7

Address 3
Counter 3
Status 3

A6
A7

IREQ
Address 4

End-of-DMA
interrupt

IACK

A8 A9 A 10
All

Counter 4
Status 4

DMARW
DMAREQ5 DMAREQ4 DMAREQ3 DMAREQ2 DMAREQ1
' 1

Address 5
Counter 5
Status 5

A12 A13 A14 A15

'

'

'

External

External

Device

Device

data transfer
2.

now

device

Signal

occurs between the memory word addressed by Address 2 and external sequences associated with the data transfer are exactly as described for the

single external device

DMA

chip.

SIMULTANEOUS DMA
Observe
of the

that cycle stealing

logic

CPU

on a

DMA really involves nothing more than reproducing a limited amount DMA device A DMA device may be likened to a CPU which is capatwo
instructions:

ble of executing just

1

Transfer data from an external device to memory. Transfer data from

2)

memory

to an external device.

Because of the very limited number of operations which the DMA device can perform, nearly all of the time-consuming sequences associated with CPU operations (for example the instruction
fetch)

can be eliminated.

But
ing

we can take DMA logic a step further. By duplicating part of the External System Bus, we can eliminate the need to steal cycles from the CPU. Look again at the timdiagram for a memory read operation:

AO

to

A15

DO

to

D7

Memory Read
Instruction

5-45

To

RAM

Devices

<

Notice that even though the External System Bus is constantly busy, neither memory nor external devices will be busy during the <t> high portion of instruction cycles. These periods, shaded above, represent the time required by the CPU's Control Unit to generate appropriate control signals.

By creating a second External System Bus, DMA logic can access while the CPU is not doing so. This is illustrated in Figure 5-17.
External devices will be connected to the data lines of the

memory modules
shown
in

DMA System

Bus. as

Figure

5-17, for

all

DMA

data transfers.

If

the external devices also access the microcomputer system

using
nal

programmed

I/O. then there

must be

additional connections to the data lines of the Exter-

System Bus; these

additional connections are not

shown

in

Figure 5-17.

At the memory modules, the must communicate with two busses and
of T-junction. This T-junction
is

same memory and address

that will require

pins

some form

TRI-STATE BUFFER

referred to as a "tri-state" buffer.

tri-

state buffer,

is,

in

effect,

nothing but a multiple signal T-junction:

[To Bus

To Device

TRI-STATE

BUFFER
,To

Bus B.

SIMULTANEOUS VERSUS CYCLE STEALING DMA

What about
ternal Data

the economics of Simultaneous

DMA? We
buffers.

must pay

for another Exis

Bus and a number of

tri-state

What we buy
it

little

time: one clock cycle for every byte of data transferred.

In reality,

the extra cost for the tri-state buffer

will

is

very small;

in fact,

is

not inconceivable that

are therefore talking

memory modules

be provided with

tri-state buffers built into

them.

We

about a very small additional expense

for a very small

performance improvement.

microcomputer designer is therefore more likely to select one DMA method or the other based upon which method is best suited to the architecture of the microcomputer system.

THE EXTERNAL SYSTEM BUS

The
on the External System Bus, as illustrated throughout this chapter, do not define a standard configuration to which all microcomputers must conform.
signals

The External System Bus represents one of the most varying features of any microcomputer system. Indeed, the only constant feature you will find from bus to bus is the
presence of eight data
lines (for 8-bit

microcomputers). Most microcomputer systems

will also

have 16 address

lines.

The greatest

variation is seen in the control signals generated by the CPU. Basically there are two philosophical extremes. One extreme calls for a complex set of control signals to which other devices passively respond. The other extreme calls for elementary control signals which must be interpreted by devices that contain a considerable amount of internal chip logic.
Consider
this

the CPU that totally dominates a microcomputer system. Devices that interface to not receive any clock signal inputs. Instead they will receive numerous control sigSemiconductor and Signetics nals which identify events on the Data Bus in detail. The National microcomputers are the best examples of this philosophy.
first

CPU

will

5-47

The MCS6500 represents the other extreme. This microcomputer outputs

to identify either data input or output. All devices that support the

just

one

control signal

MCS6500 CPU

receive this
this

controf signal, plus the system clock signal. Devices contain internal logic to
bination of

decode

com-

two

signals according to the rules of the

MCS6500 microcomputer

system.

The philosophy behind National Semiconductor and Signetics type microcomputers is special devices are needed to support the CPU. By having a very complete set of control
standard off-the-shelf logic can be used.

that

no

signals,

The philosophy
that support the

of

costs virtually nothing to

microcomputers with very elementary sets of control signals is that since it add extra logic to an LSI chip, you are far better off generating devices
in

CPU

a very precisely defined way.

SERIAL INPUT/OUTPUT
transferred over telephone lines serially. There are also some slow I/O devices, such as the common teletype and magnetic tape cassettes, which transmit and receive data serially. If a CPU is to transmit or receive serial data, then it must have interface logic capable of converting serial data to parallel data, or parallel data to serial data:

Data

is

101 10101
1

10101
'

10010001
k

10

'I: -J

10
1

J1
1

1
1

Jo
1

[o
\1

\1

lo

These are the steps via which data microcomputer system:

is

transferred

between a telephone

line

and a

Telephone
Line

MODEM

SERIAL

MICRO-

INTERFACE

COMPUTER

A modem

is a device which can translate telephone line signals into digital logic levels, or digital logic levels into telephone line signals. Some microcomputer manufacturers provide modems as a single logic device, but we do not consider the modem to be part of the microcomputer system; therefore modems are

MODEM

not described

in this

book.

A magnetic

cassette unit, or teletype, or directly to the serial interface:

SERIAL
I/O

any other

serial

device can connect

SERIAL

MICRO-

DEVICE

INTERFACE

COMPUTER

IDENTIFYING SERIAL DATA BITS

The unique property
of a serial data stream is that the data received as a single signal, via single device pins:
is

transmitted and

Transmitting

Device

^j^
Transmitting
pin
Serial

Receiving

tltE

Receiving Device

Data
Signal

How is the receiving device to interpret a serial signal

data signal can have a "high" level
ing the digit 0.
(

Like
1.

any other

digital signal,

the

5v) representing the digit

or a "low" level (Ov) represent-

Consider the binary data sequence:

representation:
Serial Data:

011100100. This
I I I I I I

is its serial

data signal

Ul "TT-|_Ln
i
I

I
I

l
I

Interpretation:

n n O'l'l M'O'O'I'O'O
i
I

'

Whereas

it

is

easy

for

you

to look at the serial data signal

lines,
bit

and

interpret

it

CLOCK
SIGNAL

within the vertical broken

tangible evidence of data

the receiving device

will

require

more

use a clock signal to identify the instant at which the receiving device must interpret the data
boundaries.

We will

signal:

Clock Signal

Serial

Data

Interpretation.
illustrated above, the falling edge of the clock signal identifies the instant at which the serial could just as easily clock on the rising edge of the signal. data signal must be sampled.

As

We

Clock Signa

Serial

Data

Interpretation

serial

data signal must be created by the transmitting device before

it

can be interpreted by the

receiving device. Let us look into the implications of this simple necessity.

5-49

If the receiving device uses a clock to interpret the serial data signal, then the transmitting device must use a clock with the same frequency to create the serial data signal:

Transmitting

Clock Signal:

Serial Data:

rarmt
SriJri-JrLJrLJrLjf^^
1

Receiving

Clock Signal:
Interpretation:
1

The

transmitting and receiving clock signals cannot be identical: this

is

because

in reality,

it

takes

a finite time for a signal to

change

state.

Now

it

makes

figures easy to follow

if

signal transitions are

drawn as clean square waves:

3
But
in reality,

every signal that changes state requires a

finite settling

time:

SIGNAL SETTLING TIME

Look

at

what happens

if

you use the same

signal transition to transmit

and receive

serial data:

Single Clock
Signal:

Serial Data:

"0"

will

be received

when

" 1"

was

in

"1"

will

be received

the process of being

transmitted

when

a "0"

was

in

the

process of being
transmitted

5-50

We

conclude that the transmitting

in

nals, while they have a great deal

and receiving clock sigcommon, cannot be a single

SERIAL DATA

signal subject to identical interpretation.

The transmitting
binary
digit:

TRANSMITTING CLOCK SIGNAL

clock signal will identify the duration of one

Transmitting

Clock Signal:

Serial Data:

During

this

time interval

the serial data signal represents

a single binary digit.
illustration

The
to

happens

show

value of "1", occurring

between two "0"

At some point within the single digit time interval a receive clock signal will identify the serial data signal level:

digits.

SERIAL DATA RECEIVING

CLOCK SIGNAL

Transmitting

Clock Signal:

c
Serial Data:

Receiving

Clock Signal:
Interpretation:

Jn

Fl
SIGNAL SETTLING DELAY

The

illustration

receiving clock signal

above shows the transmitting clock signal active on its trailing edge, whereas the is active on its leading edge: there is nothing significant in this use of signal

edges.

The receiving device must wait for the Serial Data signal to settle, presuming it has changed state, before trying to read the signal level. A signal's settling delay is a characteristic of the

5-51

transmitting device; the length of this delay

is

given by the manufacturer's

device data sheet. Here

is

an

illustration of settling delay:

Transmitting

Clock Signa

Serial

Data

Interpretation

Settling Delays

We can use a singlaclock signal to transmit and receive, providing we transmit on

the trailing edge of a clock pulse, and receive on the leading edge of the next clock pulse:

single serial

digit

time interval

Single

Clock Signal:

Settling Delays

Look

carefully at

how

the transmitted signal level

is

received:

End

of digit time

interval

and

start

of next digit time

interval

Single

Clock Signal

Serial data

Read

signal level

shortly before

end

of digit time
interval

5-52

The time
ted.

interval during
is

which the

Serial

Data signal represents a single

at

BAUD
RATE

binary digit

directly related to the

1

speed

which data

is

being transmitthis
for:
is

Suppose

10 digits per second are being transmitted;

serial digit will

com-

mon

transmission speed. Each

then endure

1000000 =9091 microseconds

110

However, the duration are measured; instead,

of a digit in a serial data

we measure
if

stream is not the way in which serial data transfers "bits per second", and refer to this number as the
this
is

BAUD

RATE.

For example,

10 digits per second are transmitted,

equivalent to a baud

rate of 110.

Our microcomputer system already has a clock signal, used to time inCLOCK CPU. Do not confuse the microcomSIGNALS puter system clock with the serial data clock; the only thing these two signals have in common is that they are both clock signals. The serial data clock signal may or may not be derived from the microcomputer system clock.
struction execution within the

*^

From

a microcomputer user's point of view, speed is the most striking difference between the microcomputer system clock and the serial data clock. A typical microcomputer system clock may have a period of 500 nanoseconds (2 MHz) whereas serial data transfer rates typically range from

between
rate
is

10 and 9600 Baud

10 Hz to 9.6 KHz.

In

other words, the fastest serial data transfer

approximately 200 times slower than a typical microcomputer

CPU

clock.

The

serial I/O clock

does not necessarily have to pulse at ex

although frequently
it

SERIAL

actly the

baud

rate,

does:

CLOCK SIGNAL

Single

Clock Signal:

V
for the clock rate to

Serial Data:

Interpretation:

It is

quite

common

be 16 times the baud

SERIAL

x 16

rate:

CLOCK SIGNAL
Data
15
1

Serial

10 11

12

13

14

15

Clock Signal

Serial Data:

Interpretation:

64 times the baud

Serial

rate

is

also a frequent option:

SERIAL x 64

CLOCK SIGNAL
Data
Clock
Signal:
Serial

62 63

31 32

33 62 63

31 32

33 62 63

Data:

Interpretation

5-53

The reason

possible to the for having x16 and x64 clocks is to get as close as signal. center of a single digit time interval when sampling the serial data clock signal does not necessarily The fact that serial data needs a companion mean that all serial I/O requires two signal lines. The accompanying clock signal does you set up a serial data communicanot actually have to be transmitted on a companion wire. not have to tions interface, with a predefined baud rate, then receiving device logic does
If

receive a companion clock signal. Receiving device

nal,

logic

can create

its

own.

local clock sig-

synchronizing

it

with a transition

in

the serial data

line:

Synchronize here
i; Serial

Data

Clock Signal:

Serial Data:

Interpretation:

Special synchronizing
In

digit

the illustration above, the Serial Data signal

is

is

permanently high

when

MARKING

not transmitting data; this

often referred to as Marking.

Note that

when using a x 16 or x64 clock signal, the receive clock can be one or two pulses out of phase with the transmit clock and no harm will be done. The receive sampling point will simply
be skewed a
little

off center.
is

If

a single synchronization binary digit

insufficient,

how about

a synchronizing digit pat-

tern?

We

can, for example, define a special synchronization serial data

state that every serial data stream

bit

sequence and

set

up

rules

which

must be preceded by

this

synchronization pattern:

Receiving clock synchronization

Receiving

Clock Signal:

Serial Data:

"^j

i_m
illustrated above does

r
Synchronization
bit

Interpretation:

pattern

The synchronization pattern

form
illustrated;

exist,

in

the

and is referred to a
serial

SYNC

character.

Specifying that a characters

is

data stream must use synchronization digits or

SYNC CHARACTER PROTOCOL

IN

serial

many rules that we must impose on order to ensure that the receiving device correctly interprets the transmitted data. This set of rules is referred to as "communications protocol".
just the first of

SERIAL

data streams

in

DATA

Every

serial

I/O data

link

must have

communications

protocol, since the serial data

line

must be

completely self-defining. Unlike

control lines

parallel I/O,

the serial data

cannot always be accompanied by any

instant.

which

tell

the receiving device

how

to interpret the data at

TELEPHONE LINES
dealing specifically with telephone lines, consider the fact that the transmitting and receiving devices may continuously switch roles, as happens in any voice telephone conversation. While talking, you are the transmitter; while listening, you are the
receiver.

When

5-54

Similarly,

when

transmitting- serial data over

telephone

lines

two-way communication

will

almost

always be required.
If a single telephone line is used to transmit data in both directions then communication is said to be half duplex. If

HALF DUPLEX
FULL

two telephone

lines
line

connect the transmitting and receiving

in

devices, with each

only,

being dedicated to data transfer

is

one

direction

DUPLEX
in

then communication
of
full

said to be

full

duplex.
is

The advantage
proceed
in

duplex telephone communication

that data transfer

both directions can

parallel.

ERROR DETECTION
Whether
serial

data

is

being transmitted over telephone

lines,

or directly

between

a transmitting

and a receiving device,

If

we must

check

for errors

in

transmission.

spurious data signals find their

way

into the serial data line, the receiving

device must have

some means
At

of determining that errors

have crept

into the data.

a primitive level, the parity bit

does

this job.

Since the parity

bit

has

PARITY
BIT
all

been set

or reset, to ensure that the total

the data unit is either odd or bits will be detected. Here are some examples, assuming odd
parity bit
is

number of 1 bits in even, then an odd number of error

parity; in

illustrations,

the

shaded and

error bits are starred:

Transmitted

Received

101101106
10110110:
100101 10i

100101108
1

Even

parity, error

detected

-1010110

Odd
Even

parity,

no error-detected
detected

100101 101

parity, error
parity,

100101101

01101001$

Odd

no error detected

An

additional technique used to check for errors in transmission is to append a "cyclic redundancy character" at the end of data stream segments. The cyclic redundancy character is a numis

CYCLIC

REDUNDANCY CHARACTER

ber created by dividing the transmitted data stream by a fixed polynomial.

Here

one commonly used 17 binary

digit divisor:

11000000000000101
The
result of dividing this divisor into the transmitted data stream, treating the transmitted data

stream as one continuous binary number, becomes the Cyclic Redundancy Character. The receiving device multiplies the received data stream

by the Cyclic Redundancy Character.

exist.

If

the result

is

not the standard

divisor,

then an error must

The

Redundancy Character is just one rather simple method used to track down errors in complex methods have been devised not only to track down errors, but also to determine exactly what the error is can be corrected. Entire books have been written so that on the subject of error detection and correction, therefore we are not going to discuss the subject
Cyclic

transmission. Very

it

any

further.

SERIAL INPUT/OUTPUT PROTOCOL

Let us

now

tie

together the miscellaneous necessities of

serial

data transfer which have been de-

scribed thus

far.

Generally stated, serial data communications protocol can be divided into synchronous and asynchronous categories. You will find protocol easier to understand you
if

5-55

approach synchronous and asynchronous data communications as two separate and not minor variations of a single concept. tities

distinct en-

SYNCHRONOUS SERIAL DATA TRANSFER

The
conforms exactly to a clock
the transmitting device

principal characteristics of synchronous, serial data transfer is that the data signal. Having once established a serial data transfer baud rate,

MUST

transmit a data

bit at

every clock pulse; therefore the receiving

device

knows

exactly

how

to interpret the serial

data signal:
I

Serial

Data

Is

Interpretation:

For example,

if

300 baud
the

serial

synchronous data

device can

slice

serial

data signal into

transfer has been specified, then the receiving 3333 microsecond segments, interpreting each seg-

ment as

a single binary digit.

We

earlier illustrated clock signals

with freguencies

1,

16 or 64 times the baud rate. x16 and x64

in

clock signals could be used with synchronous serial I/O, but

practice they are not.

How

is

the receiving device to

know

the bounds
100101
1

of

each data unit?

1

Serial data stream:

---01

Where
Clearly our

are the byte boundaries?

>

101 1000101

1--

synchronous protocol must define the length of

individual data units

and must

provide the receiving device with

character
is

used

for this

some way to synchronize on data unit boundaries. The SYNC purpose Every synchronous data stream begins with either

one or two

SYNC

characters:

SYNC

SYNC

01101001011010011011...

+
First

character of data

stream, and data unit boundary.

The data

unit in a synchronous, serial data stream usually consists of data bits without parity; but a parity bit may be present. Here is an example of a 9-bit data unit; eight data bits and a parity bit:

xxxxxxxxP

t_
Either

Parity Bit

Eight Data Bits

odd

or

even

parity

may be

specified.

Eight data bits need not always be transmitted; options allow 5, 6, 7 or 8 of the data bits to be meaningful. If less than eight data bits are meaningful, then the balance of high order bits are ignored. Here is an example of a data unit in which only 6 data bits are signifix x x x x x

t_

Parity Bit

(if

present)

Six Data Bits

Two

high order bits are ignored

and not transmitted

5-56

While waiting for synchronous, serial data to start arriving, a receiving device will enter a "hunt" mode, during which
it

SERIAL

continuously scans the

serial

serial

data input trying to match an incoming

If

SYNCHRONOUS HUNT MODE

it

data stream with the standard Sync pattern.

your protocol

calls

one Sync character, then the receiving device will start matched a single Sync pattern. More frequently, protocol will which case the receiving device will not start decoding data Sync characters.
for

interpreting data as
call for

two

until

it

soon as has Sync characters, in has matched two sequential

initial

We have already stated that synchronous data transmission

ting device to continuously

requires the transmit-

send data. What

if

the transmitting device does not have data

ready to send? Under these circumstances the transmitting

device will pad with Sync

characters until the next real character is ready to transmit. To illustrate this concept, consider an operator entering data at a keyboard; the keyboard transmits data using very slow, synchronous serial I/O. The operator has to key enter the message:
Good#morning)!$l\/lrj5Smith.
)6

represents a space character.

will

Since the operator

insert a

be entering data

at variable
is

speed, keyboard

serial

data transmission

will

Sync character whenever the operator

slow; thus the

message may be transmitted as

follows:

Go^o#d#6#mom2ing)&#M2r###Sm#ith
$ represents Sync characters.

When

the receiving device decodes a Sync character

it

in

the middle of a message,

serial

it

will

ignore

the character, but the next character.

will

remain

in

synchronization with the

data stream, ready to interpret

Assuming

that the

message

illustrated

above

is

being- transmitted
r

in

ASCII code, consider this

portion of the message:

^
Sync Char 2

The

binary parallel and synchronous serial equivalent

may be

illustrated as follows:

Sync
Char 3
1

Sync
Char 4 Char 5
1

Char

Char 3

---01001 101 101 101001 101

10010101 101001 101 101001 100101

r

101---

M
9
If

digit

characters including an odd parity

bit

are illustrated.

ASCII characters only are being transmitted, 8-digit characters, including 7 data digits and a parity digit may be used.

SYNCHRONOUS TELEPHONE PROTOCOL

Now in a real synchronous, serial data stream, when
lines,
First of

communicating via telephone

some
all.

additional information
to consider the
link

must be present.
of

we need

needs
is

two-way communication.
the transmitting

If

a serial data

communication

to work,

SERIAL DATA

HANDSHAKING device must be able to transmit commands and receive responses in dialog with the receiving device; this is the BISYNC only way of insuring that the transmitting device is ready PROTOCOL for the transmitted data or to tell the transmitting device that it must stop transmitting and start receiving. Following the Sync characters that begin and end any data stream, therefore, there will usually be some well defined control

5-57

characters which

protocol. For example. Standard

must be transmitted in both directions. This dialog is referred to as handshaking IBM 2770 Bisync protocol uses this handshaking sequence:

Wishing to transmit, send out an

I

enquiry

character

to

determine
is

whether the receiver

receive.

ready

to

Assuming

that

it

is

ready,

the

receiver sends back a |character] sig-

nifymg that

it

received the enquiry

and

is

ready to receive.

The

transmitter

now sends
it

character saying that

text.
It

is

|starting|

then sends a |block| of data,

that:
(1)

followed by a character

indicates thefendlof the block,

(2)

and

asks the receiver to check the

transmission
cyclical
relet

following

dundancy check characters and

the transmitter

know

if

there are any

transmission errors.

If

no

errors

have been detected, the

back
a
different

lMMMr
S

-
S

*-~
transmitter sends
its

receiver

sends

[character!] this

one
block,

says.

"Yes.

received

your
OK.

checked

it,

ECC

ECC

Characters
sent tram

found

it

TDATATRR
X

and

now

have
text

T X

DATA TRR

received

an

odd-nu nber

of

BCC

XCC T

Transmute
blocks from you".

tllll

The

usualptart*

of-text| character,
[text.j lf this is

followed by the
block of data to

the

last

be

transmitted,
is

an |end-of-tex t|
by
cycli-

character
cal

sent, followed

redundancy|check characters'!

D
L
1

(Characters
sent from
Receiver)

Assuming

that the
it

receiver found

no

errors,

sends

back

an

|acknowledging| character that says.

"Your

last
I

block

was

received

OK

T.
Upon
receiving this response and

and now

have received an even

number

of text blocks."

having nothing more to send, the

transmitter simply sends a Ispecial

end -of -transmission character| from

the
line.

Recognizing

the

special

end-of-

transmission character, the receiver

also disconnects

5-58

Within the telephone communications sequence, the

DATA

will

be transmitted using syn-

chronous

rules previously described:

X
ES
N

Additional requirements of telephone

ECCS
DATA
T
B
R

FCCE
DATA
V

T X

T"" ~Y~"'
V

^^C' "Y""'

T X

T
Strictly
serial

synchronous

data

ASYNCHRONOUS SERIAL DATA TRANSFER

When
serial data is transferred asynchronously, the transmitting device only transmits a character when it has a character ready to transmit. In between characters a continuous "break" signal, usually a high level, is output:

Mark
Serial Data:

Every data unit

own
is

in an asynchronous data stream must carry its synchronization information. An asynchronous data unit therefore "framed" by a single Start bit, and one, one and a

FRAMING
START
STOP
BIT

half, or

two Stop

bits:

BIT

single

asynchronous

serial

data unit

Stop bit(sU
Parity bit

Data

Framing

bits

bits

Start bit

Having a single
There
of
is

start bit

is

universally accepted in the microcomputer world.

bits

a similarity

between the synchronous data stream's SYNC characters and the framing

an asynchronous data stream.

characters frame a block of synchronous data characters. Start and stop
in

SYNC

bits

frame every

data character

an asynchronous data stream.

bits, 5, 6,
If

Of the eight data

chronous
serial data.

7 or 8

may be

meaningful, as was the case with syn

will

less than eight data bits are meaningful, the leftmost, high-order bits are
if

ignored. For example,

your protocol stipulates that there

only be five data bits

bits,

transmitted asynchronous word, then the receiving device

interpref

will

only receive five data

in each and will

each received word as follows:

single

asynchronous

serial

data unit
x x x x x

T.

Stop
Data

bit(s)

Parity bit
bits

Ignore these bits They are not transmitted.

Start bit

5-59

Thus a The

9-bit data unit

bit
is

is

actually transmitted.
parity

parity

always present. Either odd or even

may be

PARITY
BIT

specified.

1's are
stop
bits;

always used
one stop
serial 8-bit

for stop bits. Most frequently there

will

be two
bits,

STOP
BITS

bit is

then every

data

sometimes specified. If you have two stop word will contain twelve bits:

OxxxxxxxxPI

*T_

Stop
Data

bits

Parity bit
bits

Start bit

If

you have one stop

bit,

then every

serial 8-bit

data word

will

consist of eleven

bits.

Teletypes use one

bits

start bit,
.1

seven data

bits,

a parity bit

and two stop

--

for a total of

bits

per character. Teletypes operate at a standard

1

TELETYPE SERIAL

10 characters per second, which translates into

10 Baud.

DATA FORMAT
bit

Some transmission
and one
half

protocols specify one and a half stop bits. The stop

bit

width

is

one

times the normal

parity,

width.

Consider even
unit.

This

is

how

asynchronous serial data using two stop bits, with 6 data bits in each data sequence of parallel data will be converted into a serial data stream:

IU

II

iu
(

|o

[o

(o

,*A^ ,^Ao. /<^s 0110100111001101011100101101110100111011

S^S^mm^.

some form

synchronous serial data communications is occurring over telephone lines, then of handshaking protocol, as illustrated for synchronous telephone communications, is going to be required. In fact, there is nothing to prevent the identical
If
is

handshaking protocol from being used. Tins' protocol

tion

simply a

method

of transmitting informa-

between two devices

via a single

telephone

line.

Notice that during asynchronous data transfer the receiving device has an
additional

means

of checking for transmission errors.

The

first

binary digit

FRAMING ERROR

of every data unit

ary digits of the data unit

must be a representing the start bit; the last two binmust both be representing the stop bits. If the receiving device does not detect appropriate start and stop bits for any data unit in an asynchronous serial data stream, then it will report a framing error.
1

A SERIAL
Let us

I/O

COMMUNICATIONS DEVICE
SIZE

now

look at the requirements for a serial I/O interface device.

DUAL
First

IN-LINE
how

PACKAGE
some

of

all,

big should the DIP be?

We

our devices. Is there

rationale

which leads us to a

have been using 40-pin DIPs indiscriminately for all of larger or smaller package

size, or are

we better off simply standardizing on the 40-pin DIP, pins remain unused?
5-60

even

if

half the

we would like to use DIPs with as few pins as and they use up more space on a printed circuit card. Using a 40-pin DIP, where a smaller one would do, can have a snowballing cost effect: Fewer DIPs on a PC card can mean more PC cards. More PC cards can mean a larger backplane, a bigger power supply and a more expensive enclosure.
The answer
is

that

all

other things remaining equal,

possible. Bigger DIPs cost

more

to build

On

to insure that

makes no economic sense to have a bewildering variety of DIP sizes simply no DIP ever wastes a pin. For example, you are better off using a standard 40-pin DIP with two unused pins, rather than building an odd-ball 38-pin product.
the other hand,
it

this

For our serial I/O communications device we are going to select a 28-pin DIP since is one of the standard package sizes. We can get away with this smaller number of pins
serial

because our

I/O ports are going to shrink to

pin per port.

LOGIC DISTRIBUTION
two
Our

Synchronous and asynchronous serial I/O logic is going to share a single chip. The sets of logic have enough in common for this to make a lot of sense.
serial

faces:

communications I/O device may be visualized as having three interfor the microcomputer CPU and one each external asynchronous and synchronous serial I/O. Each interface will, as usual, have data lines and control signals. For the serial I/O interface, control signals can be grouped into general controls and modem controls. General controls apply to any external logic, whereas modem controls meet the specific needs of industry standard modems which does not prevent you from using modem controls for other external logic if you can.

One

THE CPU
Since the

We

SERIAL
is

I/O

DEVICE INTERFACE
to synchronous and asynchronous I/O, this
is

CPU

interface

common

where
The
bus data
buffer:

we

will begin.
is

serial

I/O device
lines

going to communicate

in parallel

with the

must therefore provide 8 data

pins,

CPU via the external system backed up by a data bus

DO

\
External

U2

System Bus
Data Lines

D3

CO
ro

w
CO

D4 D5 D6 D7

Other signals required by

parallel

the

CPU

interface are

no

different

from those

we

included

in

the

I/O interface device. Specifically, these are

in

operation

progress and

IORW

selects either a

IOSEL and IORW. IOSEL identifies an I/O 'read to' the CPU or a 'write from' the CPU.

5-61

Add

clock,

power and ground, and our

serial

I/O interface device looks

like this:

DO
D1
1

External

D2

\
a
CD
._

System Bus
Data Lines

-*-H

D3
D4

.Q

CO

D5 D6
D7

SEL

*
*"
Vdd
Vss
Vtjg
<l>

RW

THE SERIAL I/O INTERFACE We are going to use separate pins to transmit and receive serial data. Some devices
use a
Since
single, bidirectional data pin.

we have separate transmit and receive data pins, we will also need to input separate transmit and receive clock signals. Both clock signals are input by external logic to control
is

the rate at which data

being transmitted or received:

Receive Clock:

Jl_rL_TL
\
\
DO
D1
l

Receive Data:

i
2

D2
External
il

System Bus ius

Data Lines es

< >\ (
1 J
[

D3
D4

D5

d /

en

D6
D7

IOSEL

*
*Vdd
Vss
1

IORW

)i
RD
RC
1

<
<

Receive

serial

data data

^ ^
'

Vgg
<t>

Receive clocks
serial

TD
TC

Transmit
"Transmit

clocks ._
^

\
\

J
Transmit Clock

_rL_n_rL
i

/ 'i y /

Transmit Data:

5-62

If

external logic uses the

same

transmit and receive clock signal, you can

<t>

CLOCK
SIGNALS
serial

derive both signals from the system clock

In

or from any other clock logic.

any case these

two

clock signals are going to control the

will

serial data

baud

rate. Baud rate

will

not be determined by logic internal to the

I/O inter

face device and device logic

not generate or output clock signals.

Consider a synchronous data stream where every Receive Clock signal rising edge will strobe the Receive Data signal level, as a binary digit, into the Receive Data buffer Whenever the receive data buffer contains

SERIAL

DATA
INPUT

eight binary digits,

its

contents will be transferred to the Data

data entry:

Bus

buffer. Here

is

an

illustration of serial

Serial

1
Data

(o

Data Clock

Receive
Serial

Interpretation:

RD -

5-63

the loading process

The Receive Data

all

buffer

is

now

empty, so the next Receive Data

bit will start

over again.
trailing

Every Transmit Clock pulse

edge

will

strobe out a

bit

from the

SERIAL

Transmit Data buffer

The eight Transmit Data buffer

bits will
bit 7

be
has

output

in

ascending order starting with

bit 0. As soon as

DATA OUTPUT
to continue the serial

been output, the Transmit Data buffer will be considered empty, so the Data Bus buffer contents will be loaded into the Transmit Data buffer,
transmit process. Here
is

an

illustration of serial

data output:

V-,

DO*

'
Serial

'

J
Data Clock:

Transmit
Serial

Data

Interpretation:

*_

r
22 \

v^

DO

L\
no
^

Dl

\tt
JU*
Vgg

RD
"rc"

If

asynchronous

serial

data

were being

transmitted, the relationship

in

between Data Clock and

serial

Data signals would change, but that

x16 or x64 clock

bit.

Remember, and you sample the data on the 8th

is all.

an asynchronous data stream you use a

or

32nd pulse

in

the middle of the data

5-64

SERIAL

I/O

CONTROL SIGNALS

assembled data bytes and to Control logic and control signals which we are now going to describe determine which of the possible operations is occurring at any time. The serial I/O interface device will simply ignore the clock signal internal control logic has not been programmed to recognize Also, the Receive Data buffer contents will simply be lost the Data Bus buffer is not ready to receive an assembled byte.
transmit data bytes for disassembly
if
it.

The data bus

buffer cannot be used simultaneously to receive

if

Let us consider the control signals which must be present to support serial data being transmitted and received.

consider transmit logic; it will need two control SERIAL one to indicate that the Transmit Data buffer is TRANSMIT empty, the other to indicate that the Data buffer is ready to CONTROL receive another byte of data. We will call these two signals TE and SIGNALS TRDY. The two signals are not identical. For example, when serial data is being output synchronously, TE will be high while a SYNC character is being output; yet TRDY
First of
all,

signals,

will

be low

to indicate that the

is

Transmit Data buffer

is

indeed ready to receive another data byte,

the

even though data

used:

currently being output. Here

is

way

that

TE and TRDY

signals will be

Transmit

Serial

Data

DGEEX
U

SYNC

DATA

Tl TRDYTl
will call

L__
now
be read.

3CDC U IT U IT
SERIAL RECEIVE

Receive logic uses a single Receive Ready signal which we RRDY. This signal tells the CPU that a byte of data has been

loaded into the Data Bus buffer and can

CONTROL
SIGNALS

Frequently, the RRDY signal will be used to generate an interrupt request. The interrupt can be acknowledged by a very simple instruction sequence that moves the received data byte into an appropriate microcomputer system
read-write

memory

location.
is

When
serial

synchronous data

being received,

remember

that the

I/O interface device logic must detect one or two

the

SYNC
must

SERIAL RECEIVE

characters before acknowledging valid data. External logic

know when
characters.

serial

I/O device has detected these

SYNC

SYNCHRONIZATION CONTROL

We will therefore add a SYNC control signal, which will be output true as soon as the SYNC characters have been detected. Some serial I/O devices allow the SYNC control line to be bidirectional. In this case, rather than preceding synchronous data with SYNC characters, external logic can input the SYNC
control signal true; then the synchronous data:
Serial
serial

I/O device uses

this control pulse in

order to start receiving

Data

In

SYNC,

nfM^-r^
First bit

Receive Clock.
of
first

byte

5-65

MODEM CONTROL
Only the
DSR
data.

SIGNALS
be described. There are these four
whenever
in-

control signals remain to dustry-standard modem control signals:

1)

modem

(Data Set Ready)

--

The

modem

drives this signal low

it

is

ready to receive

The

signal

is

input high at other times.

Any

other external logic can use this signal as a

at a unit

master enable/disable. For example, an on/off switch

before attempting to communicate with
2)

such as an external video

ter-

minal could generate this signal. This allows the microcomputer system to test external logic
it.

DTR
it

(Data Terminal Ready)

serial

--

This control signal

is

the

serial

I/O device's equivalent of DSR;

it

is

output by the

I/O interface device to

tell

external logic that

is

ready to communiI/O operations, or

cate.

Under program
it

control

you can set

this signal

high to inhibit

all

serial

you can set

3)

low

to initiate serial
--

I/O operations.
t

RTS (Request To Send)

Wh en

he

serial

I/O device
will

is

ready to communicate with a

modem
device
4)

or other external logic.

DSR and DTR

it

both be low.

Now

the serial I/O device

that the receiving

uses the RTS signal to indicate that

is

ready to transmit data.

it

Remember

may be

temporarily busy, even though

-- In

has been turned on.

the transmitter

CTS

(Clear
if

receiver;

To Se nd) RTS got

full

duplex data
the

link,

RTS from

becomes CTS

at

the
of

sent, then clearly there

link,

must be a

modem

at the line

en d capable

receiving.

In

a half duplex data

modem

receiving

RTS sends back CTS two

millise-

conds

later.

The interaction of DSR, DTR, RTS and CTS may be gram flow chart:
Set

illustrated

by the following pro-

DTR

low

Output RTS

5-66

This

is

how

our serial interface device

now

looks:

Externa

^RTS

System Bus
Data Lines
OSR

-sync
J*-TRDY

K-

Receive

serial

dala

Transmit clock

CONTROLLING THE SERIAL

I/O

INTERFACE DEVICE

Given the many options available when using the serial I/O interface device, we are going to need a Control Register in order to select options and in some cases to determine the conditions of control signals being output.

First

we must

select

synchronous or asynchronous

I/O; then Table 5-1

SERIAL

I/O

identifies the
trol

We

fundamental decisions we must make under program conwill refer to Table 5-1 variables as mode parameters,

MODE

since they are unlikely to be

changed during the course

of

any

serial

I/O operation.

FUNCTION
Clock frequency

ASYNCHRONOUS
Baud
rate x1.

SYNCHRONOUS
Usually baud rate x1
5,

x16 or x64

Data
Parity

bits

per byte

5, 6, 7. or 8 Odd, even or none

1,

6,

7,

or 8

Odd, even or none

Stop

bits

Viz

or 2

Does not apply

1,

Sync characters

Does not apply

Table 5-1. Serial I/O

2 or external

Sync

Mode

Parameters

Asynchronous I/O using a x1 clock is sometimes called isosynchronous I/O; equivalent to transmitting data using is
it

ISOSYN-

CHRONOUS
SERIAL SERIAL
I/O

asynchronous character format (including framing synchronous data stream.

bits) in

an otherwise

Within any selected set of mode parameters, the Serial I/O Interface device must still receive commands. Commands must
identify the direction of serial data flow (transmit or receive), or terminate

I/O

COMMANDS

current opera tions allowing the

,

mode

to

be modified.
to

Commands must
error conditions.
of,

also set the condition of

the

DTR and RTS

control signals,

and respond

any

What
is

are the error conditions that

commands must
them?

take care

and

how

SERIAL

I/O

the microcomputer system to detect

We
we

will provide the

Serial I/O Interface device with an 8-bit Status register. Having

8 -bits,

ERROR CONDITIONS

we

conditions.

can read a combination of eight input signal statuses and error must be able to read are: The input signals whose level

5-67

1)

DSR
CTS
for

2)

Data set ready.

Clear

To Send. This
I/O interface

register; Serial

sometimes left out of the Status device logic must then automatically wait
signal
is

SERIAL INPUT

I/O

CONTROL
SIGNALS

CTS

true before initiating a serial data transfer.

3)

SYNC
TE

External synchronization.

4)
5) 6)

Transmit buffer empty.

buffer ready to receive data from the

TRDY
RDY

Transmit Receive
and

CPU.

buffer ready to send data to the CPU. This signal

may be connected

to in-

terrupt logic

left

out of the Status register.

These are the

1)

error conditions that

may be
in

reported:
a serial data unit.
bits

Parity error.

The wrong

parity

was detected
start

2)

Framing
Overrun

error. In error.

asynchronous mode,

and /or stop

were not

correctly detected.

3)

The Receive Data

buffer transmitted a byte of data to the Data

data.

Bus

buffer,

which was not ready to receive

The data has been

lost.

Normally an error condition does not cause a Serial I/O Interface device to abort
operations. The
error
is

reported

in

the Status register and operations continue undaunted.

Using commands,
1)

we

will react to
a

an error condition

in

one of these ways:

In

Synchronous mode, send

NAK

(no acknowledge) character back to the transmitting

source.
2) 3)
In

Asynchronous mode, abort operations and set TD

to

its

"break" signal

level (usually high).

Execute any other error recovery program.

Reset any error
bits in

4)

the Status register of the Serial I/O Interface device.

To our

Serial I/O Interface device Status register

we must now add a

Mode/Control register and a

TRDY
Receive
serial

data

Receive clock Transmit

serial

data

Transmit clock

ADDRESSING THE SERIAL

The only aspect
the device dressed.
is

I/O

INTERFACE DEVICE

of the serial I/O Interface device that we have not covered is how going to be selected, and how its buffers and registers are ad-

far as the CPU logic is concerned, the device consists of the Data Bus buffer, the Control register and a Status register.

So

data, respectively; they

direct access.

The Receive Data and Transmit Data buffers lie passively in the path of received and transmitted communicate with the Data Bus buffer, therefore do not need additional

In reality

the Control and Status registers can be looked on as a single addressable unit, since you
into a Control register

can only write

and you can only read from a Status

register.

Thus,

we
is

which
register:

only need two pins just as well, because

in

order to access a Serial I/O Interface device we only have two pins left. One pin (CS) will constitute

a chip select, while the other pin (RS) selects either the Data

Bus buffer or the Control /Status

/ 1 1

DO
D1

_^

1
External

1 D2
System Bus <
Lines

W
I

D3 D4

\ |co ^

1 D5
1
1
1

'cr

a
T

D6

D7
c

W
^
RD

TF

TRPY
Receive
serial

Vdd
Vss

o
<_>

^
w

data

"D

Vgg

*
Since

CO

RC
.

TD
TC -^

Transmit

serial dat.

Transmit clock

we

only have

two

pins to address the Serial I/O Interface device,

lines,

some

external logic will

in

be reguired to appropriately decode address

to create the

external Data bus lines or control lines

is

order

CS and RS

select signals.

Use
this

of

such external select logic

In reality,

the rule rather than the

will

exception within the microcomputer industry.

dress
In
lines,

I/O interface devices

parallel

not have 8 ad-

as

we

indicated earlier

in

chapter for the

I/O interface device.

may be

Figure 5-18 we can now illustrate one way in which a serial I/O interface device integrated into our hypothetical microcomputer system.

REAL-TIME LOGIC
The concept of vious example
easy enough to understand. The most obtime of day by a microcomputer system that is driving an employee badge reader, and must therefore record the exact time when each employee enters and leaves his place of work.
real-time logic
is is

one that

is

the maintenance of

real

At the other end

rotation

of the time scale, a

mrcrocomputer may

drive an instrument that

in

measures the
of revolutions

speed

of a

drum, fan or propeller, and reports rotation speed

thousands

per minute.

microcomputer will have no difficulty keeping track of real time of day since the whole microcomputer system is driven by a clock signal. All that is needed is to add some logic which counts clock signals and generates an interrupt request after a specified num-

ber of signal counts. For example,

if

a clock signal has a period of

millisecond time interval could be clocked by generating an interrupt evey

course,
if

the microcomputer clock signal

is

is

going to be used to

500 nanoseconds, then a one 2000 clock periods. Of measure real time of day, then a
is

very precise time interval

required.

When

used

in

an application that

not time-sensitive, a

5-69

microcomputer may have a very inexpensive crystal generating its clock signal. Indeed, cases a resistor-capacitor network may be used in the place of a crystal:

in

.some

Some

of the

microcomputers described

in

Volume

II

provide a programmable timer as an integral

all

part of device logic.

When
to the

using other microcomputers,

that

is

needed

is

some form

of pulse

count logic external

number

of

microcomputer system, generating an clock periods have been counted.

interrupt request after a fixed

LOGIC DISTRIBUTION AMONG MICROCOMPUTER DEVICES

The
individual devices that we have described in this chapter fairly represent the bulk of microcomputers being sold today. However, there is no reason why logic should be distributed among different devices as described; and if you look at the real devices described in Volume II, you will see that there is indeed wide variation between the logic that one microcomputer manufacturer will implement on single chips as compared to another.

tradeoff is power versus number of devices. At any given time semiconductor manufacturers can implement a certain number of gates worth of logic on one chip. What this logic should be is the chip designer's business. Nothing but tradition says that a Central Processing Unit and memory must be implemented on separate chips. There is no economic or scientific reason defining

The

chip/logic relationships.

What happens,

in reality,

is

that a chip designer begins by designing a Central Processing Unit.

is faced with an important tradeoff; presuming that technology has advanced to the point where he can now put 30% more logic on his chip than the last, time around, what is this extra 30% to be? Should the new CPU have a more powerful instruction set with a lot of minicomputer-like addressing modes, or should the instruction set remain the with the extra logic being devoted to read-write memory? Or how about using the exsame tra logic to put some parallel I/O on the CPU chip?

Immediately the chip designer

In reality
It

the

amount

of logic

which can be crammed onto

a single chip

is

increasing very rapidly.

we are likely to see an equally rapid evolution in microcomputers, with a diverging trend At one end of the spectrum we have already reached the one-chip microcomputer, where a minimum representation of all the different logic devices described in this chapter have been crammed onto a single chip. At the other end,
is

for this

reason that

we

are seeing microcomputers that exactly reproduce minicomputers.

therefore, conclude this chapter with a caution: The segregation of logic on different devices, as described in this chapter, is nothing more than a very approx-

We,

imate guideline; and as time goes by, you will see more microcomputers merging logic onto a very few, or even one device.

5-70

ID

"D .C

Sl^imO:

,r-

<

<

I<<<<<<<<<

tou)wl

iiiiiiiiiiiJiiiiifT^C

(1)

T!
tl)

(/)
C_

>

C)
(I)

<

_) LL

5-71

Chapter 6 PROGRAMMING MICROCOMPUTERS

Instructions are used to specify any logic sequence that may occur within a microcomputer system. For example, an instruction may complement the contents
of the
ry

CPU's Accumulator register or move data from the Accumulator to a memoword or output data via an I/O port.

To use

a microcomputer, therefore, you must first select the devices that will give you sufficient logic capability; then you must sequence the logic to meet your needs, by creating a sequence of instructions which, taken together, select chip logic capabilities that satisfy the needs of your application. The instruction sequence is a program, and programming is the creation of the instruction sequences.

THE CONCEPT OF

A PROGRAMMING LANGUAGE
The concept
microcomputer program was introduced instruction, binary addition program was described.
of a
in

Chapter 3, where a

five-

This chapter discusses the types of instructions which a real microcomputer system will need, and how programs are really written. In fact, a discussion of how programs are written must precede the discussion of instruction types, since we are going to use programming terminology in order to describe instructions.

There

is nothing to prevent you from creating a computer program as a sequence of binary instruction codes, just as they will appear in memory, or in the Instruction register. The addition program described in Chapter 4 can be written out in binary or hexadecimal digits as

follows:

Program As
10011100 00001010 00110000 01000000 10011100 00001010 00110001 10000000 01100000

Hexadecimal
Version of Program 9C

Binary Matrix

0A
30 40 9C

0A
31

80 60

Were you
is

to generate your

chances of misplacing a
unfortunate since
is
it

or a

microcomputer program directly as a sequence of binary digits, the are very high; and the chances of spotting the error are low. This 1
for a

is

not

enough

program

to

be 99.99% accurate. Unless

manifest
itself at

it

is

absolutely

accurate, there

always the lurking

possibility that the error will

It

an inopportune

moment, with disastrous consequences. is this inherent necessity for perfection that causes programmers to grasp at any device which makes errors harder to create and easier to spot.

As compared to creating a program as most obvious improvement would be

a sequence of binary digits, the first and to code the program using hexadecimal

6-1

digits,

then find some automatic

way of converting the hexadecimal digits to their

makes
digits.
it

binary equivalent.
Writing the program
in

hexadecimal

digits

harder to generate errors, because there

is

one hexadecimal

digit for

every four binary

On

the theory that every digit offers an equal

likely to

probability of being written

down

wrong, programming

one quarter the number

Programming
hexadecimal
in

of errors,

in hexadecimal digits is because there are one quarter the number

generate

of digits.

in

hexadecimal

digits also

makes

errors easier to spot, since detecting a misplaced

in

digit,

while not the simplest thing

the world, surely beats spotting a

wrong

or

mesmerizing binary pattern. The binary and hexadecimal programs are reproduced below,
error.

each having one

See

how

long

it

takes you to find the errors:

Program As
10011100 00001010 00110000 01000000 10011100 00001010 00011001 10000000 01100000
In

Hexadecimal
Version of Program

Binary Matrix

9C

0A
30 40 9C

A0
31

80 60

the end, however, the program must be converted into a binary sequence, because
is

that

how
in

it

is

going to be stored

in

memory

and

that

is

how each

instruction

must be

repre-

sented

the Instruction register.

SOURCE PROGRAMS
teletype, or any other terminal with the appropriate keyboard, generates ASCII character codes in response to keystrokes; therefore, let us assume that a program written in hexadecimal digits will initially be generated as a sequence of ASCII character codes.

Hexadecimal

digits are

represented by the digits

through 9 plus the

letters

through

F.

The

ASCII codes for these digits are extracted from Appendix A:

Hexadecimal
Digit

ASCII

Code
00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 01000001 01000010 01000011 01000100 01000101 01000110
of paper, using hexa source program.

2 3

4
5 6
7

8
9

A
B

D
E F

Suppose you write the binary addition program on a piece

adecimal
digits,

as illustrated

in

Figure 6-1. This

6-2

is

9C

OA
30 40

9C

OA
31

80 60
Figure 6-1.

Source Program Written

On Paper

This source program must be converted into a form that can be loaded into and executed. One way of doing this uses paper tape.

memory

PAPER has eight "channels", representing the eight binary digits of a byte. A hole punched in any channel represents a 1, TAPE while the absence of a hole represents a 0. Ten bytes are represented by one inch of paper tape. In other words, every 0.1" of paper tape represents one byte, as follows:

A paper tape

One
Usually a line of sprocket holes appears
to a toothed

Byte
3;

between Channels 2 and

tape.

the sprocket holes are used

wheel

to

advance the paper

OBJECT PROGRAMS
Our goal is to convert the source program, illustrated in Figure 6-1, into a paper tape, as illustrated in Figure 6-2. The paper tape in Figure 6-2 is an exact representation of the binary instruction codes that will be stored in memory; digits are represented by holes, and
1

digits are

represented by a lack of holes.

The program

illustrated in Figure 6-2

is

called

an Object program. Paper Tape

Binary Equivalent

10011100 00001010 00110000 01000000 10011100 00001010 00110001 10000000 01100000

Figure 6-2.

An

Object Program

On Paper Tape

6-3

CREATING OBJECT PROGRAMS

Converting the source program of Figure 6-1 into the object program of Figure 6-2 a two-step procedure.
First
is

the hexadecimal digits illustrated in Figure 6-1 are entered at a keyboard. We it is a teletype keyboard. Each digit becomes an ASCII code on paper tape, as illustrated in Figure 6-3.
will

assume

Paper Tape Source Program

Source Program

As Written on Paper

9C

OA
30
40

9C

OA
31

80 60

CD

CD

CD_CD_CD_C_D_cp_CD_

M U ^
Figure 6-3.

Ol

si

Paper Tape Source Program

You could create the paper tape illustrated in Figure 6-3 by simply turning a teletype punch on, then depressing appropriate
keys at the keyboard.

EDITORS

You could get

a little more fancy by attaching the teletype to a computer, which executes a program to read keyboard data and punch paper tape. This program is called an EDITOR.
Using an Editor program to create source programs is a good idea. For example, the Editor program could be written to ignore any key that is not a valid hexadecimal digit (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F). Since a teletype can read as well as punch paper tapes, the Editor can read
old source

program paper tapes,

let

of the source program. This saves the time

you make corrections, then punch out the corrected version you would otherwise spend rekeying the error-free

portions of the source program.

Having tised an Editor to create a source program on paper tape, as illustrated in Figure 6-3, you will execute another program which automatically reads the source program and creates an object program equivalent; for the moment we will refer to
this as a

CONVERTER

program.

6-4

With reference to Figures 6-2 and 6-3, the

as follows:
1)

logic of the Converter

program

is

quite simple

and

is

Combine

the rightmost (low order) four bits of every pair of source program bytes into one

object program byte.

2)
If

Channels

through 3 of the source program contain 001

7 as
is.

1,

discard these four bits and use

Channels 4 through
3)
If

Channels

through 3 of the source program contain 0100, discard these four

in

bits

and use

9 plus the contents of the four bits

Channels 4 through
as follows:

7.

These three

logic steps

may be

illustrated

Source Program As Written On Paper

discard

Source Program

From Figure 6-3

0011

Object Program In Figure 6-2

40

0A

discard 0100, but add 9 +

=A
directly into
II

The object program paper

tape, as created

by the Converter program, can be loaded

memory to be executed. Chapter 20 of "An Introduction To Microcomputers: Volume Some Real Products" describes how this is done for microcomputer systems.

in

PROGRAM STORAGE MEDIA

You do not have
fact,

to

use paper tape as the

unit, is

medium

for creating

source and object programs,"

only the simplest microcomputer systems

medium, such as a disk

other data).

Usually a magnetic used to store source and object programs (or any
will

use paper tape.

ASSEMBLY LANGUAGE
Why are
hexadecimal
digits digits

more

efficient

than binary digits as a programming

medium? Because

hexadecimal

make

the programmer's job easier, leaving the hard job to the computer.

Easing the programmer's job

significant efficiency.

by making
is

errors harder to introduce

and easier

to spot

is

Making the computer convert a hexadecimal source program

executing a Converter program

into a binary object

program

by
will

an insignificant penalty, because the Converter program

execute

in

seconds, or

(at

most) a few minutes.

Let us take this line of reasoning a step further.

digits,

we will use a programming

language which

Instead of programming in hexadecimal is even simpler for the human pro-

grammer to comprehend.
The programming language source will be very unlike a binary digit object program, so the Converter program, which converts the programming language source program into a binary object program, becomes more complex; but that remains an insignificant penalty.

6-5

What
rors

a programming language tries to do is eliminate syntactical programming erdigit, the wrong instruction code leaving only logic errors, specific to the application, as the programmer's responsibility.

the misplaced
is

Assembly language
by the

the

first

step into programming forms more easily understood

human programmer.

ASSEMBLY LANGUAGE SYNTAX

The assembly language of any mini tions, each of which occupies one
Label

or

microcomputer consists

of a set of instrucline

line of

the source program. Each

may be

divided into four parts, or fields, as follows:

Mnemonic
LIM

Operand
DC0.ADDR1
H'OF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION

HERE

LMA
AIA BZ

OUT
DCO HERE

SRA
INC

JMP OUT

Every source program instruction represents one object program instruction.

MNEMONIC
FIELD

Consider
Label

first

the mnemonic

field,

which may be highlighted as

follows:

Mnemonic
LIM

Operand
DCQ.ADDR1
H'OF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION

HERE

LMA

ill

mm
OUT
The.
only

OUT
DCO
HERE

field is the most important field in an assembly language instruction, and is the This field contains a group of letters which constitute which must have something in a code identifying the source program instruction. field
it.

mnemonic

ASSEMBLER The converter program used to convert assembly language source programs into binary object programs is called an ASSEMBLER. The Assembler reads the mnemonic field, as a group of ASCII characters, and substitutes the instruction ary code in order to generate an object program.
Consider the instruction specified by the

bin-

mnemonic SRA.

This instruction performs the

in

operation as Instruction 5 of the binary addition program described

Chapter

4,

same where is
it

shown

using the instruction code 60 16 The Assembler must therefore have logic which gener.

ates the instruction code 60 16

instruction:

upon encountering SRA

in

the

mnemonic

field of a

source program

Binary form of

Binary form of

Source

ASCII

mnemonic

Object program created

Program
S R

seen by Assembler

by Assembler

01010011 01010010 01000001

Assembler
logic

00110000

6-6

Note carefully that only the binary instruction codes of a microcomputer, that is, the object code, are sacred and unalterable. The source program mnemonics are arbitrarily selected and can be changed at any time simply by rewriting the Assembler to recognize the new source program mnemonic.
Every microcomputer's programming manual
will
is

define

instructions

using
is

source program

mnemonics. The
the fact that only

fact that selection of

in

mnemonics
different

a very arbitrary business

demonstrated by
to

rare

cases

will

two

microcomputers use the same mnemonic

identify instruction

codes that do the same

thing. In fact, the selection of instruction

mnemonics

can

become

a very

set of instruction

emotional issue. Many Intel 8080 users, for example, have created their own mnemonics and have gone to the trouble of writing their own Assemblers to

recognize their

new mnemonics.
mnemonic
is

Consider the use of more than one

to represent the

same

instruction.

We

have
.

just

shown how
.

the

mnemonic SRA

converted to the object program instruction code

60 16 Another Assembler could be written to convert the mnemonic XYZ to the object program instruction code 60 16 A third Assembler could be written to convert either SRA or XYZ to 60 16
.

The mnemonics used

microcomputers.

in

this

chapter have been selected as typical of those used by

real

The mnemonics LIM, LMA, AIA, BZ, SRA, INC and JMP come from the hypothetical microcomputer instruction set which is created in Chapter 7.

Next
Label

we

will discuss the Label field, which

is

highlighted as follows:

Mnemonic
LIM

Operand
DC0.ADDR1
H'OF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION
it. If

HERE

LMA
AIA BZ

OUT
DCO
HERE

SRA
INC

JMP

OUT
The
label field
field,

may
it

or

the label

is

may not have anything in there is anything in means of addressing the instruction. In other words,
its

LABEL
FIELD

you do not

identify

an instruction by

location

in

program memory

(as

we
in

did

in

Chapter

4),

because

at the

time you are writing the program, you

may

not

know where

memory

the instruction

will finish up.

This being the case, you give the instruction a name, or

label.

Refer to the example above. The instruction labeled

there
is

HERE must be

identified,

because

later

on

an

instruction

which

specifies a

change

of execution

sequence. The

instruction:

HERE
specifies that the instruction labeled
instruction:
it

.RETURN FOR NEXT BYTE

HERE

is

the next instruction to be executed. This

a label

is

Jump

may be used

to illustrate

what

means by drawing

the following picture of

program execution sequence:

Label

Mnemonic
I

Operand
DC0.ADDR1
H'OF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION

LIM

HERE-

-LMA
Al^ BZ

OUT
DCO HERE

SRA
INC

JMP

OUT

6-7

The Assembler is going to have to keep track of where because the Assembler is going to have to replace every

in

memory

instructions will finish up.

label with

an actual

memory
is

address.

Suppose the object program form of the above assembly language source program occupy memory words as follows:
Object

going to

Program

Memory
Locations
03FF.0400. 0401

Label

Mnemonic
LIM

Operand
DC0.ADDR1
H'OF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION
.

0402 0403.0404 0405.0406 0407 0408 0409.040A 040B

HERE

LMA
AIA
BZ

OUT
DC0 HERE

SRA
INC

JMP

OUT
will

The Assembler The

assign the value

0402

to

HERE, and 040B to OUT.

.

binary instruction

value

0402 16

code for the JMP instruction happens to be BC, 6 the label HERE has the then the Assembler will convert the source program instruction:
If

JMP
to the three object

HERE

program bytes:
BC
04
02

If

you moved the program, so

that the object

code

for:

HERE

LMA
^

now

occupied

program memory byte with address 0C7A 16 then the Assembler would convert:

JMP
to the three object

HERE

program bytes:
BC 0C 7A

The Operand
Label

field

may be

highlighted as follows:

OPERAND
FIELD

Mnemonic
LIM

Operand
QC&,ADDR1
H'OP-

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION

HERE

LMA
AIA BZ
Oti?

SRA
INC

JMP

wmm

DCO

OUT

6-8

H'OF'

means 0F 16 You cannot use subscripts must be selected.

.

in

a source program, so a reasonable alternative

Usually, but not always, the

operand

field

provides information which the Assembler

will

use to

create the second byte or second and third bytes of an instruction that requires

more than one

byte of object program code. For example, suppose the source program instruction:

LIM

DC0.ADDR1
illustrated in

is

instruction

of the binary addition

program

Chapter

3.

The Assembler

will interpret

the source program instruction as follows:

Address

of

Memory Word
0400
0401

Memory Word
9C

0A
30

LIM

DCOADDR1

Instruction

0403 0403
There
is

40
that the

no

rule

which says

object program instruction code bytes.

operand must specify or can only specify second and third The Intel 8080 microcomputer, for example, has seven ac-

cumulator-type registers and a single instruction which moves data from one register to another.
This source program instruction
is

written as follows:

MOV
where
and
But the

D.S

D
S

specifies the destination register.

specifies the source register,
field.

D.S constitute the operand

MOV
7

instruction creates just this

one object program

byte:

10

-Bit

No.

|6|1|D|D|D|S|S|S|
These three
These three
bits identify

H
the

the source register.

bits identify the destination register.

These two

bits identify

the instruction as a

MOV

instruction.

Now

look at the contents of the operand fields in the program

we

are illustrating

in this

chapter.

DC0.ADDR1

DC0 identifies the Data Counter into which immediate data must be loaded. ADDR1 is a label representing the address which must be loaded into the Data Counter. The Assembler will convert ADDR1 into a 6 -bit binary data value.
1

H'OF'

specifies

immediate,
for

hexadecimal two-digit value 0F, 6

The

instruction

mnemonic AIA stands

in

AND

Immediate. This combination of

mnemonic and
has the effect of

operand cause whatever

the operand

is in

the Accumulator to be

ANDed

with the actual value

.

field. In this

case, since the

operand

field is

0F, 6

it

setting to zero the high order four bits of the

accumulator while leaving the low

order four bits of the Accumulator as they are.

OUT
and

appearing
instruction:

in

operand

fields, identify instructions

with labels

OUT and

HERE. The

HERE
BZ

OUT

;JUMP OUT

IF

RESULT

IS

ZERO

specifies that

if

the Accumulator contains a zero value following the

AND

Immedinor-

ate instruction, then the next instruction to be executed

must be the

instruction

with label OUT, not the

mally be executed next.

SRA
The

instruction which, following sequentially,

instruction:

would

HERE
states that the next instruction to
tion

.RETURN FOR NEXT BYTE

instruc-

be executed must unconditionally be the

instruction executed.

with the label HERE, not the instruction with label OUT, which, following se-

quentially,

would otherwise have been the next

Counter whose contents
is

DCO

specifies the Data

to

be incremented.

The comment field contains information which makes the program easier to read but has no effect on the binary object program created by the Assembler. In other words, the Assembler ignores the comment field.
is the Assembler going to tell where one field ends and the next begins? Usually space codes are used to separate fields, and the Assembler uses these rules:
1)

COMMENT
FIELD

How

FIELD

IDENTIFICATION

All

characters from the

first

character on a line up to the

first

space code constitute the

label

field.

If

the

first

character

is

space code, then the

label field

is

presumed

to

be empty.

2) 3)

Contiguous space codes are treated as though they were one space code.
All

characters

between the

first

and second space codes

(or

contiguous space codes) are

in-

terpreted as the
4)
If

mnemonic

field.

the

thing that follows

5)
If

mnemonic does not require an operand, is comment.

the Assembler quits here, assuming every-

the mnemonic does require an operand, then the Assembler assumes that all characters between the second and third space codes (or contiguous space codes) constitute the

operand
6)

field.

Sometimes comment
for this purpose.

fields are

preceded by a fixed character.

We

have used the semicolon

Space code
Label

field delimiters

may be
Operand

illustrated,

according to the above

rules,

as follows:

Mnemonic
:

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT IS STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION

LIM

>'DC0.ADDR1.

HERE.

:: :

LMA-: AlA

::

BZ

: :

H-OFvXv OUT
:::-.

SRA
INC

::

:::

DCO
herf

:::

JMP-:

:::

:::

OUT

6-10

ASSEMBLER DIRECTIVES
An assembly language
illustrate

program, such as the seven-instruction sequence

instruction fields,

we
in

have been using to

assembly language

cannot be assembled as
told

it

stands.

To

give fixed,

bi-

nary values to labels

object program
will

OUT

and HERE, the Assembler must be

where

program memory the

eventually reside.

There

is

a class of instructions, referred to as

it

Assembler

Directives,
itself.

which you

will

use to provide

the Assembler with information that

In

cannot deduce
in

for

explaining

how

the labels

OUT

and HERE

the operand

field

would

be interpreted by the Assembler, we illustrated the program sequence occupying program memory locations beginning at 03FF. You would
specify this origin to the

ORIGIN DIRECTIVE

Assembler using an Origin assembler

directive as follows:

Label

Mnemonic

Operand
H'G3FF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT ISO STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION
Its

ORG
Lirvi

'DC0.ADDR1
H'OF'

HERE

LMA
AIA BZ

OUT
DCO HERE

SRA
INC

JMP OUT
The
the
origin

assembler directive generates no object code.

will

sole purpose

in

the program

is

to

tell

Assembler where the object code

be located
that

in

program memory, and thus

how

to

calculate the real binary Origin

memory addresses

must be substituted

for instruction labels.

END is the only assembler directive that is absolutely mandatory. DIRECTIVE Another assembler directive that is always present, because it makes the job of creating an Assembler easier, is the END directive. This is the last instruction in a program and tells the Assembler that there are no more executable instructions.
The END assembler
Label
directive

may be

illustrated

as follows:

Mnemonic
ORG
LIM

Operand
H'03FF'

Comment
LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT IS STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE

DC0.ADDR1
H'OF'

HERE

LMA
AIA

BZ

OUT
DCO HERE

SRA
INC

JMP END

The Equate assembler directive is one more that is universally present because it makes assembly language programming much easier. You use the Equate assembler directive to assign a value to a symbol or a label.
Consider the instruction.
AIA
H'OF'

EQUATE
DIRECTIVE

.MASK OFF HIGH FOUR

BITS

6-11

The operand H'OF' cou Id be replaced by

lustrated as follows

symbol which

is

equated to the value 0F 16 This

.

is

il-

Label

Mnemonic
:

Operand

Comment

VALU

ORG
LIM

Mm H03FF'
DCO.ADDR

HERE

LMA
AIA BZ

VALUE OUT
DCO
HERE

SRA
INC

LOAD THE SOURCE ADDRESS INTO DC LOAD DATA WORD INTO ACCUMULATOR MASK OFF HIGH ORDER FOUR BITS JUMP OUT IF RESULT IS STORE MASKED DATA INCREMENT THE DATA COUNTER
RETURN FOR NEXT BYTE NEXT INSTRUCTION
be used to assign a value to the address labeled ADDR1 did not exist as an instruction label some-

JMP

OUT

An Equate assembler

directive could also

this

ADDR1. However, you would only do where else within the program.
There are two mnemonics that appear
Constant and Define Address.

if

in

every assembly language and

DEFINE

are neither instructions nor assembler directives.

These

are the Define

CONSTANT
DEFINE

The Define Constant mnemonic is used to specify a single byte of actual data. The Define Address mnemonic is used to specify two bytes of actual data. Here is an example of how these two mnemonics would be used. The instruction sequence:

ADDRESS

ADDR1 VALUE
would cause the Assembler

ORG DC DA DC

H'0700' H'3A'

K27AC
H'OF'

to directly create the following

memory map:

0700
0701

3A
27

0702

AC
OF

0703 0704 0705 0706

MEMORY ADDRESSING
addressing has already been introduced in Chapter 4, where some discussion of the subject was needed in order to define the registers which a CPU will require. We are now going to cover the subject of memory addressing thoroughly as a precursor to defining a microcomputer's instruction set.

Memory

MICROCOMPUTER MEMORY ADDRESSING WHERE IT BEGAN

We will
subject

begin our discussion of microcomputer addressing modes by looking at the

in overall

perspective.

6-12

The forerunner of all microcomputer instruction sets is the instruction set of the 8008 microcomputer and the Datapoint 2200 minicomputer. These two devices
the

Intel

have

same

instruction set. but the Datapoint

2200 executes

instructions approximately ten times as

Mr. Vic Poor (and associates) at Datapoint developed this instruction set for the limited data processing environment of "intelligent terminals." Discrete logic replacement was not what they had in mind. Vic Poor's instruction set was deliberately limited, to accommodate the confines of
fast.

large scale integration (LSI) technology as it stood in 1969-1970. The instruction set's ory addressing capabilities were primitive out of necessity, not desire.
Intel,

mem-

who

initially

market

for the

product

developed the 8008 microcomputer at Datapoint's reguest. found a significant in discrete logic replacement a market for which the instruction set was

never intended.

Subsequent microcomputer instruction sets have evolved as a

ing influences:
a)

result of

two competin

Microcomputer designers incorporated minicomputer features as fast as advances technology would allow while there was no definable microcomputer user base.

LSI

b)

Now that a definable microcomputer user base designers are responding directly to users' needs.

is

beginning to emerge, microcomputer

Influences (a) and (b). above, do indeed differ. Microcomputer users' needs are not always well suited by minicomputer instruction sets, a fact to which we will continuously return in this chapter.

IMPLIED
An

MEMORY ADDRESSING
in detail in

instruction that uses implied memory addressing specifies the contents of a Data Counter as the memory address.

Implied

memory
this

addressing has been described

Chapter

4; therefore,

we

will

simplyx

summarize

addressing mode.

Using the Data Counter to address

memory

is

a two-step process:

First,

the required

memory

address must be loaded into the Data Counter.

the Data Counter con-

Next, a single-byte
tains the

address
first

memory reference instruction is executed, where of the memory location to be referenced.

instructions of the

Consider the

two

programming example we have been using

in

this

chapter. Execution of the

two

instructions

may be

illustrated

as follows:

Program

Memory

6-13

Object code for the

Byte
tion

first

instruction (LIM

DC0.ADDR1) occupies

three program

memory

bytes,

with addresses 067A, 067B, and 067C. These

memory

addresses have been

arbitrarily selected.

067A

contains an 8-bit object program code which represents the LIM

instruction specifies that the contents of the next

DC0.ADDR1

instruc-

mnemonic. This
in

two program memory

bytes are to be loaded, as a 16-bit value, into Data Counter DCO. Recall that the actual binary

code appearing

memory word 067A

will

vary from microcomputer to microcomputer.

The second

memory

instruction, with mnemonic LMA, specifies that the contents of the location which is addressed by Data Counter DCO is to be loaded into the

Accumulator. We call this IMPLIED memory addressing, because the memory reference instruction, in this case LMA, does not specify a memory address; rather, it stipulates that the memory location whose address is implied by Data Counter DCO is the memory location to be referenced.

DIRECT
Simple direct
addressing.
In

MEMORY ADDRESSING
directly specifies the address of the
in

An instruction with direct memory addressing memory location to be referenced.

memory
addressing has been described

Chapter 4 along with implied

in this

memory

terms of the instruction sequence

we

are using

chapter, the

LIM and

LMA

instructions could

be combined

into

one

direct

memory

reference instruction as follows:

Program

Memory
Address Register

067A
067B

43
2F

Accumulator

067C

3C

067D
067E
067F

2F3A
2F3B

2F3C

4A

2F3D

An Address

Register performs the

same

function as a Data Counter, but

it

does so

transiently.

direct

memory

reference instruction always starts with a

register.

memory

address being computed and

loaded into the Address

reference.
Direct addressing
is

This

becomes

the address of the

memory

location to be

the simplest addressing

mode used

by minicomputers. Implied

memory

ad-

dressing

is

a microcomputer

phenomenon.

DIRECT VERSUS IMPLIED ADDRESSING

By way of direct comparison, a minicomputer Address nonprogrammable register. This means that a minicomputer
load data into the

register

is

referred to as a

has no instructions that merely

Address

register or

modify the Address

is

register's contents.
in

The process

of

changing the contents of the Address register

ecuting a

always one transient step

the course of ex-

memory

reference instruction.

6-14

The Data Counter

in a

microcomputer

is

programmable.
into the

In fact,

every microcomputer

will

have a number of instructions that simply load data Counter contents, but do nothing else.

Data Counter, or modify the Data

Some microcomputers provide both implied and direct memory addressing. These microcomputers have one or more Data Counters for implied memory addressing, plus an additional Address register for direct memory addressing.
The
first

into the

CPU

microcomputers used implied memory addressing only, because it was simple to design Control Unit; there was no other reason. The penalty incurred by the use of implied
addressing
is

do what one direct memory addressing inwhere microcomputer designers could do away with implied memory addressing, but they have not done so. Today most microcomputers include a limited number of instructions with direct memory addressing, but implied memory addressing remains the standard; why? Because some necessary variations of direct
that
it

memory

takes

two

instructions to

struction could do. LSI technology has

advanced

to the point

memory ROM.

addressing generate features that are very undesirable

when programs

are stored

in

VARIATIONS OF DIRECT

MEMORY ADDRESSING
We
A
will first consider variations of direct memory addressing as they apply to minicomputers with 12-bit and 16-bit words. This is a good beginning, since direct memory addressing variations evolved as minicomputer memory addressing features.
16-bit

word allows a minicomputer to have 65,536 different instructions in its instruction set. A word allows a minicomputer to have 4096 different instructions in its instruction set. These are ridiculously high numbers. Minicomputers therefore separate instruction words into instruction code bits and address bits.
12-bit

Consider first a minicomputer with a 12-bit word. Digital Equipment Corporation's PDP-8, the world's first popular minicomputer, uses a 12-bit word. The PDP-8 CPU is now manufactured by Intersil on a single chip, called the IM6100. The 12-bit word may be used as follows:
o o o o x x|x x|x x x|x|
i

12-BIT

WORD

DIRECT

ADDRESSING
PDP-8
INTERSIL

r-

*
Address
bits (2
8

256 10

IM6100

Instruction

code

bits

Eight address bits allow this instruction to directly address up to 256 memory words; 256 words constitutes a very small memory, so we will have to seek ways of expanding our memory addressing range, without using more addressing bits.
Will four instruction
tion of

code
is

twelve

bits into four instruction

reference instructions. This

tions:

the above separacode bits and eight address bits only applies to memory how the PDP-8 and IM6100 interpret memory reference instruc-

bits

be enough? Yes indeed. Remember,

III
J

'

^-1

Ixlxlxlxlxlxlxlxl

Address
Indirect

bits,

if

memory

reference instruction

address option (which

we

will
if

describe

later)

Only a

memory

reference instruction

these three
(for

bits

hold 000, 001, 010, 011, 100 or 101

memory
non-

reference

instructions);

110 and

111

specify

memory

reference instructions

6-15

These 9

bits

allow 5 1 2 non-

memory

reference

instructions, for

instruction

a total of

each of two code options; thus 1024 non-memory

reference instructions allowed.

These 3
specify a

instruction

code
if

bits

non-memory
they
10 or
1 1

reference instruction,
contain
1

1.

16-bit

computer could address 4096 10 memory words with 12

bits of

an instruc-

tion word:

m. Q|o|x|x|x|x|x|x|x|x|x|x|xTx]

T
The

Address

bits (2

12

= 4096 10
bits

>

Instruction

code

16-bit computer could offer more instruction code options, and a smaller addressing range, as follows:

loioiolololololo X|X|X|X|X|X|X|X|
i

8 address

bits (2

256)

8 instruction code

bits

Most minicomputers divide their single word instructions into eight address bits and eight instruction code bits, as illustrated above. An 8-bit microcomputer can easily
achieve the

same

result,

using

two

8-bit words, as follows:

bits

8 instruction code

X X X X X X X X
8 address bits
(2
8

256)
instruction:

2-bit

computer could address 4096 10 words by providing two words per

12 instruction code bits

X X X X X X X X X X X X
>

.~>

12 address bits"
(2
12

= 4096 10

6-16

Although two

12-bit

words per

instruction

is

very feasible,

all

PDP-8

instructions are, in fact, one-

word
If

instructions.

a 16-bit of

words

computer uses two words per memory:

16
i

instruction,

it

can directly address 65 536 10

nstruction

code

bits

X X X X X X X X X X X X X X X X
16 address bits
(2' 6

65.536,

The microcomputer programming examples we have used earlier 16-bit memory addresses via three 8-hit wnrH f n ii<-.,o-

in this

book specify

Word Word Word

It is

8 instruction code

bits

2 3

X X X X X X X X X X X X X X X X

16 address

bits

clear that

where from 8 to 16 address

In

one way or another, instructions can have anybits. What is the optimum number?

ADDRESS
BITS

minicomputer applications, statistically we find the 80% to 90% of Branch instructions only need an addressing range 128 words (addressable with eight address bits):

THE

Jump and

OPTIMUM NUMBER

XXXX -

128

Instruction
here, at

Most frequently
y addressed

Address

XXXX
127

Memory Words

XXXX +

Most minicomputers provide more than one

or
all

instruction

word format,

including

three of the following:

two

Format
(limited

|o|o|oio|o|ofo|ojx|x|x|x|x|x[xTx|
.

addressing
range)

8 Address

bits

8 Instruction code

bits

Format 2
(limited

|o|Q|o|o[x|xlxixix|x|x|xlxix]x|x]

addressing
range)

2 Address bits

4 Instruction code

bits

Format 3
(extended
addressing
range)

16 Instruction code

bits

x X X X X X X X X X X X X X X X

16 Address

bits

6-17

'

Instructions with a restricted addressing range are referred to as

SHORT FORM
any word

instruction.

LONG

FORM

instructions have sufficient address bits to directly address

in

memory.

PAGED DIRECT ADDRESSING

computers provide some instructions with a limited addressing range. If all of a computer's instructions are subject to a limited addressing range, the computer is said to be PAGED.
All

To

illustrate
is

paging, consider a

12-bit
into

Memory

effectively

segmented

minicomputer with eight address 256 10 (100 16 word pages as follows:

)

bits
'

per instruction.

Hex

Memory
Address

Page Count

_0000 _0100 16

0300

_0200, 6
1R

Page Page 2 Page 3

1

.0900, 6

Page 10

.OAOOir
Etc.

The eight address

four digit

bits of

an instruction word provide the two low order hexadecimal

digits of a

memory

address; the

two high order

digits are

taken from the Program Counter. Thus

the instruction:

would be coded

|1|0
i

f
in

JMP

H'3C

one

12-bit word, as follows:

loiololi lilili lolol

Address
bits are

3C 16

(H'

'(specifies a

hexadecimal value

between quotes.
Jump,
direct instruction.
in

Next instruction to be executed has

location

object code stored

memory

computed using

address

bits of this instruction

word.

6-18

Suppose the jump instruction is stored in a memory word with the ad0709 ie After the jump instruction has been fetched from memory, the Program Counter will contain the value 070A The effective
dress
.

EFFECTIVE

MEMORY
ADDRESS

16

is given by the two high order digits of the Program Counter, plus the two low order digits from the instruction, as follows:

memory

address, therefore,

2-Bit

Program Counter
1

2 Bit Instruction Register

|o|i|iniololo|oli|o|o|i|

|o|

lololol

ilol oi

Effective Address:

073C

digits, taken from the Program Counter, are PAGE page number. The low order digits, supplied by the inNUMBER struction code, are the address within the page. Combining the two portions of the address yields the effective memory address. The term "effective memory address" applies to any memory address that must be computed in some way using information provided by the instruction.

The high order

called the

As

illustrated

below, the instruction:

JMP
will

H'3C
Program Counter, so the next
instruction will

cause the value 073C 16 to be loaded

into the

fetched from

memory

be

location

073C 16

Memory
(12
bit

Memory
Address

words)

Instruction Register

Program Counter

e specified by
gits of

two

high order

Program Counter
as follows:

This illustration

is

described, with reference to the

keysQ, and,

6-19

(T)

The Program Counter addresses memory word 0709 16 The contents of this memory word, A3C 16 is fetched and stored in the Instruction register. The Program Counter is incremented
.

to

070A 16

thus,

it

addresses the next sequential program

in

memory word.

(2)

The

instruction

code

the Instruction register

is

an unconditional jump. The two low order

to the

digits of the Instruction register

(3C 16 are
)
.

moved

two low order

digits of the

Program

Counter, which

now

contains 073C, 6

The next

instruction will

be fetched from memory location 073C 16

Consider another example. The instruction:

LMA

H'6C

located on Page 2F 16 would cause the contents of memory location 2F6C 16 to be loaded into the Accumulator. The same instruction on Page 1C 16 would cause the contents of memory location

1C6C 16

to

be loaded

into the

Accumulator.

With many paged computers a devious error occurs at the page boundaries. Recall that the Program Counter is incremented
an instruction has been fetched. Therefore the page number is acquired from the high order digits of the Program Counter, AFTER the
after

PAGE

BOUNDARY
ERROR

Program Counter has been incremented. Suppose the

instruction:

LMA

H'6C
this instruction

were located at a memory word with address 2FFF 16 After Program Counter will contain 3000, 6 Now the contents 306C 16 would be loaded into the Accumulator, instead 2F6C, 6
. . .

has been fetched, the

with address
with address

of the

of the

memory word memory word

that an
is

The most severe

reference any

restriction

imposed by fixed pages

on which the

is

instruction

cannot

memory word

outside the page

instruction

located: to read data, to

write data or to execute a

program branch or jump. Therefore, programs cannot reside across

page boundary:

Page 06
noperable

memory
a

program module or subroutine in Paged Computer

location for a

Page 07

<

Page 08

Paging is wasteful of computer memory, because it requires programs to access data on, or via addresses stored on the program's page. Thus numbers used com monly by programs on many different pages must be stored repeatedly on each page, or else we must add some new flexibility to paged addressing.
all

6-20

Also,

when
fills

exactly

writing program modules and subroutines, is difficult to contrive that every module one page. As a result, a small portion of memory at the end of each page is wasted,
it

since it is too small to accommodate even the smallest subroutine. Thus a programmer must frequently waste a lot of time juggling the sizes and memory locations of his program modules and subroutines.

Consider, for example, a program with the following modules:

Program

Size (words)

MAIN
SUB1 SUB2

88 16
22 16 78 ;6
52 16

SUB3 SUB4 SUB5 SUB6

38 16
50, 6

66 16
as follows:

We

can

map

the program into

memory

Program

Memory
0300,6 0388, 6 0400,6 0452,6
-

Location
0387,6 03FF, 6 0451,6 0489,6 04FF, 6 0565, 6 0585,6

MAIN
SUB2 SUB3 SUB4 SUB5 SUB6 SUB1
But beware of an error
tions, say).
will

0490 !6
0500,6 0566,6

in subroutine SUB3 that requires you to increase its size (by two instrucSubroutines SUB3. SUB4. and SUB5 no longer fit on one page, and correcting SUB3

require

remapping the whole program

of eliminating
is

in

memory.

One method
This
is

some

of the restrictions

imposed by

paged addressing
option, the

BASE PAGE

to provide the computer with a base page.

what the PDP-8 does, so let us look at this specific case. In order to give itself one more PDP-8 uses just seven of the eight address bits to compute addresses within a pagein other words, the PDP-8 page is not 256 words long, is 128 words long. However, the eighth bit allows you to address either the current page, that is, the page on which the instruction is located, or you can address the base page, that is. one of the first 128 words of
it

memory

This

is

illustrated

as follows:

12 -Bit Program Counter

12 -Bit Instruction Register

|p|p|p|p|p|p|p|p|p|p|p|p|

|o|o|o|o|d1x|x|x|x|x|x|x|

Effective

address,

memory D =
1

Effective

memory

address,

D =

|010|0|0|Q|X|X|X|X|X|X|X|

6-2

In

the

above

illustration,

symbols are used as follows:

represents individual binary digits with the Program Counter.

represents the instruction code
bits of

the Instruction register.

represents individual address

is
If

bits of

the instruction word.

computed by this bit is 0. then the effective memory address is the page select bit. in the five moving the X bits into the low order bits of an Address register and inserting 0's to 127 from order bits of the Address register; in other words, memory locations high may be addressed. This is referred to as the base page of memory. the D bit is 1. then
If

high order bits of the the five high order bits of the Address register are taken from the five which the instrucProgram Counter; only memory locations within the 128 word page in
tion resides

may be

referenced.

A more flexible
ing,
in

an instruction repreadded to the Program sent a signed binary displacement, which must be

which

it

is

variation of paging is assumed that the address

PROGRAM RELATIVE
bits of

pag-

PROGRAM
RELATIVE

PAGING

Counter contents.

program

relative

page may be

illustrated

as fellows:

Instruction

Range
-

of

Memory

Address B

Directly

Addressable

Range
Directly

of

Memory

Instruction

by Instruction B

Addressable

-Address

by Instruction A.

in a forward Program relative addressing allows an instruction to address memory each direction of half a (positive) or backward (negative) direction with a range in

page. Consider again an

8-bit address, this time in a 16-bit

word:

8 Address
,

bits
bits

8 Instruction code
is

Assume that the high order address bit is a sign bit; 24AE 16 and .the eight address bits contain 7A 16 then
. .

if

the instruction
the effective
1

memory word memory address is given by:

located at

0010010010101 10 1010 0000000001 0010010100101000

1
1

24AE _ 7A
2528
bits

Sign

bit is

propagated through high order eight

6-22

This example of forward

tions as follows:

memory

addressing

may be

illustrated

using assembly language instruc-

Memory
Address

Object

Code

Source Program Instruction

24AD

BC7A

JMP

HERE

2528
In

HERE

LMA

THERE

the above
is

illustration,

BC represents the JMP

so
it

instruction code. (The

is left

LMA

instruction's object

code
dress

irrelevant to the discussion at hand,

bits of

the

JMP

instruction

The Assembler will compute the adby subtracting the value in the Program Counter, after the JMP
out.)

instruction has

been loaded, from the value associated with the

Label

label

HERE:

HERE

is

equivalent to

2528

PC

contents after instruction load

Difference

= 24AE = 007A
instruction
is illegal,

If

the Assembler
will

computes

a value greater than 7F 16 the

.

JMP

and an

error

message

be transmitted

to the errant

programmer by the assembler.

Suppose the two

instructions

were

reversed;

we would now

have:

Memory
Address

Object

Code

Source Program Instruction

24AD

HERE

LMA

THERE

2528

BC84
bits of the

JMP

HERE
in

The Assembler
the value
in

will

compute address

JMP

instruction

the

same way, by

subtracting

the Program Counter, after the

JMP

instruction has

been loaded, from the value asso-

ciated with label

HERE:
Label

HERE

is

equivalent to

24AD

PC contents

after instruction load

Difference

= 2529 = 7C

-7C

is

stored

in its

twos complement form:

7C
ones complement

= 111110 = 10
1

twos complement

10000100=
JMP
instruction
is

84
follows:

The

effective

memory

address provided by the

computed as
2529 FF84

0010010100101001 1111111110000100 0010010010101 101

(. Sign
bit is

24AD
bits.

propagated through high order eight

DIRECT
IN

MEMORY ADDRESSING

MICROCOMPUTERS

Variations of direct addressing which are useful in minicomputer applications are not useful, and are frequently not even viable, in microcomputer applications. Let us carefully examine why this is the case.

Consider

first

a three-byte, direct

memory reference

instruction,

EXTENDED
DIRECT

which

we

have represented as follows:

code

ADDRESSING
Instruction

Two

address bytes generated

16-bit address

This instruction format

will certainly

work. The two address bytes allow any

memory

location to

otherwise manipulate data, or to change program execution sequence by executing a jump or branch instruction. There are, however, two
tions: first, the

be addressed

directly either to store, read or

problems associated with the use of three-byte, direct memory reference instructwo address bytes cannot be changed; second, three-byte instruc-

tions are very wasteful of

memory.

Here

is

an example of an instruction sequence that moves data from one buffer to

Load
first

another buffer:

buffer

starting address

Load second buffer

starting address

Load

buffer length

Load byte from

buffer into

first

Accumulator

Store Accumulator contents into second

buffer, next byte

Increment first buffer address

Increment second buffer address

YES

the above program logic sequence would be executed by a microcomputer that has two Data Counters (DCO and DC1) and two Accumulators, (AO and A1). Assume that Buffer 1 begins at memory location 0470 , Buffer 16 2 begins at memory location 08C0 16 , and each buffer is eight bytes long. Illustrating CPU Data register contents, this is what happens:

Consider

how

6-24

< <

000Q00
O O
*3"

oooooooo
^T

OOOOOOOO oooooooo

cocococococococo

O O u

CO

K s

c_>

< o o -

^
I

o ^ O

u o

o r

u u o - _ ~ U U Q Q u u <
-

^
CO

^ S S Q

CD

00000

oooooooo

OOOOOOOO oooooooo

r- 5 o
o o o

o o & o

6-25

0000
o o

oooooooo
T s u < o o -

UUUUUCJUU

oooooooo

cocococococoooco

o o u

00000
O 8 o u o

oooooooo
s 3
C_>

UOCJCJOOUU

oooooooo

< 3 o '

(_)

a.

o -- o < < u u

6-26

q q y o <

TD

"D

00000

oooooooo
J
H^
o

UUOUUUUCJ oooooooo
COCOCOCOOOCOCOCO

e
1

o o o ^r co o o
r-~

^r CM

oo

^ T3
o

c ;

Q po
GJ

0000

oooooooo

oooooooo

CJ

o o

s o
<->

o - o < < U
<-J

6-27

y 8 u < a a u
E E
CO

W i Q

0000
o o
o o U
Is
1

oooooooo
^ K s u < o o
-t
^r

u o o
^r

o
-

u o

q y y <
E

<<??E
o
CO
.

^ D

CO
<3-

e 00000
o o o o
o

O o o o o o o o
*3"

u u u o u CO o o o o o o o

s u < o o -

o o
^r

o U

CL

< <

(J

6-28

0000

UUUCJUUUO oooooooo

D-

< < U U

Q Q u u <

003

OOOOOOOO
111
I
I
I

C_l

o o o
-

6-29

Observe that the program, as illustrated, fits into 15 program memory bytes. Instructions 4 through 9 are re-executed eight times. This is possible, since with each re-execution, the part that changes, data memory addresses, changes in the Data Counters. This is the virtue of implied memory addressing.

How would

the

same program

direct addressing, but no implied addressing?

consist of a pair

be implemented by a minicomputer that has If the program is in ROM, it will have to of three-byte instructions repeated eight times:
logic

o <
CD

<
(J

o <
o o
CD

o
CO T3

CO ~o

Total program length will be 48 bytes. Implied memory addressing has saved memory by allowing a set of instructions to be re-executed, and by allowing memory reference instructions
to

occupy
Implied

a single byte:

Memory

Direct

Memory

Reference Instruction

Reference Instruction

Load

into

accumulator

data addressed by

DC

^ Load into Accumulator

/data addressed by
'

these two bytes

Addressing problems associated with microcomputers become more severe if you try to use any type of paged direct addressing. Minicomputer designers use

PAGED
DIRECT

paged

direct addressing

in

order to

ADDRESSING

reduce the number of address

instruction.

bits that are part of

Pages may be absolute or program

relative,

each memory reference as we havg just described.

The problem with any form

Jump and Branch memory reference

(or larger)

is that it can only be used for form of addressing simply cannot be used for instructions that write into memory. ROM usually comes in 1024-byte

of paged, direct addressing

instructions. This

be

ROM

or

modules. Pages are either 128 or 256 bytes long. Therefore, an entire page will either RAM. It is not possible to have the program area of a page in ROM and the data area
in

of the

same page

RAM:

6-30

One 1024

byte

ROM

Module

PageO

Page

No
can

Write instructions, using any kind of paged addressing.

exist here.

Page 2

Page 3
high order
half of
\

page

" can

Write Wn instructions with program

exist here, but only
if

relative,
is

paged addressing

next page

RAM

It

would

certainly

be possible to have
th S
'

memory
d
'

dir^^f

aata areas, as follows:

WOU d
'

reference instructions that read data out of proint0 a

reqU

'

re

Vld

'

ng UP mem0rV

checkerboard of program and

One 1024

byte

ROM
/

Module
data

PageO

program

data

Page

program
data
data

Page 2
program

Page 3

program

data

memory mapping greatly increases the cost of creating microcomputer oro grams, plus the potential for introducing programming errors. As a result microcoZte grams are almost always written with separate program and data areas of

This type of complex

n^ me^TlSlo^"

6-31

Memory

Program Area *

Data Area

So

universal

specify separate

dresses a dresses a

memory into program and data areas that some microcomputers admemories for programs and for data. This means that the Program Counter Counter adwhich the Data Counter cannot address; and conversely, the Data memory memory which the Program Counter cannot address.
is

this division of

AUTO INCREMENT AND AUTO DECREMENT

that the two addresses, the data movement example we just described, observe reference. Data Counters, must be incremented after each memory stored in the two
In

adstarts at the other end of a data buffer, so the memory is easy to imagine program logic that can create a In either case, dress must be decremented after every memory access.
It

we

single one-byte instruction that specifies a memory address increment or decrement:

memory

reference operation, plus a

d
re

AO AO

via vih

DCo\ DC1 \

nl

DCO
DC1

IS
THE STACK

nt

.tncril

DC1

which has existed in many There is a variation of implied memory addressing another in almost every minicomputers and is implemented in one form or of a stack was introduced microcomputer; it is known as Stack addressing. The concept
at the

end

of

Chapter

4,

in

connection with Chip Slice Control Unit addressing

logic.

MEMORY STACKS
The more common Stack
architecture sets aside some area of addresses. The data memory for transient storage of data and register, called the Stack is addressed by a Data Counter type of

STACK
POINTER

Stack Pointer.
writing to the top of the Stack Only two Stack operations are usually allowed: top of the Stack (referred to as a Pop, (referred to as a Push), and reading from the
or a Pull).
stack of data words, where the fact that it may be visualized as a data word at the top of the stack. entered into the stack, or the first empty only the last data word Pointer. via an address stored ,n the Stack may be accessed. In either case the Stack is accessed
its

The Stack gets

name from

6-32

A Push
word

operation,
(or

which writes
other

into the Stack, will

register) to

Accumulator

some

CPU

cause data from the be written into the memory

PUSH

I
'

currently addressed by the Stack Pointer (SP); the Stack Pointer contents is then automatically incremented to address the next free word, at the new top of the Stack, as follows-

Before Push Stack

21

After Push

Stack
0C40
0C41

4A
62
7 7 ?
->

0C42

0C43
0C44 0C45
0C46

0C47

Pull or

Pop operation
is

is

the exact reverse of a Push; the Stack register

contents

POP

decremented

to address the last

the Stack, then the contents of the

word written into the top of memory word addressed by the Stack

is

cumulator or

some

moved

other

CPU

to the

Ac

register. This

may be

illustrated

as follows-

Before Pop
Stack

After

Pop
Stack

Observe that
data

at the

end

of a

Pop

memory word
word
is

operation, the Stack Pointer

is

again addressing the

first

at the top of the Stack;

unused
he

once data has been read out

assumed

of the top of the Stack

to

be empty.

between implied memory addressing, using a Data Counter, and Stack memory adS n9 3 " 9 the only difference between the two is inter is self ev dent ln fa that ^p the Stock Pointer contents MUST be incremented after a write,
parallel
'

The

fhfr
h ere
tlo n

'

'

and

MUST

be decremented

after

C UrS
th

that^

h u

bove

mow

the%"

nmhing ch"

m T" VT
thln
r

th

be nQ lm P lemented in mory - the opposite direcaCC8SSed r8ther than the t0p In the se e '"^trated f deCr6mented after a Wnte and ^remented after a read. Otherwise
*
'

StaCk

^
"

'

6-33

THE CASCADE STACK

There
is

an alternative Stack architecture that

is

less frequently seen. This

(it is

P^ SH

architecture provides a limited

in

number
is

of registers

commonly 8
it

or 16)

the CPU.

When

a byte of data

pushed onto the Stack

cascades

down

as follows:

Before Push

After Push

Stack

When

a byte of data

is

pulled or

popped from the top

of the Stack, data

POP

cascades up as follows:

Before Pop

After

Pop

Stack

Stack

CA

Pointer, since at This Stack architecture requires no Stack read out of the top of the Stack.

all

times data

is

being written

into, or

HOW A STACK
The Stack
is

IS

USED
it

Consider the

users; a great convenience to minicomputer necessity in microcomputer applications. are use of subroutines. Most programs, whether they

is

an absolute

SUBROUTINES
program

consist of a number of written for a minicomputer or a microcomputer, which is recorded once, somewhere in frequently used instruction sequences, each of routine is then accessed as a subroutine.

memory. The

An

application

may

require arithmetic to

four conbe performed on 32-bit numbers, occupying

tiguous bytes as follows:

Byte 3 Byte 2 Byte
1

Byte

single, 32-bit

number

6-34

The most

efficient

way

of handling this type of arithmetic

is

to write four separate

programs to

perform 32-bit addition, subtraction, multiplication, and

perform addition (for example), you will subroutine. A call may be illustrated as follows:

Now every time you want to use an instruction which CALLS the
division.

SUBROUTINE CALL
Program Memory Used by Main Program

Program

Memory used

by 32-bit binary
addition subroutine

represents the instruction execution sequence

Suppose you did not use subroutines; the instruction sequence needed to perform 32-bit, binary would have to be repeated every time program logic specified 32-bit, binary addition. The program would now appear as follows:
addition

Program Memory Used By Main Program

Program Memory Used By

32-Bit, Binary Addition

Most programs, whether they are written for minicomputers or microcomputers, eventually become nothing more than a large network of calls to subroutines. Providing the importance of subroutines in all microcomputer programs is accepted at face value, you need not understand any more about subroutines at this point. However, let us consider what happens when a subroutine is called, and how program logic handles a return from a subroutine.

The PDP-8 minicomputer, and a number of other old minicomputers use the first memory word of a subroutine as the location where the return address is to be stored. For example, suppose our 32-bit, binary addition subroutine instructions occupy memory locations

4C2 16 through 4E0 16 The PDP-8, being

.
,

a 12-bit minicomputer, stores only 12-bit adIf

Memory word 4C2 16 is the first word of the subroutine, and must be left empty. subroutine is called from memory location 72A 16 the following sequence of events occur:
dresses.

the

6-35

The current contents

The address
of the

of the

Program Counter are stored

is

in

memory

location

4C2 16-

2)
3)

first

subroutine instruction, 403^,

loaded into the Program Counter.

Program execution proceeds

at the instruction stored in

memory

location

4C3 16

This

may be

illustrated

as follows:

Before Call

After Cal

Subroutine
?

Subroutine
04C2 04C3 04C4 04C5 04C6
04C7
72C

04C2 04C3 04C4 04C5 04C6

04C7

Cc Ming Progra

m
0728 0729

Ccailing

Program
0728

72C

PC

4C3

PC

0729

CALL
4C2

072A
072B

CALL
4C2

072A
072B 072C

072C

072D
072E 072F

072D
072E

072F

0730

The

last instruction executed within the subroutine must be a return instruction. This instruction moves the address (72C 16
)

SUBROUTINE RETURN

in the first word of the subroutine (at 04C2, 6 back into the Program Counter, thus causing program execution to continue at the instruction following the

stored

subroutine

call.

cannot work in a microcomputer apthe subroutine is going to be stored in read-only memory; this being the case, the return address cannot be stored in the first word of the subroutine. Microcomputers store subroutine return addresses in the Stack. The 32-bit binary addition subroutine call would be executed as follows:
This

scheme

for calling subroutines obviously

plication, since

6-36

Before Call

After Call

Subroutine

Subroutine
04C2 04C3 04C4 04C5 04C6 04C7
04C2

H
04C3
04C4

04C5
04C6
04C7
1 1

i i

1 1

ailing Progre

m
0728
0729

c ailing Program
0728

0729

CALL
04

072A
072B PC SP
04C2

CALL
04

072A
072B

C2

072C

0C45

C2

072C

072D
072E 072F

072D
072E
072F

Stack

Stack
I 1

1
1

21

0C40
0C41

21

OC40
0C41

4A
62
? ? ?

4A

0C42

0C43
0C44

^^ Top

62

of stack

~^

0C42

07

0C43 0C44 0C45

2D

0C45

In

the above

illustration,

note that 8-bit

bits long,

two memory words

memory words are assumed. Since addresses are are required to store each address.

all

16-

In order to return from a subroutine, it is only necessary to pop the top two bytes of the Stack into the Program Counter. Execution will then proceed with the instruction following the call to the subroutine.

NESTED SUBROUTINES

AND USE OF THE STACK

A
nested subroutine
is

subroutine.
There

defined as a subroutine which has been called by another

is nothing at all unusual about one subroutine calling another. In subroutines are frequently nested to a level of five or more. There are even certain mathematical routines in which the most efficient way to write the program is for the subroutine to call itself.

fact,

RECURSIVE SUBROUTINES
call itself is re-

ferred to as a recursive subroutine.

subroutine that can

So

long as the Stack

in

nested

StacT
Were
this
illustrations.

is being used to preserve return addresses, subroutines can be any way. or can call themselves; and providing the return path follows the eXaCt V the C rreCt retUm address wi always oe at the cu "*nt
' '

"

top of the

book a programmer's guide, we would now prove the above statement with extensive However, in order to understand microcomputer concepts and microcomputer programming, you can take at face value the fact that the Stack will
insure that the return path
is

the

6-37

yourShould you still be curious, you can prove this or exact inverse of the subroutine call path. Arbitrarily selec located in various areas of memory. self by defining a number of subroutines a piece of other subroutines exist. Draw a Stack on locations within subroutines where calls to return, pop the return adperform a push of the return address. For each

paper and

for

in exactly that you come out of nested subroutines dress ,nto the Program Counter. You will find however complex the subroutine call sequences may the same sequence as you entered them,

each

call

be.

INDIRECT ADDRESSING
An INDIRECT ADDRESS
specifies a

memory word which

is

assumed

to

INDIRECT

hold the required direct address.

ADDRESS

Memory

Jump

indirect object

code

Address

XXYY

provided by

Jump

instruction

The

first

of these

two memory

bytes has address XXYY, and the two bytes contain AABB.

This

memory byte has the memory address AABB. and the addressed memory
location.

is

AABB

address For indirect addressing, the effective

is

given by the equation:

INDIRECT

EA = [XXYY]
where:

ADDRESS COMPUTATION

EA
[

signifies the

stands for Effective Address contents of the

memory word whose

address

is

enclosed by the

brackets.

A PAGED COMPUTER'S
INDIRECT ADDRESSING
since it is the only an absolute necessity on a paged computer, own page. location outside an instruct.on s way a program can access a memory instruction: on a paged computer, the direct address Thus,
Indirect addressing
is

LMA

XXYY

6-38

must,

if

XXYY

is

beyond the

instruction's page,

be replaced by the

indirect

address instruction:

LMA

"HERE

HERE
In

DA
HERE

XXYY
provides the address of the indirect address

the

LMA

(Load Accumulator) instruction,

memory word, and "*"

specifies indirect addressing.

Memory

location

HERE

contains'an address

XXYY which becomes

the effective

memory

address.

With an absolute, paged microcomputer, an instruction with indirect addressing will only occupy two bytes. The effective memory address is now computed as follows:
Memory
Any
indirect instruction's

Memory

address of instruction

object code

code bytes

Address within page provided by instruction

The

first

two

bytes,

on the

same

page, holding the

required

memory addresses

AABB

which can memory, has the memory address AABB, and is the addressed memory
This
byte,

memory

be anywhere

in

location.

6-39

The PDP-8, being a

direct addressing:

12-bit minicomputer, uses the following variation of paged, in-

Memory
These three
identify the
instructor!
bits

These seven

bits

provide an

12-bit

address within the page.

memory
address of instruction, a
are binary digits.

Each n represents a binary

and b

digit.

aaa aabbbbbbb

An

indirect addressing

instruction

These two
both be
indirect
1

bits

must

to specify

address on

current page.

12-bit

aaaaannnnnnn

memory
address of word, on same
stored, a
digits.

page where indirect address and n are binary

is

This 12-bit

word has the

hexadecimal address PQR.

This
is

the indirectly

addressed

memory word.

The PDP-8, and any other paged computer that has

a base

INDIRECT VIA

page, will use a large part of the base page to store addresses; these addresses will be referenced indirectly. For ex
ample, suppose

BASE PAGE

aaaaabbbbbbb is in the above illustration the object code at memory location HUOnnnnnnn. instead of being 1111 Innnnnnn. Now the address stored in memory location OOOOOnnnnnnn would be chosen, not the address stored in memory location aaaaannnnnnn.

6-40

Another variation of indirect addressing sets aside certain memory locations as auto increment or auto decrement locations. For example, the PDP-8 minicomputer sets aside memory locations 008 16 through 00F 16 on the base page, as auto increment locations. If an address is stored in any auto increment location, then the address will be incremented whenever it is referenced indirectly.
,

INDIRECT AUTO

INCREMENT

AND DECREMENT

With reference

to the

most

recent, illustration,

if

then after the indirect addressing instruction had executed, memory location 008 would contain" 16 PUH+ i; on the next execution of the indirect addressing instruction. PQR + 1 would be the effective memory address, not PQR.
)

aaaaannnnnnn were 000000001000

(i

008

An

auto decrementing

indirect

address would have generated

PQR-1

s^reTln the base page are to change. stored in

**'* ***

rather than

PQR + 1.
if

S'

be ,m P |emented

read-write

memory

addresses

PROGRAM RELATIVE, INDIRECT ADDRESSING

Ute tha U S Pr 9ram relative direct addre "ing ! w! f.tZ indirect addressing. This is what H relative, happens
'

can also have program

Memory

Memory

address of

Any

instruction

code

indirect instruction's

bytes.

.PPQQ

object code

PPQQ +

YY

Displacement address provided by instruction

These two bytes contain the required memory

address.

-(PPQQ + D+YY
(PPQQ+1 )+YY +
1

AA

AABB

which can memory, has the address AABB, and is the

byte,

This

memory

be anywhere

in

addressed

memory

location.

6-41

INDIRECT ADDRESSING
In

MINICOMPUTERS VERSUS MICROCOMPUTERS

the world of minicomputers, even if the minicomputer's direct addressing is not paged, indirect addressing is a great convenience since it allows one Load or Store instruction to access a number of different memory locations, depending on the current contents of the indirect memory address word. Consider the following example:

Memory
Indirect addressing instruction

object code

XX YY

Address

XXYY

provided by

indirect instruction

These two memory bytes contain

the effective address.

XXYY yyyY +

AABB

These are the memory bytes may be addressed.

that

TPQQ

RRSS

Why

would you want to change the

indirect address

AABB

to

PPQQ

or

RRSS?

Many minicomputers are time-shared. This means that a single minicomputer may be executing many programs, attending to each one for a few milliseconds before going on to the next. Each program will use parts of memory to store programs and data that are needed for immediate execution, while the bulk of programs and data will remain on disk. A program or data table may occupy completely different areas of memory on each re-execution. This is because the area of memory that is free for use may be impacted by totally unrelated programs that were executing in preceding milliseconds by the time-sharing system. Variable indirect addressing is one of the ways in which minicomputers are able to cope with the fact that programs and data tables may occupy different areas of memory from one execution of the pro-

gram to the next. is only necessary to change a few addresses, such as AABB, in order to change the location of a data table or a program. While this justification for indirect addressing makes a lot of sense in complex minicomputer applications, it makes absolutely no sense in microcomputer applications. When an entire microcomputer system, complete with memory, costs a hundred dollars or less, it will be cheaper to give each user his own CPU and memory, rather than go to the extra programming expense required to
It

share the use of such a low-cost item as a microcomputer.

6-42

Non-time sharing applications can also make effective use of variable indirect addressing. For example, a single data area may be used by a number of data tables of variable
length. Consider a simple telecommunications application. Data
is

arriving over a

telephone

line at

some random

memory. At fixed intervals, a microcomputer program is executed to process the most recent chunk of raw data. Observe that each time the microcomputer program is executed, the data on which it must operate will reside in a different area of read-write memory. If the microcomputer program references read-write
it

rate;

as the data arrives,

is

stored

in

read -write

memory via indirect addressing, then by simply loading the new beginning address of the data area into the indirect address space, the microcomputer program can access the next segment of data wherever it may be:

Memory

One

of

many

indirect addressing

Indirect addressing instruction

instructions,

all

of

which access the

object code

same

data.

Address

XXYY

provided by

indirect instruction.

These two memory bytes contain

the currently effective address.

XXYY XXYY+1

Start of data area

processed data

Raw data

currently begins

here. Store this address at

XXYY and XXYY +

Of course,

1.

XXYY

and

XXYY + must
1

be read-write

memory

location.

6-43

microcomputer that has only implied and direct addressing would have to simulate This could be done indirect addressing to perform the operations described above.
follows: using three instructions for each indirect addressing instruction as

Memory

Load

direct into high order

byte of Data Counter

XX
from

XX YY
direct into

YY
Load
low order byte

XX YY +

of Data
1

Counter
1

fromXXYY +

Implied addressing instruction

object code

XXYY XXYY +

INDEXED ADDRESSING
A number
implied memory addressing as of microcomputer manufacturers describe the same. indexed addressing; the two are similar but they are not address. This may be ilAn indexed address is the sum of a direct and an implied follows: lustrated as

Memory
Data Counter

Indexed addressing
instruction

code
to

XXYY

AA
|

Base address, equivalent direct address of direct

addressing instruction

XXYY +A ABB

-This

is

the addressed

memory

location

6-44

When used as illustrated above,

dex
register.

the Data Counter

is

called an Inin-

Some minicomputers do
1

not have index registers, or

INDEX REGISTER

dexed addressing; most do. Minicomputers that do have indexed addressing may have from to 15 index registers. 16-bit minicomputer indexed addressing may be
illustrated

as follows, for long instructions:

16-Bit

Memory

Index
Register

Indexed addressing instruction

code
Base Address

XXYY+AABB

-This

is

the addressed

memory

location

16-bit

minicomputer indexed addressing may be

illustrated

as follows for short instructions:

16-Bit

Memory

Indexed addressing instruction

Index
Register

code

Base Address

XXYY

+ OOBB

This

is

the addressed

memory

location

6-45

The index
while
bit
it

register derives

its

indexes an area of

name from the fact that its contents is likely to change (for example, memory being treated as a data table). This may be illustrated for a 16-

minicomputer as follows:
16-Bit

Memory
Index
Register

.Indexed addressing instruction

code

AABB

-Table Base Address

AABB-

First

memory

location for data

table

DISP+AABB.

.This

is

the currently addressed

location

memory

Indexed addressing
gives
rise to

may be combined

with indirect addressing, and

this

PRE-INDEXING

two

possibilities;

the index

may be

applied to the base adis

dress, or to the indirect address.

When

the index

applied to the base address,

we

talk of pre- in-

dexed addressing. This may be

illustrated

as follows:
16-Bit

Memory
Index
Register

Pre-indexed addressing
instruction

code

Base Address

This

is

the

memory

location
indirect

which contains the

address

PPQQ-

This

is

the addressed

memory

location

6-46

For pre-indexed addressing, the effective address (EA)

equation:

is

given by the

EFFECTIVE

ADDRESS

EA = [BASE + INDEX]
The square brackets denote "contents
of". In the

above

illustration:

EA = [AABB + XXYY] = PPQQ

Suppose the index
dress
is

register contains. 213A 16

and the base address

is

413C 16

the effective ad-

given by:

EA = [413C 16 + 213A 16 = [6276 16

]

Therefore the effective address

is

the contents of the

memory word

with the address 6276 16

When

the index is applied to the indirect address, we talk of post-indexed addressing. This may be illustrated as follows:
16-Bit

POSTINDEXING

Memory

Index
Register
I

Post-indexed addressing'
instruction

code

XXYY

Base Address

This

is

the

memory

location
indirect

which contains the

address

This

is

the addressed

memory

location

For post-indexed addressing, the effective address (EA)

equation:

is

given by the

EFFECTIVE

ADDRESS
=i

EA

[BASE]

INDEX
of." In the

Again the square brackets denote "contents

above

illustration:

EA = [AABB] + XXYY = PPQQ + XXYY

Again suppose the index
address
is

register contains

213A 16 and

the base address

is

413C 16

the effective

given by:

EA

= [413C 16 ] + 213A 16

6-47

Therefore the effective address

is

the contents of the

memory word

with address

413C

lfi

plus

213A 16

MICROCOMPUTER INDEXED ADDRESSING

An 8 -bit word
size is the feature of
if

microcomputers which dictates

how much

index-

ed addressing,

any. will be impJemented.

in its

Let us begin by looking at indexed addressing

simplest form. For an 8-bit

microcomputer, this

may be

Hlustrated as follows:

Memory

Index
Register

Indexed addressing
instruction

code

Base Address

This

is

the addressed
location

memory

Clearly there

is

some redundancy
sum
valid

XXYY + AABB

cannot

to

in indexed addressing, as illustrated above. more than FFFF ]6 since this is the largest value that a 16-bit ad,

dress can acquire.

Any

indexed address can therefore be rewritten as follows:

Memory

Index
Register

Indexed addressing
instruction

code

Base Address

This

is

the addressed
location

emory

This

is

the effective address:

EA = XXYY + AAOO

= XXYY + AABB

6-48

We

have saved a byte in our indexed addressing instruction, and given up nothing. dexing data tables, this representation of indexing may be illustrated as follows:

In

terms of

Memory

Index
Register

-Indexed addressing
instruction

lAAYYl

code

'Base Address

AABB-

-First

memory

location

for data table

AABB

+ OOYY

-This

is

the currently addressed

location

memory
Since
effect,

we
is

a 16-bit index register, but only an 8-bit memory word, what we are doing in creating the table base address out of the index register high order byte, plus the base

have

address byte. The index register low order byte becomes the table index.

Effective index

Index Register:

Effective base address

Base Address byte

In

sent. This

many

the world of microcomputers, straightforward indexed addressing is rarely preis because we are dealing with an 8-bit instruction code, and if we try to specify too
addressing options,

we

will

quickly run out of

bits.

6-49

Chapter 7

AN INSTRUCTION SET
We are now ready to create a hypothetical instruction set. The instruction set we are
now
Rather,
justify

going to create will not copy any existing microcomputer's instruction set. them; what we must do is it will contain features representative of all of

each feature.

CPU ARCHITECTURE
The first prerequisite, before we can discuss individual instructions, is to select the number and type of registers, plus the number and type of addressing modes that
our hypothetical miocrocomputer will have.

We

will start

with re gisters.

number We cannot simply select a enough for any situation. Remember, every
large
logic,

of

registers

we

more than
have many

NUMBER OF
REGISTERS
is

register

must become chip

if

using up limited

real

estate on the

CPU

chip; also,
bits,

registers,

we

will

use up

many

instruction

code

referenced. Therefore

we must

carefully justify every single register

simply identifying which register we elect to have.

to be

We

are going to select

two Accumulators (AO and AD.

rather than one, simplifies 16-bit data operations, since the as the upper and lower bytes of a single 16-bit unit:

Having two Accumulators, two Accumulators can be visualized

0.

Bit

No.

15

14

13

12

11

10 9

10.

.16-Bit

Representation

16-bit data operations are

seen frequently enough

is

to justify having

two Accumulators.

Having two Accumulators

in parallel; this is

also useful

easier

and

faster with

when data from two tables must be read and processed two Accumulators, which, in effect, provide two indepen-

dent channels for data

Will

transfer.

two Accumulators be than two Accumulators,

registers are

sufficient?

Some microcomputers have more

registers,

or

equivalent

but the additional

DATA COUNTERS

used as Data Counters or memory address registers of three 16-bit Data some form We are going to provide our microcomputer with Accumulators, or Counters (DCO, DC1 and DC2); therefore, we do not need more than two
equivalent registers.
greatly simplifies processing data out of ta-

Why
bles.

have three Data Counters? The answer

is

that

it

(the most obvious examFrequently data from two source tables are combined in some way third table. Microcomputers with less than ple is multi-byte addition) and the result is stored in a addresses between temporary three Data Counters, or equivalent address registers must shuffle of having only one (or two) Data storage in memory, or must otherwise circumvent the limitations

Counters.

7-

Consider the simple case of multibyte addition. Having three Data Counters,
similar operations, are easily

this operation,

and

handled as follows:

Memory

XXXX

DCO
DC1

XXXX YYYY
zzzz
.

YYYY

DC2

'ZZZZ
Original

DC

contents;
will
all

these addresses

be incremented

after

every table access

Having two Data Counters,

either

we would

have to

move one

of the source data buffers (beginning at

XXXX

or

YYYY)

into the

answer

buffer,

then add as follows:

Memory

XXXX

YYYY
DCO
DC1

YYYY
ZZZZ
Step
1

\
/
zzzz
I

XXXX
ZZZZ
n

DCO
DC1

4+ Tic1

Step 2

microcomputer with only one Data Counter would have to store the three table addresses in read-write memory, then load each address into the Data Counter before accessing each table.

somewhere

7-2

microcomputer with indirect addressing could store the three memory, then access tables indirectly via the three addresses:

table addresses in read-write

Memory
Address
Base Page

will

These are original addresses; they be incremented after every

table access.

YYYY

ZZZZ

7-3

11

We

will

give our microcomputer a Stack Pointer (SP) and a Program

(PC).

Counter

CPU
REGISTERS

Our complement

of registers looks like this:

SUMMARY
8-bit 8-bit

Accumulator

ACO
Data Counter

Accumulator AC1
16-bit 16-bit 16-bit

DCO
DC2

Data Counter DC1

Data Counter

16-bit 16-bit

Stack Pointer SP

Program Counter PC

STATUS FLAGS
Chapter 2 we described status flags, and microcomputer w,th the four status flags Z
In

how

they are used.

(Zero).

(Carry).

will prov.de our hypothetical (Overflow) and S (Sign)

We

r 6a T!tI?c registers

ADDRESSING MODES A CO U^' S addressin 9

which have been selected.

6

modes wi " b influenced by the number and type p

' '

of

^ ^ ^ ^ ^S^JSS^T ^
aTan^tTmativT'^^T^^
Since

access,n9 a

C Unter S " kely t0 proV(de ndirect addressing number of data areas; th,s was "

ited

we
'

have three Data Counters,

we

will

^l^S^
follows:
1)

nStrUCt, nS that reference i"*"'

^ Y memor
'

save on instruction code bits, and CPU chip logic bv Wl11 nClUde 3Ut0 inCrement 3nd au
will

be divided into two categories as

two

- Se-men

Load and Store instructions. Because they

will

have a complete, and

are frequently used, these

instructions

flexible set of

addressing options.
'

2>

w T

rnX^^g^:r
b

Cti nS
'

"

=^^
01
1

^ "^ ^ ^ *
eSS

offered

by the Load and store

*"

Address specification

bits for a

Load or Store

instruction.

00 use Data Counter DCO use Data Counter DC1

10 use Data Counter
direct addressing.

DC2
The next two bytes provide the
direct

memory address

If bits and 1 are } 1. these two bits are unused. are not 11. then interpret bits 2 and 3 as follows:

If

bits

and

00
01

specifies simple, implied

memory addressing increment contents of specified Data Counter

of instruction

at

conclusion

10 decrement contents of specified Data Counter at conclusion of instruction

1

increment and skip feature (described with Load and Store

instructions)

7-4

Memory

reference instructions, other than Load and Store, will offer this limited

subset of addressing options:

Address specification
7
I

bits for

memory

reference instructions

other than Load and Store

6 5 4 3 2

10
I I

M M

II

00 Use Data Counter DCO 01 Use Data Counter DC1

10 Use Data Counter
1

Simple, implied

memory

addressing only

DC2
The next two bytes provide the
direct

Direct addressing.

memory

address.

A DESCRIPTION OF INSTRUCTIONS
There are two competing perspectives which we must maintain while evaluating the instructions that are to constitute our microcomputer's instruction set. First, we must decide what instruction types are vital, very useful, or simply desirable; next, we must select instructions that use the 256 possible combinations provided by an 8-bit instruction code; we cannot have more than this number of options.
In order to balance our two perspectives in the following discussion, we are going to create a complete, but hypothetical, microcomputer instruction set. This means that we must justify each instruction, or instruction type, and we must specify the object code pattern which is to be interpreted by the CPU Control Unit as identifying the specified instruction.

INPUT/OUTPUT INSTRUCTIONS
A
microcomputer system would be useless
if it

did not provide

means
is

for receiving data from,

and transmitting data

(I/O) instructions.

to external devices; this

is

input/output and

specified via input/output

An input/output
1)
Is

instruction needs to specify three things:

(input), or is
it

the instruction reading data from an external device ting data to an external device (output)?

transmit-

2)

As we discussed in Chapter 5, most microcomputer systems have, or at least allow, more than one port through which data can be transferred between external devices and a microcomputer system. We must identify the I/O port via
which the input or output operation
is

to occur.

3)

What is the source (for input) or destination (for output), within the microcomputer system, for data being transferred via I/O instructions?

in

Input/output operations are so frequently used in microcomputer applications, that order to save memory, it is a good idea to include a few single-byte I/O instruc-

tions.

We

as the destination), the other

specify

could use just four of the 256 object code options, two for input (one for each Accumulator two for output (one for each Accumulator as the source), then

one

of

256 possible I/O ports

in

an immediate data byte to follow:

Byte Byte

1:

Input or Output instruction.

2:

Using/this I/O port.

7-5

This

scheme
7

for I/O instructions

is

better:

6 5 4 3 2

10
IpIpI

Bit

No.

Mojo IQM

00 specifies I/O port 01 specifies I/O port

1

10 specifies I/O port 2

specifies I/O port specifies input
1

in

the next program byte

specifies output

An

I/O instruction specified

We
is

have used up eight object code options, without specifying which Accumulator involved in the data transfer. These are the eight object code options used by I/O instruc-

tions:

00001000
00001001

Input via I/O Port Input via I/O Port

1

00001010 00001011 00001100 00001101

Input via I/O Port 2 Input via I/O port addressed

by next byte

Output Output Output Output

via
via via

I/O Port
I/O Port
1

00001110
00001
1

I/O Port 2 I/O port addressed by next byte

via

It is going to take an additional bit to specify one of the two Accumulators as the data source or destination in I/O instructions. The eight object code options illustrated above would have to be repeated (perhaps with bit 4 set to 1) in order to represent two sets of I/O instructions, one set accessing Accumulator A0, the other set accessing Accumulator A1 As a result, 16 object code options would be consumed by I/O instructions; and that is unnecessarily extravagant Instead we will stipulate that Accumulator A0 will always be the source or destination of data for I/O instructions.

This preferred use of Accumulator AO will occur frequently in PRIMARY our instruction set, since it is an easy way of reducing the ACCUMULATOR number of object code options used up by any instruction type. By making one Accumulator always more accessible, rather than spreading preference between the two Accumulators, the programmer can think and program in terms of a pnmarv Accumulator (A0) and a secondary Accumulator (A
1
).

We

will

use the following mnemonics for our I/O instructions:

INPUT SHORT

For Input Short: INS P

is the instruction operand, and must be 0, 1 or 2 to specify one of the three I/O ports allowed by a single byte I/O instruction. The Assembler will flag any other

value

in

the operand field as

il-

Next, for Input Long;

INPUT LONG

IN

7-6

This time P
follows:

may have any

value from

through 255.

two-byte instruction

will

be generated as

Input to

AO

Via this I/O port.

For Output Short:

OUTPUT SHORT
OUTS
P
will

This

is

identical to the Input Short instruction,

(0,
1

except that data

be output from Accumulator

AO, through the specified I/O port

or 2 only).

And

for

Output Long:

OUTPUT LONG
OUT
P

This instruction

is

identical to the Input

cumulator

AO

to an external device via

Long instruction, except data will be transmitted from Acany I/O port from through 255.

transfer,

By making I/O instructions access only Accumulator AO as the source or destination for a data we have decided that it is more important to specify a limited number of ports within a
instruction,

one-byte I/O

ratherthan allow either of the two Accumulators to be the data source

or destination.

Referring to the shower temperature controlling example, let us assume that temperature readings arrive through I/O Port 0, while controls are output to the hot water valve via I/O Port 1 I/O Port 2 is used as a common status port for inputs and outputs. Information at these I/O ports will be interpreted as follows:
.

I/O Port

0:

millivoltage, ranging

from

mv
F

through 255 mv. Temperature,

in F,

may be

ap-

proximated as follows:

=30

+ 0.45 mv.

I/O Port

signed binary number, specifying the hot water valve must be opened (positive) or

closed (negative). The

solute value

amount

of valve

movement

will

be proportional to the ab-

through 127.

I/O Port

2:

Bits of this port will

be interpreted as follows:

I/O Port
7

I/O Port

6 5 4 3 2

hliloi Hi
l

10 loM
1

Bit

No.

\ k_

= New data at I/O Port = No new data at I/O Port = New data has been read = New data has not been read

Not, Used
1

= New data at I/O Port = No new data at I/O Port = Retransmit last data value = Last data value read and OK = Ready to receive data at I/O Port = Not ready to receive data at I/O Port
1
1
1

Not Used
In

the Port 2

illustration,

represents bits input by an external device;

represents

bits

output by

the CPU.

7-7

11

MEMORY REFERENCE INSTRUCTIONS

data arriving from a temperature sensor arrives in multibyte units, each data byte that is loaded AO by an input instruction must immediately be stored in read-write memory. Data output to the hot water controller must be read from memory, loaded into AO. then output via an output instruction. The data output to the hot water controller depends on the data input from the temperature sensor; in the process of computing the data to be output, any
If

into

stantly reference data in

memory

program

will

have

to con-

to load, store, add,

perform

logical operations, etc.

basic architecture of any computer, mini or micro, provides a very limited data storage in CPU registers, and a (relatively) enormous data storage capacity in memory external to the CPU. This makes memory reference instructions the next most vital, after I/O instructions. Recall from Chapter 5 that some microcomputers treat I/O instructions as a subset of memory reference instructions, by assigning specific memory addresses to I/O ports.

The

capacity

As might be expected, the two most commonly used microcomputer memory reference instructions merely move data to or from memory; these are the Load and Store instructions.

Load instruction moves data from a memory location

to

an Accumula-

LOAD

tor.

I 1

Store instruction

moves

data from an Accumulator to a

memory

loca-

I
*

tion.

STORE

These being the two most commonly used memory reference instructions we will spend the bits needed to include in the Load and Store instruction very flexible addressing modes.
Load and Store instruction object codes
will

appear as follows:

^6543210
1

Bit

No

01

00 Use Data Counter DCO Use Data Counter DC1

10 Use Data Counter
1

DC2
The next two bytes provide the
direct

Direct addressing.

memory

address.
If

If Bits and 1 are 1 1, these two bits are unused. are not 11. then interpret bits 2 and 3 as follows: 00 Specifies simple, implied memory addressing.

bits

and

01

Increment contents of specified Data Counter

of instruction.

at

conclusion

10 Decrement contents of specified Data Counter at conclusion of instruction.

1

Increment and skip feature Reference Accumulator

A0

Reference Accumulator

Load
1

Store

Load or Store

instruction

now look at the complete addressing capabilities offered by the Load and Store instructions, starting with the simplest.
Let us
After describing

what the addressing modes

are.

we

will justify

each one.

Load or Store instruction with direct addressing will have 1s

and
1.

DIRECT

in bits

and the

direct address will

bits

be provided

in

the

two bytes

ADDRESSING
must both

that follow.

Observe that

2 and 3 are not used for direct addressing;

they must, however, have a definite value.

We

will

therefore specify that bits 2 and 3

will

be

for a direct

addressing Load or Store instruction; these instructions

now

have the follow-

ing object code;

Byte

0/

Load

into

Accumulator

or

Byte 2

the contents of the

memory

location addressed by these

Byte 3

two bytes

Byte

1"

Store the contents of Accumulator

into the

or

Byte 2 Byte 3

memory

location addressed by these

two bytes

The following
7

object codes have nothing to

do with Load

or Store instructions:

6 5 4 3 2
1

10
lilil

Bit

No.

lohl
J
I
k

-Direct addressing

if

bits 2

and 3 are both

if

.Not a Load or Store instruction

these two

bits are 01,

10 or

1.

.These two

can have any value and not represent Load or Store instruction if bits 2 and 3 are not both 0.
bits

.Normally specify a Load or Store instruction.

There

from Load and Store instruction object codes. Twelve of the combinations do not represent Load or Store instructions, as illustrated above (3
are

64 object code combinations

resulting

01XXXXXX, where X may be

or 1; these are the

NUMBER OF LOAD AND

STORE
INSTRUCTIONS

combinations of

bits 2

and

3,

times 4 combinations of

bits

4 and

5.

equal

12 combinations). Therefore, there are 52 variations of the Load and Store instructions.

Load and Store instructions with implied

have any of the following object codes:
7

memory addressing

can

IMPLIED

ADDRESSING

6 5 4 3 2
I

10
| |

lohj

lolol

00 Address
01

implied by

DC0

Address implied by DC1 10 Address implied by DC2

Simple, implied

memory

addressing

Reference Accumulator
1

A0

Reference Accumulator A1

__0 Load
1

Store
or Store instruction

-Load

7-9

The

effective memory address for the Load or Store instruction DCO, DC1 or DC2, whichever has been specified by bits and

is
1.

the contents of Data Counter

Introducing the auto increment and auto decrement feature is quite easy to understand; the auto increment feature says that the implied
will

AUTO
INCREMENT

memory

address, that
1

be incremented by
will

the contents of the specified Data Counter, at the conclusion of the memory reference inis.

struction. Conversely, the

Counter contents
struction.

auto decrement feature specifies that the Data be decremented by at the conclusion of the in1

AUTO DECREMENT

The object code

struction will

for

an auto increment instruction

in bits

equivalent object code only

3 and
2.

2.

which

will

will differ from the implied addressing be 01, the equivalent auto decrement in-

have 10

in bits

3 and

Increment and skip, specified by having not a common microcomputer feature.

Load and Store

1 's in

bits 2

and

3, is

INCREMENT

We

are going to create

AND SKIP

instructions with the following format:

/Load
7

6 5
?1

3 ?
1

or Store, then increment contents of the Data Counter specified by bits and 1; then check contents

Byte

Jnjl}

ofDataCounte
<

Byte 2

\jtrW

the last 6 bits of the Data Counter contents are 000000, increment the Program Counter to bypass (and ignore) this byte. If the last 6 bits of the Data Counter have any other value, treat this byte as a signed binary number, to be added to the Program Counter contents,

forcing a Branch.

The most effective way of illustrating the necessity for the various addressing modes is with short program sequences. Let us therefore first describe the instruction mnemonics which will be used for the Load and Store instructions.
Load and Store
Direct will use these

mnemonics:

LOAD DIRECT

LRA
LRB

SRA
SRB

ADDR ADDR ADDR ADDR

Load Load

direct into direct into

A0
|

STORE DIRECT

A1

Store direct from Store direct from

A0
A1

ADDR
data
digits

is

will

instruction

any symbol representing a memory location from which data will be read or to which We use the letter A to represent A0 and B to represent A1; we could use the and 1, but it is too easy to confuse and O. and with therefore, use of and 1 within
be written.
1
I;

mnemonics

is

unpopular.

Load and Store Implied

will

use these mnemonics:

LOAD IMPLIED
memory
location

LMA
LMB

DCX DCX DCX DCX

Load

into

A0

from the

STORE IMPLIED
|

addressed by

DCX
memory
location

Load

into

from the

addressed by

DCX

SMA
SMB
DCX
specifies

Store the contents of

A0

into the

memory

location

addressed by

DCX
A1
into the

Store the contents of

memory

location

addressed by

DCX
and therefore must be DCO, DC1 or DC2.

one

of the three Data Counters

7-10

The Load
will

or Store with

Auto Increment
will

or

Auto Decrement

instructions

be

identical to

Load/Store Implied, as described above, except that

the specified Data Counter contents

be incremented or decremented.

We

for Load with Auto Load with Auto Decrement, SNA and SNB for Store with Auto-Increment and SDA and SDB for Store with Auto Decrement.
will

use the instruction mnemonics

LNA and LNB

LOAD/STORE WITH AUTO INCREMENT OR DECREMENT

Increment,

LDA and LDB

for

specified by the following instruction

Load and Store instructions with Auto Increment and Skip mnemonics:

will

be

LOAD/STORE WITH AUTO INCREMENT

LSA
LSB

DCX, LABEL

Load Load

into

AO
A1

AND SKIP
AO

DCX.LABEL DCX.LABEL DCX.LABEL

into

SSA
SSB

Store contents of Store contents of

A
memory
will

DCX
DC1

identifies the

Data Counter holding the implied

address;

it

must therefore be DCO,

or

DC2.
is

LABEL

symbol
last six

identifying the instruction

which

be executed next

if.

after

DCX

is

incre-

mented, the
In

binary digits are not

all

zeros.

order to demonstrate the

addresses of

at a simple problem
starting

power of the Load and Store instructions, let us look which moves data from one buffer to another. Assuming that the the source and destination buffers are in Data Counters DCO and DC1, and
is

assuming
follows:

that the buffer length

stored

in

Accumulator A1, the problem may be

illustrated

as

Data

Memory

XXXX
Move raw

zz <

data input

by thermometer

*^

AO
A1

ZZ

DCO
DC1 DC2

XXXX YYYY

YYYY

ZZ<

To data

buffer

where data

is

held

while being processed

XXXX YYYY
ZZ
is

is

the beginning address of the input data buffer.

the beginning address of the output data buffer.

is

the length of each data buffer.

7-11

The following

instruction

sequence

will

perform the required data move:

LOOP

LMA SMA

DCO
DC!

Load next input data byte

Store
in

next destination buffer byte

DCO contents Increment DC contents

Increment
1

Decrement A1 contents
If

A1 contains
which

0.

branch to

LOOP
in

Instructions

we

have not yet described are written out

words, rather than using un-

familiar instruction

mnemonics.
this
is

Now we

will

introduce the auto increment feature, and

instruction

what hap-

pens to our

sequence:

LOOP

LNA

AUTO INCREMENT OR DECREMENT

JUSTIFICATION

DCO
DC1
1

Load next input data

Increment address.

byte.

SNA

Store

in

next destination buffer byte. Increment address.

Decrement A
If

contents
0,

A1 contains

branch to

LOOP
six instruction

Two

instructions have been removed from the program code have been saved.
that the destination buffer

sequence and two bytes

of object

Now assume
the
last six

ends

at

memory
zeros:

location

08C0

binary digits of this address are

all

08C0 16 = 000010001100*3000

AUTO INCREMENT AND SKIP

JUSTIFICATION

We

can

now compress

our data

move program

to these

two

instructions:

LOOP

LNA
SSA

DCO DC LOOP
1,

Load next input data byte; increment address.

Store,

increment and skip on end.

bytes, as follows:

These two

instructions

occupy three

C
We
A

,0
1

Q
1

Load A0
1

via
via

DCO; increment DCO

DC1; increment DC1 and skip
of 2

Store

A0

Twos complement

Increment and Sk,p instrucfionmcrements the destination buffer address, it tests the incremented value; if the incremented value does not end in six binary zero digits, execution will return to the Load instruction- this twoinstruction loop will be continuously re-executed until the Store, Increment and Skip instruction does increment the destination address to 08C0 16 at this point the branch will be bypassed and the instruction which immediately follows the above data movement loop will be executed.
;

no longer need to hold the buffer length in Accumulator A1. Nor do the buffer, length, or increment memory addresses. After the Store,

we need

to

decrement

minicomputer programmer would recoM at an addressing scheme such as the auto increment and skip. The idea that data tables must be
placed at
six binary

zeros poses more problems than

memory addresses ending

in

it

offers advantages.

7-12

While the minicomputer programmer may see the neatness of instruction loops that require no special end-of-loop logic, problems associated with data relocation would be horrible; if a program were to be re-used in another application, or if it were part of a time-sharing system, the programmer would constantly have to worry about ensuring that data tables ended at correct

memory boundaries

or else the

program would simply not work.

We

minicomputer programmer's axiom: "Remember return once that whatever you do today may impact tomorrow." But remember that in the world of microcomputers there is no tomorrow. Whatever you do today becomes a ROM chip and minor will never again change. Mapping data tables onto memory address boundaries is only a inconvenience, since memory mapping will be a significant part of every microcomputer programming assignment anyway. When the ROM chips that result from your program may be
again to the old
reproduced thousands of times, you
the fewest, smallest chips possible.
will

want

to

be absolutely sure that your program resides

in

The auto increment and

penalty paid
that

microcomputer application because

skip feature offers very significant advantages in a it saves on object program bytes, while the is part of a job having to map data tables onto address boundaries

must be done

in

any event.
instruc-

We have not yet justified the need for direct addressing

tions.

DIRECT

Are they necessary?

is

ADDRESSING
JUSTIFICATION

There

nothing a direct addressing instruction does which could not be

implied addressing instruction;
in

done with an
tions use less

certain cases,

memory. Consider the

In

buffer length

which
in

we were

however, direct addressing instrucgoing to load into Accumulator

A1, and then decrement.

the end

we

eliminated this logic sequence from our data

instances
similar

movement

example, but there are going to be

nated.

many

which

this

type of logic cannot be elimiinto the

How

does the buffer

length, or

any

three-byte direct addressing instruction will

number, get loaded do the job as follows:

Accumulator?

Program

Memory

01000011

Load

direct into

A0
location with this

From the memory

address

To A0-

7-13

Using implied memory addressing the operation Data Counter as follows:

will require four

bytes and

will

temporarily

Program

Memory

Load immediate
1

into

DC0

These two bytes

Load
into

01000000

AO

via

DCO

This byte

addressed

To AO

The three-byte .mmediate

necessary expense,
to load

instruction
it

which

is

needed

to load data into a Data

when

Counter

is

an un-

is

followed by a s.ngle

memory

of an index into another register; as

an address
in

the address
If

we have seen earlier in this chapter, the three bytes needed Counter result in a great subsequent memory savings, but only if the Data Counter is going to be re-used many times.
into a Data
is

reference, such as the one-time load

microcomputer

the

more

to have either direct addressing or implied addressing, implied addressing

desirable; for example, the Intel 8008.

,s

which was the predecessor

implied addressing but no direct addressing.

of the Intel

8080 has

to

Most programs load single values (such as counters and indexes) make direct addressing justifiable.

into registers frequently enough tyenuugn

G C er 0r ndeX t0 be l09ded mt0 9 reg Ster h9S a value that Wl change, " use neither , direct nor implied addressing to load the value into a register. You would use immediate addressing:

^1", t would
you

'

'

Program

Memory

Load

into

A0
of this byte.

The contents

7-14

1 1

SECONDARY MEMORY REFERENCE (MEMORY REFERENCE OPERATE) INSTRUCTIONS

Let us now look at memory reference instructions other than Load and Store. In each case an operation will be performed using the contents of one of the Accumulators, plus the contents of an addressed memory location. The result will always be stored in the identified Accumulator, erasing whatever value had previously been in the Accumulator (the Compare instruction described below is an exception). The Zero, Sign, Carry and Overflow status flags will be set or reset to reflect the result of the operation. For example, the "Add memory to A1" instruction will add the contents-of the addressed memory location to the contents of Accumulator A1. The previous contents of memory are- not
changed.

With the exception of the Store instruction, microcomputer instructions memory since that implies the presence of read-write, memory.

will

avoid modifying

ADD ADD DECIMAL

SUBTRACT DECIMAL

We

will include

these secondary

memory

reference

in-

AND
OR XOR

structions:
7

6 5 4 3 2

10

COMPARE
00 Use Data Counter DCO
Simple, implied

memory

_01 Use

Data Counter

10 Use Data 1 Direct addressing. The next two bytes provide the direct

DC Counter DC

addressing only

memory

address.

000 Add binary 001 Add decimal 010 Subtract decimal

01
"

AND
OR
Exclusive

100
101

OR

110 Compare 111 Not Used

Use Accumulator A0 Use Accumulator A

Secondary memory reference instructions

These are the instruction mnemonics

we

will use:

ABA

or or or or or or or

ABB

Add

Binary to

ADA
DSA

ADB
DSB

Add Decimal
Decimal

A0 or Al A0 or A1 Subtract from A0
to

or

ANA ORA
XRA

ANB ORB
XRB

AND
OR

with

A0

or

CMA

CMB

A0 or A OR with A0 or A1 Compare A0 or A1 with memory

with
Exclusive

7-15

The code "10"

in bits 7 and 6 specifies that the remaining six bits represent secondary reference instructions. However, only seven of the eight combinations possible for bits

memory

2,

are used for secondary

tions are,
In
in fact,

secondary

memory reference instructions. Therefore, memory reference instructions.

will

only 56 of the 64

bit

3 and 4 combina-

each case, the instruction

be written out

like this:

MNEM
where

DCX
is

MNEM

one

of the

mnemonics

listed

above

(e.g.,

ADA), and

DCX

is

one

of the

Data

Counters (DCO, DC1 or DC2).

The

direct

memory

referencing version of the instruction

will

look

like this:

MNEM
where

ADDR
the direct address.

ADDR

is

Here are two examples. The instruction:

ABA

DC

d A USmg binarv addlt,oa the contents of the memory location whose address !l ' ?f 1X1. This by is the object code generated:
7

is

implied

6 5 4 3 2

10

olololololofT]

^pL_
is

.Address implied by DC1

binary

-Add
.To

A0
is

.This

a secondary

memory

reference instruction

The following

a direct

memory

referencing instruction:

XRB

ADDR
'

h C n f A1 S XCluS e - Red Wlth the contents of the memory location addressed by ^ mb olTn nR These three object program bytes will : symbol ADDR. Th be created:

This

is

secondary

memory

reference instruction.

Reference

Exclusive-OR

7
1

5*4 3 2
1
1

XjF
1 1
1

direct addressing specified

These two bytes contain the 16-bit address represented by the symbol ADDR

Only two of the seven secondary memory reference instructions described above auvc need any comment.

Add and subtract decimal perform decimal addition two binary steps, as described for binary-coded
7-16

or subtraction, using three or

in

decimal arithmetic

Chapter

2.

We
We

perform decimal subtraction using a separate instruction, since the logic sequence

is

suffi-

ciently different

from a decimal add to make the extra instruction worthwhile.

a separate binary subtract instruction, since this
in
is

do not provide

BINARY

simply a twos complement followed by an add, as described

Chapter

2.

SUBTRACT
DECIMAL ADJUST
majority of

Note

carefully that the decimal addition

and subtraction

instructions are

not the

same

thing as a decimal adjust instruction. Decimal adjust simply

takes the contents of a register and re-arranges the bits to create the

decimal equivalent of the binary number;

this

is

explained

in

Chapter

2.

microcom-

puters offer a decimal adjust instruction; a minority offer decimal arithmetic instructions.

The Compare
dressed
result

instruction subtracts the contents of the ad- | COMPARE | location from the specified Accumulator; the it is not stored in the specified Accumulator. However, of the subtraction is discarded

memory

the Z status
tion since
it

bit is set

or reset to reflect the result of the subtraction. This

is

a very useful instruc-

allows the program execution sequence to be determined by the relative magnitude

of data items.

The Branch on Condition

of,

and are used

in

instructions, described later in this chapter, take advantage conjunction with the Compare instruction.

Are the secondary memory reference instructions necessary?

This question must be
First,

SECONDARY

answered two ways:

MEMORY
memory
reference

are the operations performed by the secondary

REFERENCE INSTRUCTIONS
JUSTIFICATION

instructions necessary?

Second, must these operations be performed using secondary

reference instructions?

memory

addition. Boolean logic and compare, are such basic steps in any The operations described logic sequence that a microcomputer that did not offer these logic capabilities, one way or another, would be worthless.

There

however, no reason why these operations have to be part of memory reference instrucexample, it would be possible to load the two operands into Accumulators AO and Al, then to perform the same operations, register-to-register. Microcomputers which have many Accumulators, such as the Intel 8080, favor register-to-register instructions over register-to-memory
is,

tions. For

instructions;

register-to-memory instructions as
Let us look at a simple example.

microcomputers with fewer Accumulators, such as the Motorola M6800. use we have described.

Suppose the two

illustration)

buffers beginning at
single,

XXXX

and

YYYY

(in

the preceding
in

each hold a

multibyte number.

buffer beginning at

XXXX

could be added to

The number the number in the

the

MULTIBYTE ADDITION

buffer

beginning at

YYYY

as follows:

Initially

clear the carry status

LOOP LMA DCO

Load the next input byte

ABA
SSA

DC1

Add

binary from

answer

buffer

DC 1, LOOP

Store the result, increment and skip

7-17

The above
stored
will
in

This

was just added; therefore, may be illustrated as

First

program assumes that the buffer beginning at YYYY (this address is contains one of the numbers to be added, but at the end of the addition this buffer contain the answer. This logic works, since the answer is going to over-store the byte which

three-instruction

DC 1)

information
follows:

is

destroyed only when

it

will

not be needed

in

the future

Second Source

Source

And

Destination

Another three instruction loop can perform a binary addition where the result buffer, which we will assume is addressed by DC2. The three instructions

is

stored

in

a third
this

will

looTl^e

LOOP LNA
SSA

DCO
DC2.LOOP

Load next augend byte

ABA DC1

Add

corresponding addend byte

result,

Store the

increment and skip

An example

of the usefulness of the Boolean secondary memory reference mstructions is to test switches for setting changes.

BOOLEAN
LOGIC JUSTIFIED

Suppose the status of eight switches are input to I/O Port settings for these eight switches are stored in memory

4-

the previous

dressed by the symbol SWITCH. The following instruction sequence identifies which switches have changed settings and how the settings have

at a location

ad-

SWITCH CHANGE
TESTS

,N

Input

new switch settings

changed switches
in

XRA SWITCH
Save contents

Identify

of

AO

A1
switches that turned on

ANA SWITCH
This
is

Identify

what the above three

instruction inputs the

instructions do;

The

first

new

switch settings to AO; suppose these settings are:

01100101

7-18

Where

represents an "off" switch and

represents an "on" switch-

Suppose the previous switch SWITCH, are:

10101101

settings, stored in the

memory

location identified by the

symbol

Switches 7 and 3 were "on", and are

5, 4, 2,
1,

now

"off".

Switch 6

was

"off",

and

is

now

"on". Switches

and

have not changed.

The XRA
settings
in

instruction leaves the Exclusive-OR of the old

and new switch

EXCLUSIVE-OR

A0:
Old Settings

New

Settings:

10101101 01100101
1 1

XRA
The changed switches
are identified by
1

00 000
1

gives changed switches

bits,

and are stored

in

A1.

^___
\

The AND instruction leaves the changed switch settings in A0:

AND

of the old switch settings, and the

AND

Changed

Settings:

Old Settings

11001000 10101101
10001000
gives on-to-off switches.

ANA

LOAD IMMEDIATE INSTRUCTIONS,

JUMP AND JUMP-TO-SUBROUTINE

The concept
of immediate addressing has been discussed frequently as a means of instrucloading data or addresses into registers. How vital are immediate addressing tions to a microcomputer instruction set? an address into a Data

We cannot use implied memory addressing to load

Counter, since implied

addressing requires a Data Counter to already hold an address. Direct addressing could do the job. A base address stored in two memory bytes could be directly addressed, and

memory

IMMEDIATE INSTRUCTIONS
JUSTIFICATION

loaded into a Data Counter, as follows:

Load

direct into

DC0

XX XX

Starting at this address

DC1

xxxx

7-19

But the above illustration clearly has some redundant bytes; the address being loaded into the Data Counter could just as easily be stored in the two direct memory address bytes as follows:

Load immediate

into

DCO
DC1

YY YY

Immediate instructions are not absolutely vital to a microcomputer instruction set, but they are certainly a great convenience; we will therefore include eight immediate addressing instructions: to load data into the three Data Counters, the Stack Pointer, the Program variations) or the two Accumulators. These will be either two- or three-byte instructions; since the Accumulators are only one byte long, immediate instructions that load data into an Accumulator will be followed by just one byte of immediate data. The Data Counters the Program Counter and the Stack Pointer are all two bytes long; therefore, immediate

Counter (with two

instructions
data.

that load data into any of these registers will be followed by two bytes of immediate following object code patterns will specify immediate instructions:

The

JL
7

6 5 4 3 2

jl 10
I
I 1

Immediate instruction specified

Bit

No.

hlol I1I1I1I

000 Load immediate DCO 001 Load immediate DC 1 010 Load immediate DC2 011 Load immediate SP
100 Load immediate PC (Jump) Load immediate PC (Jump to subroutine) 110 Load immediate A0
101 111

Load immediate A1

Since there are eight immediate instructions, and there were eight unused object code combinafrom within the secondary memory reference instruction group, we use these eight unused combinations for immediate instructions, as illustrated above.
tions

Special attention must be given to the two instructions which load immediate data into the Program Counter; unlike the other immediate instructions, these two modify the program

JUMP
INSTRUCTION

execution sequence; the next instruction executed is going to be fetched from the memory location whose address was loaded immediately into the Program Counter

7-20

In its

simplest form, this

is

an Unconditional

Jump

(or

Branch) instruction:

Program

Memory
0401

0402

10111100
41

Load immediate

into

PC

PC
St

^s

0405

if 0403
1^0404
/
0405
I

2A

These two bytes

This instruction

will

be executed next.

V.

4129

^>412A
412B

412C

412D

Jump-to-Subroutine instruction differs only in that the curProgram Counter contents must be saved before the new immediate data is loaded into the Program Counter; since our
rent

JUMP TO
SUBROUTINE INSTRUCTION
is

microcomputer has a Stack, the Program Counter contents

onto the Stack
(as

will

be pushed

described earlier

in this

chapter), before the

.

immediate data

loaded into the

Program Counter:

Stack

04
05

~*

Old top of stack

New

top of stack

Jump to
PC

subroutine

Starting at this address

This instruction wi

be executed

next.

Most microcomputers' instruction set descriptions do not include Jump and Jumpto-Subroutine instructions in the immediate instruction category; instruction logic is, however, almost identical.

7-21

Instruction

mnemonics

for

immediate instructions

will

be different

for

Jump and for the straightforward Load Immediate instructions. For Load Immediate we will use the following mnemonics:
LIM

LOAD IMMEDIATE

R.DATA

R must be AO, A1. DCO, DC1, DC2 or SP. DATA must be a number, or a symbol representing a number; it must be equivalent to an 8-bit value if R is AO or A1, it must be equivalent to a 16-bit
value otherwise.

The Jump

instruction will appear as follows:

JUMP

JMP
ADDR must
be the

ADDR
label of the instruction

which

is

to

be executed next.

The Jump-to-Subroutine
JSR

instruction will appear as follows:

JUMP TO
SUBROUTINE

SNAME
label of the
first

SNAME

must be the

instruction

executed within the subroutine.

We

will

now

create a subroutine.

Let us return to the data

move program
fully, this

that illustrated the Increment-andin-

SUBROUTINES

Skip instruction; written out

program would include additional

structions to load addresses into Data Counters, as follows:

BUFA
BUFB

EQU EQU

XXXX YYYY

LIM LIM

DCO.BUFA
DC1.BUFB

Load Source

initial

address

Load Destination

initial

address

LOOP

LNA SSA

DCO

Move

data from Source

DC LOOP
1,

to Destination

The EQU mnemonics represent Assembler Equate

Recall that

directive.
it

an Assembler directive

is

not an instruction, and

generates

EQUATE ASSEMBLER
DIRECTIVE

no object code; instead it provides the Assembler with information without which the Assembler could not generate an object program.

EQU

identifies

an Equate directive;

this directive tells

in

the label field occurs, the the Assembler:

the Assembler that wherever the symbol

in

number

the operand field

must be

substituted. For

example
'

it

tells

"Use the hexadecimal value

XXXX

wherever you see the symbol BUFA."

We

could just as easily rewrite our program as follows:

LIM
LIM

DCO.XXXX

DC 1. YYYY

LOOP

LNA
SSA

DCO DC 1, LOOP

7-22

The advantage of having the Equate is that the symbol BUFA (or BUFB) may appear many times within a program. the value assoIf

ASSEMBLER
DIRECTIVES

THEIR VALUE symbol changes, all you have to do is change one Equate in the source program. When you re-assemble the source program, every reference to the changed symbol will be corrected in the new object program which the Assemciated with the
bler creates.

Without the Equate

directive,

you would have to

find every source

program

instruction that

references the changed symbol, then you would have to correct each source program instruction,
with no guarantee that you found

them

all.

moving program into a subroutine, all we do is give a label to the instruction which is to be executed first, and to add an instruction which executes a return from the subroutine:

To

turn the data

JUMP TO
SUBROUTINE

MOVE
LOOP

LIM LIM

DCO,

BUFA

Load source

initial

address address

DC1.BUFB

Load destination

initial

LNA
SSA

DCO

Move

data from source to

DC 1, LOOP

destination

Return from subroutine

The Return-from-Subroutine
the Return logic for now.

instruction

is

described with the Stack instructions;

we

will

ignore

Other programs can

call

the subroutine with this one instruction:

JSR
Subroutine

MOVE

MOVE

can be called by any other program, any number of times.

IMMEDIATE OPERATE INSTRUCTIONS

limited number of Immediate Operate instructions will be very useful; these instructions will perform operations on the contents of an Accumulator plus the immediate operand, storing the result back in the specified Accumulator. Consider these

instructions:

J^
7

6 5 4 3 2
I

T?T
10
hi liMI

An immediate

operate instruction

is

specified

lohl

Select
~1

A0

Select

.00
01

Add immediate

AND

immediate

10
1

OR immediate
Compare immediate

7-23

11

Each

instruction describes

an operation that

will

be performed using the contents of an

Accumulator, and the byte following the instruction code:

Program

One
Accumulator

Memory
t

Immediate Operate

instruction

The status
tion.

flags C, O,

Z and S

will

be set or reset to

reflect

the results of the opera-

Observe that we have used eight of the twelve unused object code combinations from the 64 Load/Store patterns 01XXXXXX. These four combinations still remain unused within this pattern:

01000111 01010111 01100111 01110111

These four combinations may be represented
by:

01XX01

1.

We

will

use the following mnemonics

for the

Immediate

Operate instructions:
AIA
AIB

ADD IMMEDIATE AND IMMEDIATE

OR IMMEDIATE

NIA
NIB

OIA
01B CIA
CIB
In

DATA DATA DATA DATA DATA DATA DATA DATA DATA

is

Add immediate

to

A0

Add immediate toA1

COMPARE
IMMEDIATE

AND immediate to A0 AND immediate to A

OR immediate with A0 OR immediate with A
Exclusive-OR immediate with

A0

Exclusive-OR immediate with A1

each case.

number

bytes of object code

will

(or a symbol) that becomes an 8-bit value. In each case, two be generated. For example, the OIB instruction will create this object

code: Byte
1 1

ill

OR immediate
the data
in this

with
byte

Byte 2

I
at

We
2

will

now demonstrate the

how.

value of the Immediate Operate

in

instructions. Look again

the I/O instruction description. Port

IMMEDIATE OPERATE
INSTRUCTIONS
JUSTIFIED

was defined

as a combination control and status port.

if

These two
INS

instructions determine

there

is

new

data at I/O Port 0:

Input status

NIA

H'OV

Mask out

all

but the

bit

H'OV means 01 hexadecimal.

7-24

The NIA

instruction resets to

all

bits in

Accumulator other than

bit 0:

INS

A0 Contents XXXXXXXX
0000000X

NIA

HOT

X
If

represents either
the result
is

or

zero, bit

must have been zero, and no new data is at I/O must have been 1, so there is new data at I/O Port 0.
zero, bit

Port 0;

if

the result

is

not

Recall that the

result.

Z status

will

record whether the NIA instruction generates a zero or a non-zero

After reading data from I/O Port

bit
1

0,

the program can reset

bit

of the I/O Port 2 to 0,

and can

set

to

1.

using these four instructions:

INS

2 H'FE' H'02'
2

Input status

NIA

Clear

bit
1

OIA

Set

bit

to

OUTS
This
is

Retu n the result

2ns'. what happens

INS

2 H'FE' H'02'
2

NIA

OIA

OUTS

A0 Contents XXXXXXXX XXXXXXXO XXXXXX10 XXXXXX10

1).

I/O Port 2 Contents

XXXXXXXX XXXXXXXX XXXXXXXX

XXXXXX10

Again X represents any binary

If

digit (0 or

you are unclear on

how

the

AND

and

OR

ANDing I/O

Port 2 contents with 11111110, then

work, refer again to Chapter 2. All we are doing ORing the result with 00000010.

is

BRANCH ON
CONDITION INSTRUCTIONS
to this point, status flags Zero (Z), Carry (C), Overflow (O), and Sign (S) have been useless curiosities, because the microcomputer provides no way to take advantage of the status flags.

Up

What

is

the logical

way

of using status flags?

The answer is to provide instructions which allow program execution sequence depend on the condition of a status flag.

to

We have already seen two examples of how status flags can determine the subsequent course of
for a zero or

program's execution. In the Immediate Operate instruction description, bit of I/O Port 2 is tested non-zero value. If this bit has a zero value, program execution must branch to some instruction sequence which does not attempt to read new data from t/O Port 0. If this bit is 1, the program execution sequence must branch to a routine which will input data from I/O Port 0.

The discussion
the
last

buffer length into

Load and Store instruction categories started out with a routine that loads Accumulator A 1, then decrements the contents of A 1 as a means of testing if program buffer byte has been moved; so long as A1 has not decremented to zero,
of

7-25

execution returns to the beginning of the data move loop; as soon as the contents of A1 decrements to zero, program execution must continue and not branch back:

LIM LIM LIM

AO.LENGTH
DCO.BUFA

Load buffer length

Load source buffer
starting

address address

DC1.BUFA

Load destination buffer Load next input data

starting

LOOP

LNA SNA
AIB
If

DCO
DC1
H'FF'

byte,

increment

DCO

Store next input data byte, increment

DC1

Add

H'FF' to A1; this

decrements

A1 does not contain A1 does contain

0,

0, return to

LOOP

If

continue with next instruction

While the AIB instruction (which has already been described) in effect decrements the contents of A1, a Register Operate instruction (which has not yet been described) does the job in one byte,
instead of two.

Branch on Condition instructions are vital to a microcomputer because they are the means of testing status flags; status flags in turn are vital to a microcomputer because they are the means for determining what happends when an instruction executed with more than one
possible result.

BRANCH ON
CONDITION INSTRUCTION
JUSTIFICATION

There are two philosophies concerning Branch on Condition instructions; one uses Branches, the other uses Skips.

Branch on Condition instruction, as the name implies, has a one- or two-byte displacement following the instruction code
(just like

BRANCH
PHILOSOPHY

immediate
is

data).

If

a specified condition

is

met, then the dis-

placement

added
is

to the contents of the

a program branch

executed.

If

the specified condition

Program Counter as a signed binary number, and thus is not met, the Program Counter is increinstruction
is

mented beyond the displacement bytes and the next sequential

This

executed.

may be

illustrated

as follows:

Memory
Address
142 A

Program

Memory

142B

142D

PC

142C

Branch on condition

142D
142E

3A

Displacement byte

/.
is

142F

if

142D + 003Aif
condition

is

not met.

met.

The Skip on Condition placement. The logic

instruction has no following address disof this instruction

SKIP

states that if the specified status conditions are met, then the next sequential in-

PHILOSOPHY

7-26

'

struction will be skipped;

tial

if

instruction will

be executed. This may be

the specified status conditions are not met, then the next sequenillustrated as follows:

Memory
Address
142 A

Program

Memory

142B

142D

PC

142C

142D
142E
142F

Skip on condition

J Next instruction

/
2D
if

i r

condition

142F

if

condition

is

not met.

is

met.

In

the
it

illustration

above, observe that "Next instruction" happens to be a two-byte instruction;

instruction" a three-byte instruction, the

were
dition

a one-byte instruction, the Program Counter

was

met.

Were "Next
if

would be incremented to 142E 16 the conProgram Counter would be

,

if.

incremented to 1430 16

the condition

was met.
on condition
instruction,

By including an Unconditional

Jump

instruction directly after a skip

you

create the inverse of a Branch on Condition instruction:

Memory
Address'
142 A

Program

Memory
142D
Skip on condition

142B
142C

PC

142D
142E

Jump
\ to this

unconditional

address
if

/
1
f

142F

1430

1430

condition

142D, then
contents of 142E

is

met.

and 142F
condition
is

if

not met.
is

Observe that the auto increment and skip form of Skip on Condition instruction.

logic available with

Load and Store

instructions

Should our microcomputer include Branch on Condition or Skip on Condition instructions? will choose Branch on Condition instructions because they are a little more economical with this type of two-way execution sequence:

We

Data

Movement Program Loop

LOOP

LNA SNA
AIB

DCO
DC1
H'FF'
if

LOOP

LNA SNA
AIB

DCO
DC1
H'FF'
if

Branch to Loop

A =
1

Skip next instruction

is

not

equal to

JMP

LOOP

Branch Logic

Skip Logic

7-27

What

are the conditions on

which

we will

branch?

We will

choose

the following eight branch conditions:

BRANCH ON WHAT
CONDITIONS?

Branch on Zero
Branch on Zero

(Z) (Z)

equals equals equals equals

1 1

Branch on Carry Branch on Carry

(C)

(C)

Branch on Overflow (O) equals Branch on Overflow (0) equals Branch on Sign Branch on Sign
(S) (S)
1

equals

equals

Branch on Condition instructions will be followed by single-byte displacements, which means that a forward or reverse displacement of +127 or -128 bytes is possible. This is reasonable since 90% or more of all branches will be served by this range, so to provide twobyte displacements would be wasteful of memory. Of course, you can always generate a longer
range branch by combining an Unconditional
follows:

Jump

with a Branch on Condition instruction as

Branch on Z

Displacement to THERE. Out of range!

Substitute:

Branch to HERE on Z

JMP
HERE
The JMP memory.

THERE

Next instruction
instruction
is

followed by a two-byte address, so

it

can continue execution anywhere

in

The Branch and Jump

Condition instruction.

instruction

sequence

illustrated

above has the same

logic as a Skip

on

We

will

use the following eight object codes

6 5 4 3 2
1

for

our eight Branch on Condition instructions:

Bit

No.

X X X
.000 Branch on Z 001 Branch on Z 010 Branch on C
011 100
101

110
1 1
1

= = = Branch on C = Branch on O = Branch on O = Branch on S = Branch on S =

.Branch on Condition instruction

Branch on Condition instructions

will

have the format:

OP
LABEL
is

LABEL
if

the label of the instruction to be executed

the condition specified by

OP

is

met.

7-28

The Assembler
the Assembler

will

convert
1

LABEL

into a

displacement by subtracting the current Program

Counter contents from the

will print

6-bit address value assigned to

LABEL;

if

the result

is

out of range,

an error message.

OP

will

be a mnemonic as follows:
BZ
Branch on Zero
(Z

=
(Z

BNZ
BC

Branch on No Zero

= 0)
1

Branch on Carry (C

BNC

Branch on No Carry (C =0)

BO BNO
BP

Branch on Overflow (0
Branch on No Overflow

1)

(0=0)

Branch on Positive

(S

BN

Branch on Negative

(S

= 0) =

The Compare

instruction causes novice programmers a great deal of confusion. "Branch on zero" and "Branch on carry" are not nearly as meaningful as "Branch if greater" or "Branch if
less."
Recall that the

BRANCH ON LESS, EQUAL OR GREATER

of the specified

Compare

instruction subtracts

an operand from the contents

Ac-

cumulator, and sets status flags based on the result of the subtraction. The following conditions

can therefore be

identified:

Branch on Accumulator less than or equal

Branch on Accumulator
less than

(BLE).
(BL).

operand

Branch on Accumulator and operand equal

(BE).

Branch on Accumulator and operand not equal (BNE). Branch on Accumulator greater than operand
(BG).

Branch on Accumulator greater than or equal (BGE).

Depending on whether the Accumulator contents is being interpreted as signed or unsigned binary data, the qualitative conditional branches can be determined by using the following Boolean logic:
Branch
Condition
BLE
BL BE
Z

Boolean Condition

Signed Data

Unsigned Data
1

OR
S

XOR 0) = = XOR Z =
(S
1
1

C =

OR Z =
C =
Z

BNE

Z Z

=0
C =

Z =
1

BG
BGE
In

OR
S

(S XOR 0) = XOR 0=0

OR Z =
1

C =

the table above, for unsigned data,

some
case,

microprocessors invert the Carry status following a

subtract or
In

compare

operation.

In that

you must exchange C =

and C =

0.

look at

order to illustrate the use of Branch on Condition instructions, we will take another how the shower temperature controller might read data being input by the

thermometer.

When

this bit is 1, of I/O Port 2. tests bit the thermometer is ready to output a byte of .data, thermometer logic assumes that any previous data it sent has been read and processed; therefore thermometer logic transmits a byte of data to I/O Port and signals this event by setting bit of
it

If

7-29

I/O Port 2 to
Port

1.

Thermometer

logic will also reset bit

of I/O Port 2 to 0, since the data at I/O

has not yet been read:

Data

in

I/O Port 2
|_
I | |

{>has been read

liloM-

V
read as

__ ^
is

I/O Port

I/O PortO

Data

ready to transmit

to I/O Port
bit
1 1

'Test
It

of I/O Port 2

is

so reset to
to
1

Set

bit

and output data

I/O PortO

I/O Port 2 has not been read

Data

in

I/O Port

There

is

new

data

in

I/O Port

In

order to read data input by the thermometer, the microcomputer program must keep testing
of I/O Port 2 until this bit
is
1
.

bit

Then the microcomputer must read the data in I/O Port 0; but at the same time the microcomputer must reset bit of I/O Port 2 to since, as soon as data is read out of I/O Port 0, becomes old data. The program must now set bit of I/O Port 2 to 1; this tells thermometer logic that the data in I/O Port has been read.
it
1

The following instruction sequence performs the operations described above; in addition, this instruction sequence assumes that the data byte read out of I/O Port will be stored in a memory location addressed by Data Counter DCO. Auto increment addressing is used with DCO so that
this

Data Counter automatically addresses the next free byte of the input data buffer, ready for the

next access of I/O Port 0.

LOOP

INS

Input status

NIA

H'OV

Clear

all

bar

bit
if

BZ
INS

LOOP
2
H'FE'

Return to

LOOP
is

bit is

New
Set

data
bit
1

ready. Input status again.

to
1

NIA

Reset
bit

OIA

H'02' 2

to

OUTS
INS

Restore the

new

status to I/O Port 2

Input the data byte

SNA

DCO

Store

in

memory

using implied, auto increment addressing

A number of microcomputers have Jump-to-Subroutine instructions akin to the Branch on Condition instructions we have just
described. Our microcomputer has one Jump-to-Subroutine which was described as an Immediate instruction.
instruction

JUMP TO
SUBROUTINE ON CONDITION

Conditional Jump-to-Subroutine instructions will usually be followed by a two-byte address,

since subroutines
structions.

may
if

well reside

in

The

logic of Conditional

memory a long way away from the Jump-to-Subroutine inJump-to-Subroutine instructions is otherwise similar to the
is

Branch on Condition:
next instruction
is

the specified condition

met. the Jump-to-Subroutine occurs;

if

not, the

executed.

Many minicomputers also have a set of Conditional Return-fromSubroutine instructions. These instructions restore to the Program Counter the address which the Jump-to-Subroutine instruction saved. have no

CONDITIONAL

We

RETURN FROM SUBROUTINE

special Return-from-Subroutine instruction;

we

will

use a Pop instruction

instead (described along with the Stack instructions).

7-30

REGISTER-REGISTER

MOVE INSTRUCTIONS
There are two types of instructions that reference two CPU registers: instructions that move data from one register to another, and instructions that perform secondary memory reference type operations, but entirely within the CPU.
Register-to-register data

movement

instructions can be quite

REGISTER TO REGISTER

limited in our microcomputer, given its register organization.

MOVE
INSTRUCTIONS
JUSTIFIED

We

must be able

to

move

data between
is

AO and

A1. Exchanging the con-

tents of the Accumulators

also frequently useful.

to the

Moving data from the Accumulators

addresses
in

Data Counters allows program logic to create variable

these addresses to a Data Counter, for variable im-

the Accumulators, then

move

plied addressing.

Moving data
in

in

the reverse direction allows a Data Counter to be used as tem-

porary storage for data

the Accumulators; of course, this

assumes

that the Data

Counter

in

question

is

not being used for implied addressing.

There

is

rarely

any need
ability to

However, the

to move data from one Data Counter to another. move data between the Stack Pointer and Data

MULTIPLE

STACKS

Counters, or between the Stack Pointer and Accumulators is useful, since this allows a program to have more than one Stack. DC2 could be used as a buffer for the Stack
Pointer, for

example; now, by exchanging the contents of

DC2 and

SP,

two Stacks could be

ac-

cessed.

Moving data between the Accumulators and the Program Counter allows program logic to compute jump addresses. This is very useful in branch tables, which are illustrated later in this chapter.

COMPUTED JUMP

We

will therefore
7

provide Data

Move and Data Exchange

No.

instructions as follows:

6 5 4 3 2
1

10

Bit

.000 X 001 X

=A0

010 X
011 X 100 X
101

=A =A
=A0

=A

X =SP 110 X =SP X = SP

1 1

Y =A1 Y =DC0 Y =DC1 Y =DC2 Y =PC Y =DC0 Y =DC1 Y = DC2 X

to

_00 Move
01
11

contents of

Move

contents of Y to X

10 Exchange contents of

Y and X
instruction
of the
is

Not Used

.A
In

register-to-register

Move

specified

the description above,

X =A

specifies a 16-bit value

formed out

two Accumulators as

follows:
7

A0
6 5 4 3
2
1

A1
7

15 14 13 12 11 10 9

7-31

This instruction:

MOVE
MOV
S.D

Will

move the

register contents specified

by S
1

to the register specified by D. S and D

must be one of the eight valid pairs shown; therefore, these

Moves

are legal:

MOV MOV MOV

This

A AO AO. A
1
.

Move A
Move

AO Move AO contents to A
contents to
Stack Pointer contents to

SP.DC 1

DC

Move

is

illegal:

MOV

DC1.DC0
two
legal

but the intended operation could be achieved via these

Moves:

MOV MOV
Recall the switch

DC1.A

Move DC

contents to Accumulators
to

A.DCO
test

Move Accumulators
it

DCO
Move
instruction as follows:

change

program:

used a register-to-register

IN

Input

new AO

switch settings

XRA

SWITCH
A0.A1

Identify

changed switches
contents
in

MOV
ANA

Save

A1
on

SWITCH

Identify switches that turned

Exchange instruction mnemonics

will be:

EXCHANGE
S.D

X
The same
rules apply to

S and

as described for

MOV.

REGISTER-REGISTER

OPERATE INSTRUCTIONS
tions,

Because our microcomputer has a number of secondary memory reference instrucseven it needs very few Register-Register Operate instructions; the following instructions, which parallel the secondary memory reference instructions, will do:
7

5 4 3 2
1 1 1

10

.000 Add binary 001 Add decimal

010
011 100
101

Subtract decimal

AND
OR
Exclusive -OR

110 Compare
111

Not Used

Register-Register Operate instruction

7-32

The four status

Because there
result.

flags are set or reset to reflect the results of the operation.

is

an

A0-A1 Exchange

instruction,
is

Register-Register Operate instructions,

where AO
will

we have only one set of always the destination of the

The Register-Register Operate instructions these mnemonics:

AB
Add
A-1 to

use

AO

binary

ADD BINARY ADD DECIMAL

SUBTRACT DECIMAL

AD
SD

Add A1

to

AO

decimal

Subtract A1 from

AO

decimal

AND
OR
EXCLUSIVE OR

AND
OR

XOR

AND A1 with AO OR A1 with AO XOR A 1. with AO

Compare A1 with AO
Operate instructions have operands.

COMPARE

CMP
None

of the Register-Register

These three
struction:

instructions will allow

A1

to

be the destination

-of

any Register-Register Operate

in

A0.A1

Exchange AO and Al contents

AB
X
A0.A1

Add

binary; the result

is

in

AO

Exchange AO and A1 contents

Register-Register Operate instructions are convenient to have, but not vital, since they do nothing that could not be done using Load, Store and secondary memory reference instructions.
Register-Register Operate instructions
will

REGISTERREGISTER

execute faster than equivalent

since

OPERATE INSTRUCTIONS
JUSTIFICATION
and
that takes time.

secondary

memory

reference

instructions,

secondary

reference instructions require one data byte to be fetched from

memory memory -

There is one further set of Register-Register Operate instrucACCUMULATOR tions which will prove very useful; we will allow the contents of DATA COUNTER Accumulator AO to be added, as a signed binary number, to any ADDITION one of the Data Counters. This allows a data address displacement to be computed, then added to (or subtracted from) a Data Counter.
This instruction
is

particularly useful in matrix arithmetic,

where doubly

subscripted parameters such as

ADDRESSING MATRICES

VAL

(X.Y)

may be used. If the dimension of Y is known, each increment of X may be handled by adding the dimension of Y to the Data Counter which is addressing VAL. This is illustrated as follows:

7-33

VAL
Data Table

VAL(I.I)

VAL (1.2)

VAL (1.3)
VAL (1.4)
1

VAL (1.25) VAL (2.1) VAL (2,2)

VAL (2.3)
1

VAL (2.25) VAL (3.1)

VAL (3.2) VAL (3.3)

To extend this type of matrix handling, we will also allow unit, to be added to any Data Counter.

AOand

A1. treated as a 16-bit

We now

have these instruction codes:

7 6 5 4 3 2

10

Bit

No.

11

'"X

.00 DC0
01 DC1
10
1

is is is

destination

destination

DC2
SP

destination
destination

is

_0
1

Add A0 Add A
to

.Add

Address

register instruction specified

specifies the 16-bit unit:

A0
7

A1
3
2

10
8

10

Bit

No. (8

bits)

15 14 13 12 11 10 9

10

Bit

No. (16

bits)

We will

use these mnemonics:

DAD
S
is

S.D

the source, and

may be A0

or A;

no other options are allowed.

or SP;

is

the destination, and

may be DC0. DC1. DC2

no other options are allowed.

7-34

The Accumulator-Data Counter Addition instruction

useful for creating branch tables.

is

also

BRANCH
TABLES
one
of

branch table

is

list

of addresses, identifying a
logic.

number

of programs, just

which must be

executed, based on current program

First

we

will

create a table of program starting addresses; because this

it

is

not a simple concept,

we

will illustrate

with an example that uses

real,

but arbitrary numbers:

Start of
Start of Start of

ADDR1

EQU

H'1247'

Program

ADDR2 ADDR3

EQU EQU
etc.

H'183C

Program

K28CA'
H'0800'

Program 3

ORG
BTBL

DA DA DA
etc.

ADDR1

ADDR2 ADDR3

The EQU mnemonic, recall, is an Assembler directive; it tells the Assembler what values to assign to the symbols ADDR1, ADDR2, ADDR3, etc. The DA mnemonic is a "Define Address" Assembler directive; tells the Assembler to place the 16-bit value provided by the operand in the next two currently identified memory locations.
it

EQUATE
DIRECTIVE
DEFINE

ADDRESS
DIRECTIVE
ORIGIN DIRECTIVE

The

ORG mnemonic
address.
in
;

is

an Assembler directive which provides the current

case,
it

memory
0800 16
six

In this

defines the current

the

memory address
in

as

terms of

memory map,
.

above

instructions result

these

data bytes:

Memory
Address

Memory

07FF

BTBL

n ^ OoOO
~
~

12

ADDR1

0801

47
18

0802
0803

ADDR2 ADDR3

3C
28

0804
0805 0806
The
label

CA

BTBL, note, becomes a symbol with the value

is in

suppose a program number the program number as follows:

LIM

Now

Accumulator A0;

we

can execute the program identified by

DC0.BTBL

Load the beginning address

for

program addresses

into

DC0

DAD DAD
LNA

AODC0
A0.DC0

Add

the table

number

twice,

since each address occupies

two bytes

DC0 DC0
A,PC

Load the address

identified

by

DCO

LMB

MOV

Move

this

address to PC

7-35

Look
1)

at

what happens:
instruction loads

The LIM

0800, 6

into
2:

DCO.
the

2)

Suppose Accumulator A0 contains contains 0804, 6

.

two

DAD

instructions

add 4 to DCO. which now

3)

The LNA
DCO.

instruction loads the contents of

memory

location
.

0804, 6

into

A0. then increments

Now A0
LMB
CA, 6

contains 28, 6 and

DCO

contains 0805, 6

4)

The
tains

instruction loads the contents of

.

memory

location

0805, 6

into

A1.

Now A1

con-

5)

The

MOV

instruction

memory

location

moves the 28C A, 6

.

value

28CA, 6

into the

Program Counter, forcing a jump

to

When would you

tions.

use a branch table? One example

is

given

in

the description of interrupt instruc-

REGISTER OPERATE INSTRUCTIONS

Register Operate instructions modify the contents of a single register; no other register's contents are modified in any way.

Some Register Operate instructions are absolutely necessary, whereas others are nothing more than conveniences. We will therefore identify the ways in which a register's contents may be modified, and determine whether the operation is necessary, or just a convenience.

to increment and decrement registers' contents is universal; whenever a register contains a counter or index, there is the probability that it will have to be incremented or decremented. To some extent, the auto increment and auto decrement variations of implied addressing makes the need to increment and decrement the Data Counters

The need

INCREMENT

AND DECREMENT
less
vital; still

useful capability, since

it

allows addresses to be incremented or decremented selectively

it

is

not

always.

Since we have no binary subtract instructions, it is vital that j COMPLEMENT | there be an instruction to complement at least one of the Accumulators. Complementing the Data Counters serves no useful purpose. See Chapter 2 for a discussion of twos complement subtraction.
It

must be possible to zero each Accumulator;

is

this

is

a frequent prestep.

CLEAR
REGISTER

requisite before performing addition, or simply as

an

initialization

Zeroing the Address Registers

not necessary, since they have data

loaded into them as the most frequent operation.

Shift- and rotate operations are very important for two reasons: they are vital to most multiplication and division algorithms, and they are frequently used' in counting operations.

SHIFT AND

ROTATE
SHIFT

shift

operation

is linear:

o.o.o.o
KJ

lost-*-

in

KJ >u
will
lost.

Thus a simple
order
will
bit

shift left,
bit

as illustrated above,
left, will

having no

to.the

be

move each bit to the next bit to the left; the high There being no bit to the right of the low order bit,

be moved

into the

low order

bit.

7-36

rotate operation

is

circular;

assumed

adjacent:

A
and

the high and low order bits

i^

AA

would be

ROTATE

(J~
Numerous
variations of shift
shift or rotate left:

<b KJ KJ
rotate operations are possible;

J
you can

SIMPLE SHIFT

AND ROTATE

c
Simple Rotate Left

^3
Simple
Shift Left

You can

rotate or shift right:

Simple Rotate Right

D
Simple
2.

Shift Right

A
A

right rotate (or shift)

2,

is

equivalent to dividing by

while the

left

rotate (or shift)

is

equivalent to
itself.

multiplying by

and can be reproduced by adding the contents

status, in

of a register to

shift or rotate

shift

and

rotate

may occur through the Carry become identical operations:

which case the

SHIFT

AND

ROTATE

THROUGH CARRY
high order
bit

old value of Carry

to

becomes new
value of Carry

low order

bit

left

shift/rotate through Carry

is

illustrated

above; the equivalent

right shift

through Carry

is

self

evident.

Another

variation

branches a

bit into

the Carry status, but excludes the old

SHIFT

AND

Carry status from the shift or rotate:

ROTATE WITH BRANCH

CARRY

The
shift

=FFF =f
7TRotate with Branch Carry
with branch-carry
is

Shift

With Branch Carry

very useful as the

first in

a multibyte shift operation,

where an

initial

value of

must be assumed

for the Carry status.

bit

The

shift

may

also

be arithmetic and propagate the high order

7

(sign

bit)

ARITHMETIC
SHIFT

to the right:

6 5 4 3 2

10

Bit

No.

^unchanged

>

7-37

An

arithmetic shift

left will

maintain the sign

bit,

and shin out

of the penultimate bit into the Carry:

6 5 4 3 2

10

Bit

No.

unchanged

i
data.

w
in

four-bit shift, left or right,

is

very useful

microcomputer

applictions,

SHIFTING

which frequently process numeric

As was discussed
four
bits;

in Chapter 2. binary-coded decimal digits each occupy each byte holds two BCD digits. A four-bit shift is therefore equivalent
is,
it

BINARY CODED DECIMAL DATA

__

to a single

decimal

digit shift, left or right: that

left

is

equivalent to multiplying or dividing by ten.

The

four-bit

and

right shift also

makes

it

the ASCII representation of a decimal digit

easy to pack and unpack ASCII characters. Recall that appears as follows:

2 3

4
5 6
7

8
9

= = = = = = = = = =

00110000
00110001

00110010
00110011

00110100
00110101

00110110
00110111

00111000
00111001
port

Suppose a string of ASCII digits are being read through an I/O format, two digits per byte as follows:
Data as read:

and must be packed

in

BCD

0011 0010

0011 0110

0011

1000

0011 0101

Data as packed:

0010 0110

1000 0101

The

four-bit shift

is

a natural for this operation;

we

will settle

on some

shift

mnemonics, then

write a program to perform this

BCD

packing operation.

How
Shift

many, and which shift/rotate instructions should

we

have?
in

and rotate instructions are usually inadequately rpresented

microcomputer

instruction sets.

We

will

provide shifts and rotates,

Shifting Data
is

have such instructions for the two Accumulators only, but without Carry (simple), with Carry, and with branched Carry.
it

we

will

a luxury
will

we

Counter contents would not be very useful; will have to forego.

would provide

a 16-bit shift, but that

We
In

include

two

versions of the four-bit

left

of either

Accumulator A0 or A1; the other

will

and right shift. One will operate on the contents operate on the combined unit as a 16-bit number.
Accumulator
will

each case, since

we

are dealing with four-bit units the

be ignored during the

shift operation.

We can

now summarize

the Register Operate instruction object codes as follows.

7-38

For the operations which are confined to the Accumulators, these are the instructions and their object codes:
7
1

6 5 4 3 2
1

10

Bit

No.

A
.

0000
0001
001

Simple, shift right

Simple

shift left

0010 Simple
0100
0101

rotate right
left

Simple rotate
Shift right

through Carry

Shift left

through Carry
with branch Carry with branch Carry

0110
0111 1000
1001

Shift right

Shift left

Shift right arithmetic

Shift left arithmetic

1010 Clear

register

1011 Complement register

Operate on
1

AO

contents contents

Operate on

Register Operate instruction

The

shift

and

rotate instructions
status.

may modify

the Carry status.

The Complement

instruction will

affect the

Zero

No

other status flags will be changed.

The two
ject

codes

4-bit shift instructions can operate on AO, A1, for these instructions will be as follows:

A(A0

Al 16-bit unit). Ob-

W
Address
registers;

6 5 4 3 2

Bit

No.

.1

1101

100 Operate on AO contents Operate on A1 contents

1110 Operate on

contents

Shift left four bits

1

Shift right four bits

.Register Operate instruction

and on the The Increment and Decrement instructions operate on the Accumulators
they
will

use these object codes:

Bit

6 5 4 3 2
1.1

10

No.

000 Operate on AO
001
01

Operate on

010 Operate on A
Operate on DCO 100 Operate on DC1 101 Operate on DC2
Increment register contents Decrement register contents

.Register Increment or Decrement instruction

7-39

The Shift and Rotate instructions without operands:

will

have these mnemonics,

SHIFT

AND

ROTATE
INSTRUCTIONS

SHRA SHRB SHLA

SHLB

RORA RORB ROLA ROLB SRCA SRCB SLCA

SLCB SRBA SRBB SLBA
SLBB

SRAA
SRAB SLAA
SLAB SR4A SR4B SL4A
SL4B SR4 SL4

CONTENTS RIGHT SIMPLE CONTENTS RIGHT SIMPLE CONTENTS LEFT SIMPLE SHIFT A1 CONTENTS LEFT SIMPLE ROTATE AO RIGHT SIMPLE ROTATE A RIGHT SIMPLE ROTATE AO LEFT SIMPLE ROTATE A1 LEFT SIMPLE SHIFT AO RIGHT THROUGH CARRY SHIFT Al RIGHT THROUGH CARRY SHIFT AO LEFT THROUGH CARRY SHIFT A1 LEFT THROUGH CARRY SHIFT AO RIGHT WITH BRANCH CARRY SHIFT Al RIGHT WITH BRANCH CARRY SHIFT AO LEFT WITH BRANCH CARRY SHIFT A1 LEFT WITH BRANCH CARRY SHIFT AO RIGHT ARITHMETIC
Al
1

SHIFT AO SHIFT A1 SHIFT AO

SHIFT A1 RIGHT ARITHMETIC SHIFT.AO LEFT ARITHMETIC SHIFT A LEFT ARITHMETIC SHIFT AO RIGHT FOUR BITS SHIFT A1 RIGHT FOUR BITS SHIFT AO LEFT FOUR BITS SHIFT A1 LEFT FOUR BITS SHIFT AO AND A1 RIGHT FOUR BITS SHIFT AO AND A LEFT FOUR BITS
1 1

These are the mnemonics

structions:

we

will

use for Register Operate

in-

INCREMENT
REGISTER

INC

This specifies the "Increment Register' instruction; R

may be

AO. A1. A. DCO. DC1 or

DC2

The "Decrement Register" mnemonic, as follows:

instruction will differ only in the

DECREMENT
REGISTER

DEC

Complement and
and
will

Clear will apply to the

two Accumulators

have these mnemonics:

only,

I
'

COMPLEMENT vmrixmtnt
CLEAR
|

CLA
CLB

Clear

AO

Clear

COA
COB
These four
instructions

Complement AO Complement Al

have no operand.

7-40

We will
ples of

now illustrate the value of Register Operate how these instructions may be used.
shifts;

instructions with

some exam-

Consider multibyte

they allow multibyte numbers to be multiplied

will

SHIFT

and divided.
status,
ple,

rotate

through Carry

propagate a

shift

down

number

MULTIBYTE
sim-

of bytes, since the high order bit of

each byte propagates

the next byte. This

into the Carry

illustrated for the following

then into the low order

left shift:

bit of

may be

three-byte

start

lohhlohlohhl |ilohhlohloifl lohlonnioMlo

C
Stepl:

assumed
l

initial

status

|0[1|1|0|1|Q|1|11 /Il|0|lill0llf

0r\ l^

>

Step

2:

J0I1I1I0I1I0I1TTI |0IH1|Q|1|0|1|0|

ll

Ml MIOlHOlol

Step

3:

I1I1I0I1I0I1I1I1I

loiil 1I0I 1I0I1I0I

I1I0I1I1I0I1I0I0I

The program

to

perform

this

operation

is

as follows:

LIM

DCO.

Load the buffer

starting

address

in

DCO

LMA
SDA

DCO
DCO DCO DCO DCO DCO

Load low order byte

Shift left with

into

AO

via

DCO

branch carry

Store the result back; decrement

DCO

LMA
SLCA

Load the second byte

Shift left with carry

into

ACO
DCO

SDA

Store result back; decrement

LMA
SLCA

Load

last

byte

Shift left with carry

SMA
The LIM

Store result back

instruction simply loads the

address of the

last

byte into Data Counter DCO.

7-41

step 1. First. LMA loads the low but does not modify the address in DCO, since we will want to same address. The SLBA instruction is very useful at this point because it performs a branch carry; we do not know what the Carry status is before enterinq this routine, but with the SLBA instruction we do not care; this instruction loads into the low order VeS the high rder bit f A0 Int0 the Carr sta ready to be^hrfted into the V ?k next byte. Tu SDA mstructioa stores the The shifted contents of AO back into the memory byte from which the unshrfted source came; then the address in DCO is decremented to point to the second byte

The next three

instructions.

LMA. SLBA and SDA accomplish

order byte .nto Accumulator

AO

return the shifted result to the

'T

^.

The next three instructions. LMA. SLCA and SDA perform step 2. These three instructions differ from the previous three instructions only in that a shift left with carry must now be performed since the Carry status represents the high order bit of the previous byte, which must become the low order bit of the current byte.
Step 3
is

ts dress

differ
in

accomplished via the last three instructions. LMA. SLCA and SMA; these three instrucfrom the three step 2 instructions only in that we do not bother to decrement the adDCO. since there are no more bytes to be shifted.

Observe that since only three bytes are to be shifted, we do not use an instruction loop The whole of the program above only occupies 12 bytes, three for the Load Immediate into DCO instruction, one each for the remaining instructions. We could condense the three steps into one set of three repeated instructions so long as we can change the SLBA to a SLCA instruction and so long as the final SMA instruction becomes an SDA instruction. The program now appears
as

Clear Carry status

which must

initially

be

!^ LIM
,

??' BUFA A1.3

LOOP

LMA
SLCA

DCO
DCO
A1

Load buffer startin 9 addres s m DCO Load byte count into A1 Load next byte into AO, via DCO
Shift left

with Carry

SDA
DEC BNZ

Store the result back; decrement

DCO

LOOP

Decrement byte count Return not end

if

a program with e.ght instructions versus the previous ten. But these eight instruc going to occupy 12 bytes; three for the Load Immediate into DCO. two ach or the Load Immediate into A1 and the Branch on Non-Zero, and one each for the emamder

We now -have
ions are
st,H

t structure offers

IrXs1 economies Wh6n 00P few compared

f3Ct th9t

Thi

is

'

haS VerV f6W

to a

as

t-nch-and-loop P ro ram once-through program structure.

3
-

lterat ' nS

we described reference instructions could be tested for "on" or "off" status in a program loop as follows:
when justifying secondary memory
1)

Next consider switch testing. The eight switches

SWITCH
TESTING

s^edTfr^h left with

shifted

T ^
A
k" branch carry
into

3re 9 ,ng t0 USe until a 1 appears

A1
in

eight shifts have

2)
3)

been performed.
AO.

aS 3 SW tCh COunter * contents will be the Carry status, which will indicate 'nuicaie that mat
'

Load switch settings

Shift

AO one

bit right in

with branch carry. The low order

still

bit

of

AO

is

now
bit

in

the Carry status

since a

4)

Save

AO and A1

DC2. The Carry status

reflects the

low order

of

instruction will not affect the status flags.

5>

AO

Move

program

"

"^ **"

"^

n " Program
"

therWISe

COntinue Wlth

"

sw *ch off

7-42

6)

When
Shift

the "switch on" or "switch off" program has completed execution, reload

AO and A1

from DC2.
7)

A1

left

one

bit

with branch carry.

If

Carry

is

set,

we

are done.

If

Carry

is

not set return to

step 3 above.

The program steps

required to implement the

above

logic are as follows:

LIM
IN

A1.1
4

Load 01

into

A1

Input switch settings from I/O port 4

Shift

LOOP

SRBA

AO

right

with branch carry

in

MOV
BC

A.DC2

Save AO and A1

DC2

SWON

Branch on C = 1 to "switch on" program

"Switch off" program logic appears here.

MOV
SLBB

DC2.A

Restore
Shift

AO and A1
left

from

DC2

with branch carry

Now

consider the program steps needed to pack the numeric

PACKING
ASCII DIGITS

bits (low order four bits) of ASCII numeric digit representations; two numeric digits will be packed per byte, as described directly before
shift

object codes

illustration.

These steps would be required

Step
1

to

pack

digits:
in

Step 2

Step 3

move
read

in

one ASCII
four
bits.

digit

and store

Accumulator AO.

shift left

the contents of

AO

to

A1. A1
ASCII

now
digit:

contains the high order digit as follows:

00

XXXX

After four

bit shift left:

XXXX0000

Step 4
Step 5

mask out
follows:

Input the next ASCII digit to Accumulator AO.

the high order four bits of AO.

AO now
digit:
bits:

contains the low order digit as

ASCII
After masking high order

0011YYYY 0000YYYY
as follows:

Step 6

Add A1
store the

to AO.

AO now contains the high and low order digits 0000YYYY + XXXX0000 = XXXXYYYY
digits in

Step

two packed

memory (we
two ASCII

will

assume the

correct buffer

is

addressed

byDCD.
Step

8
will

return to step

for the next

digits.

We

assume

that ASCII digits are input at I/O Port

5,

and

bit

of

I/O Port 6
5.

is

set to

by the

inputting device

whenever

it

has transmitted an ASCII

digit to

I/O Port

7-43

Program steps are as follows:

LOOP1

IN

Input status
Shift bit

SRBA
BNC
LOOP1
6

of
is

AO

with branch carry

If

Carry Carry

0.
1,

input status again

OUT
IN

If

is

output

AO

to I/O Port 6

This clears the status

Input the next ASCII digit
Shift left

SL4A

bits

MOV
LOOP2
IN

A0.A1

Save

in

A1
first

Repeat

five instructions

SRBA

to input next ASCII digit

BNC

LOOP2
6 5
H'OF'
.

OUT
IN

NIA

Mask out

high order four bits

AB LDA JMP

Add A1

to

AO
digits

DCO
LOOP1

Store the

two packed

Return for next two digits

STACK INSTRUCTIONS
Since our microcomputer has a Stack, it must have Push instructions to move registers' contents onto the Stack; it must also have Pop instructions to move data off the Stack, and into registers.
the Jump-to-Subroutine init pushes the Program Counter contents onto the Stack before loading a new address into the Program Counter.
list

Many microcomputer manuals

struction as a Stack instruction, since

JUMP-TO SUBROUTINE

Push instructions will be used primarily for interrupt processing; programming examples are given along with interrupt
handling
instructions.

I
'

PUSH

I
'

Pop instructions are used in interrupt processing, and in order to return from a subroutine; examples of the latter use are
given
shortly.

POP
RETURIM-FROMSUBROUTIIME

Push and Pop instructions are sometimes used to pass data (parameters) to subroutines; we will illustrate this use of Push and Pop instructions later.

SUBROUTINE

PARAMETER
PASSING

Our microcomputer

will have Push and Pop instructions that reference the two Accumulators, and the four Address registers; object codes will be as follows:

6 5 4 3 2

Bit

No.

nun
t

in
k

000 AO selected
001
01

selected

010 DCO selected

DC

selected

100 DC2 selected

101 SP selected

110 PC selected

Push
1

Pop

Stark instruction Rf

The Push and Pop

instructions will use this instruction format:

OP
OP
R
represents the instruction mnemonic;
it

R
be

will

PUSH

or POP, for a

Push

or

Pop

instruction,

respectively.
will

specify the register

data

popped from the

Stack. R

whose contents is to be pushed onto the Stack, or which is to receive may be A0, A1, DCO, DC1, DC2 or PC. No oth er symbol is allowed

We will allow an additional instruction mnemonic for subroutine

returns.

RETURN
INSTRUCTION

The

instruction:

POP
will

PC

move

the

two bytes

at the

top of the Stack into the Program Counter, thus effecting a return

from the subroutine. The mnemonic:

RET
will

mnemonic

perform the same operation, and generate the same object code; will generate the one object code byte:
7
1

in

other words, the

RET

6 5 4 3 2
1

10
1

As an example of Stack instructions' use. return to the data movement subroutine which was described along with Immediate instructions; the subroutine was listed like
this:

MOVE
LOOP

LIM

DC0.BUFA
DC1.BUFB

Load source

initial

address

LIM

Load destination

initial

address

LNA
SSA

DCO

Move

data from source

DC 1, LOOP

to destination

Return from Subroutine

7-45

addition to adding a Return instruction, this subroutine can be made useful if the beginning addresses for the source and destination buffers (BUFA and BUFB) are variable. Stack instructions provide one way (but not the best way) of making this possible.
In

more

PARAMETER
PASSING

Before calling subroutine

MOVE,

a program can push

its

BUFB onto

version of the addresses

BUFA and

the Stack, as follows:

LIM

DCO.BUFX

PUSH
LIM

DCO
DCO.BUFY

PUSH
JSP,
'

DCO

MOVE

The top

of the Stack

now

looks

like this:

Stack

Stack Pointer points here

Return address,
i.e..

address of

instruction following

JSR

Address BUFY

Address BUFX
I

Previous Stack contents

Subroutine

MOVE

must be modified as

follows:

MOVE
-

POP POP POP

DC2
DC1

Save the return address

in

DC2
initial

Load BUFY as destination

address

DCO
DC2 DCO DC 1, LOOP

Load BUFX as source

initial

address

LOOP

PUSH LNA
SSA
RET

Replace return address

at

top of stack

Move
Pop

data from source

to destination

return address from stack

PARAMETER PASSING INSTRUCTIONS

Because subroutines are so frequently used, which make subroutines easier to use.
Let us return again to the data
In
it is

worth taking a look

at instructions

move

subroutine which

we

have been developing up to

this po.nt.

data from a source buffer with a dedicated address, to a destination buffer with another dedicated address.
Next,

the

first

place, this subroutine simply

moved

when

describing the Push and

Pop

instructions

we

improved on the

subroutine by allowing the calling program to specify the PARAMETERS source and destination buffer beginning addresses. These two addresses are called "parameters", which the calling program passes to the subroutine. Parameter passing is a very important feature of subroutine handling; by making parameter passing easy a microcomputer becomes a significantly more powerful device.

versatility of this

SUBROUTINE

7-46

Parameter passing instructions are, in fact, quite simple to specify. What we will do is to allow parameters to follow the Jump-to-Subroutine instruction, then we will provide the microcombecome the puter with a form of indirect addressing, where the two bytes at the top of the Stack

memory address from which

data

will

be fetched.

But before we explain this concept with pictures and examples, let us define the parameter passing instructions which our microcomputer will include.
First,

there are the object codes that are to be used:

7

6 5 4 3 2

10
I

Bit

No.

ololol

01

Pass parameters to
to

A0
A1

.100 Pass parameters

101
1 1

Pass parameters to

Pass parameters to
Pass parameters to

DC0 DC DC2
1

Parameter passing instructions specified

The

instruction format for the Pass Parameter instruction will be

as follows:

PASS PARAMETER
INSTRUCTION

SPP
SPP

is

the instruction mnemonic, and R identifies one of the registers A0, A1, DC0.
is

DC1

or

DC2

no other symbol

allowed for

R.

We will now develop a very efficient implementation of the data

moving subroutine.
The subroutine
will

PASSING

PARAMETERS TO
SUBROUTINES

be called as follows:

JSR

MOVE
BUFX BUFY

Call

data

move

subroutine

DA DA

Specify beginning source address

Specify beginning destination address

Recall that the

DA mnemonic
in

represents the Define Address Assembler directive. Suppose these

instructions reside

memory

as follows:

Program

Memory
-

04C0
PC.

^04C1
04C2 04C3 04C4 04C5 04C6
04C7
0478

10111101
20

tl^

\ Move subroutine execution address

80 08
> BUFX

00 08
>

BUFY

40

7-47

After the

JSR

instruction

has executed, PC

will

contain 2080, 6 which

.

is

subroutine

MOVE. The

previous value of PC.

04C4 16

will

be

at the

the execution address for top of the Stack:

Stack

SP 04

C4

The

MOVE

subroutine appears as follows:

MOVE
LOOP

SPP
SPP

DCO
DC1

Load source

starting

address into

DCO

Load destination

starting

address jnto

DC

LNA
SSA
RET

DCO DC 1. LOOP

Move
Pop

data from source

to destination

return address from Stack

The
1)

first

SPP

instruction

causes the

CPU

to execute the following

logic:

The two bytes

at the

top of the Stack are fetched into the CPU.

2)

These two bytes are treated as

identified

by

this

address

is

then
.

contains 08, 6 Therefore, at the end of this step, the high order byte of value 08, 6 and the memory address has

a memory address. The contents of the memory location memory address are loaded into the high order byte of DCO The memory incremented. The memory address was 04C4 and memory location 04C4 16
16

DCO

contains the

been incremented

to

04C5 16

3)

Step 2 is repeated, with the data fetched from memory going to the low order byte of At the end of this step DCO contained 0800 16 and the memory address is now
,

DCO
.

'

04C6 16

4)

Instruction execution

is

complete so the memory address

,

is

which

now

holds 04C6, 6 not

returned to the top of the Stack

04C4 16

The second SPP instruction ,s a repeat of the first SPP instruction, except that DC1 is specified as the destination: therefore, at the conclusion of the SPP instruction. 0840 16 will be stored in DC1 and the top two bytes of the Stack will hold the value 04C8 16 This is the address of the next instruction to be executed following the two parameters. BUFX and BUFY. At the conclusion of the Move subroutine, the RET instruction will pop the value 04C8 16 back into the Program Counter tnus allowing normal program execution to continue.
.

INTERRUPT INSTRUCTIONS
In reality we are going to talk about more than interrupt instructions. There are only three interrupt instructions; one disables all interrupts, the second enables all interrupts, and the third is a Retum-from-lnterrupt instruction.

How

is

our microcomputer going to handle interrupts?

similarities between processing an interrupt and entering a each case, program execution temporarily branches from a mam program to a secondary logic sequence, at the conclusion of which program execution returns to the main program. The difference between a subroutine and an interrupt is that a Jump-to-Subroutine is part of the scheduled mainstream logic:

There are many

subroutine;
,n

Main Program

2\
^SubroutineX

An

interrupt on the other hand, is an unscheduled event, and the main program has no way knowing when the interrupt will occur:

of

Interrupt!

Main

Program

We

Chapter 5. the various ways in which external devices can interCPU's interrupt protocol becomes more minicomputer-like, and more sophisticated, so also the cost and complexity of the external logic needed to meet the reInquirements of CPU interrupt protocol goes up. We will therefore adopt a very simple scheme. when the CPU terrupting devices will be daisy-chained on a single interrupt request line, and sends out an acknowledge signal, the interrupting device will output a single byte of data to an
discussed at

some

length,

in

rupt the

CPU.

Recall that as the

I/O port with address FF 16 The

.

CPU

will interpret

the data

in

I/O port FF 16 as identifying the

in-

terrupting device.

As soon as the CPU acknowledges an

interrupt,

it

will automatically

do three things:

interrupt from being processed before the First, it will disable interrupts, thus preventing another must be executed by current one has been adequately handled. An Enable Interrupt instruction

the program before any further interrupts can be handled.

Next the

CPU

will

save the status

flags'

contents by pushing them onto the Stack.

of the Stack,

Finally the

CPU

will

push the Program Counter contents to the top

to continue at

and

clear the Pro-

gram Counter. This causes program execution

memory

location 0.

instruction can be executed at any time to prevent any interrupts from being acknowledged; this condition will last until the Enable Interrupt instruc-

A Disable Interrupt
tion
is

re-executed.
first

Let us

look at the object code for the Enable and Disable Interrupt instructions:
Interrupt procesing instruction specified

t
7

6 5 4 3 2

JL 10

Bit

No.

MiliMMiM
Enable interrupts
.1

Disable interrupts

7-49

The mnemonics
Dl

for

the two interrupt instructions will be:

ENABLE INTERRUPT
DISABLE INTERRUPT

for Disable Interrupts,

and

El

for

Enable Interrupts.

The Return-from-lnterrupt
First
it

instruction will

do three

things:

RETURN

will

return the status flags,

matically

when

the interrupt

which were saved on the Stack autowas acknowledged.

FROM
INTERRUPT

Then

it

will

pop the

return address from the Stack to the

Program Counter.

Finally the Return-from-lnterrupt instruction

enables interrupts.

The Return-from-lnterrupt
7

instruction's object
No.

code

will be:

6 5 4 3 2
1
1 .1 1

10
1
1

Bit

X
The
instruction
RTI

Return from interrupt

mnemonic

will be:

To

illustrate

the use of interrupt instructions,

we

will

show

the program steps which follow an

In-

terrupt

Acknowledge.

We

will also

show

the program steps which must be present at the end of the interrupt service

routine.

Following an interrupt these steps must occur:

1)

INTERRUPT

ACKNOWLEDGE Acknowledge, the CPU logic saves the status flags at the top of the Stack, pushes the Program Counter contents onto the top of the Stack, then disables interrupts. The Program Counter is zeroed, which means that program execution jumps to memory location 0.
At the time of the
Interrupt

2)

memory location 0. there is a short program #sequence which saves the contents CPU registers by pushing registers' contents onto the Stack. This is necessary, since the registers may be used in any way by the program which is about to be executed.
Starting at
all

of

3)

After
read,

all

registers'
is

and

contents have been saved on the Stack, the contents of I/O Port FF 16 is used to compute the starting address of the particular program which will service

the identified interrupting device.

7-50

4)

The program which gets executed following step 3 may

rupt instruction.
If

optionally contain

an Enable

Inter-

this instruction

is

present, another interrupt

may be

processed, before the

current interrupt has completed execution, as follows:

First Interrupt

Main Program

Second
interrupt

service routine

If

interrupts are not enabled, then

is

no further interrupts can be processed

until their

Retum-from-

Interrupt instruction

executed-.

This

is

the instruction sequence which, given our interrupt service logic, must be present begin-

ning at

memory

location 0:

ORG
PUSH
PUSH PUSH PUSH

AO
A1

Save

all

registers'

contents

on the stack

DCO
DC1

PUSH
IN

DC2
H'FF' Input device ID from I/O Port FF

LIM

DCO.BTBL

Load jump table base address

Shift

SHLA

AO

left,

simple, to multiply by 2

DAD
LNA

AO.DCO

Add AO
Load the
starting

to

DCO

DCO DCO
A,PC

interrupt service routine

LMB

address

MOV
This
is

Move

the address to PC

what the above

short program does.

Recall that the

the

ORG mnemonic specifies the Assembler. The ORG mnemonic above

code beginning
at

current
tells

memory address

for

the Assembler to start

SAVING REGISTERS

creating object

memory

location 0.

ON STACK We
in

The five Push instructions save the contents of aH registers on the Stack.
The
IN instruction will receive a device ID at

I/O Port FF.

are

taken for the

place
its

CPU

to execute the
at

Push

instruction, the interrupting device will

assuming that within the time have been able to

ID

number

I/O Port FF. This ID

number
7-51

will

be

Accumulator AO.

The instructions from LIM to MOV constitute a branch table. Branch tables BRANCH were described along with the DAD Register-Register Operate instruction. TABLE Notice in the branch table instruction sequence above that a Shift instruction has been used to multiply the contents of AO by 2 before adding to DCO; in the previous
ample, the

ex-

DAD

instruction

was executed

twice to achieve the

same end

result.

The address computed by the branch table becomes the beginning address of the interrupt service routine, which will now be executed to service the specific device which requested an interrupt. Once the interrupt service routine has completed execution, will call a subroutine that reverses the interrupt acknowledge steps as follows:
it

RINT

POP POP POP POP POP

RTI

DC2
DC1

Restore

all

registers'

contents

DCO
A1

AO

Observe that registers are popped from the Stack in the reverse order to which they were pushed, since the Stack is a last-in-first-out storage unit.

RESTORING REGISTERS

The

final

RTI instruction

will

restore the saved status (which

is

on the Stack
will

FROM STACK
acknowledge.

following the interrupt acknowledge) to the four status flags, then

load back into the Program

Counter the
If

memory address which was saved

still

at the time of the interrupt

interrupts are

disabled, the RTI instruction will re-enable interrupts.

will

Program execution

now

continue at the point where the interrupt occurred.

STATUS INSTRUCTIONS
we have four status flags. Sign (S). Carry (C), Overflow (O) and Zero (Z), it must be possible to set or reset these flags individually. The most common situation in which
Since
program logic will rquire a flag to be set is just before entering a program loop which contains a Branch on Condition instruction at the beginning of the loop. In the normal course of events, status flags will be set later in the loop to be tested when program logic comes back to the beginning of the loop. It must be possible to set status conditions before entering the loop, so that can get by the Branch on Condition on the first pass.

we

There are also many multibyte arithmetic algorithms which require the Carry and Overflow statuses to be either cleared or set before starting the algorithm; subsequently, after each byte of
the multibyte

number

is

processed, carries are passed from one byte to the next via these
in

two

status flags, as described

Chapter

2.

We

will therefore include

these eight status instructions:

6 5 4 3 2
i

10.
i i

Bit

No.

loioiohni

00

Select Carry (C)

01 Select Overflow (0) "10 Select Zero (Z)

1 1

Select Sign

(S)

__0 Reset
1

status to
1

Set status to

.Status instruction specified

7-52

The Set Status

instruction will have this format:

STATUS SET

SET

The Reset Status

instruction will have this format:

STATUS RESET
J

RES
each case. X may be
C. O.

X
one
of the four status flags.

In

or S, to identify

No

other symbol

is

allowed.

As an example

with the secondary

addition routine, described along of status instruction use. the multibyte. binary status: reference instructions, starts out by clearing the Carry

memory
RES

Clear Carry status

LOOP

LMA
ABA
SSA

DCO
DC1

Load next input byte

Add

binary from

answer

buffer

DC 1, LOOP
addition

Store the result, increment and skip

Once

in

the

loop.

the.

binary

instruction

ABA

sets

and

resets

the

Carry

status

appropriately.

HALT INSTRUCTION
Every microcomputer has a Halt instruction.

When

this

instruction

is

executed, the

microcomputer that has a front panel, microcomputer simply stops. In a minicomputer, or in a on the panel. So far as the CPU is conprogram execution is restarted by hitting a restart button described in Chapter 4) must be signal which is input to the CPU (and was
cerned, the reset

pulsed
In

in

order to

start

execution after a Halt instruction.

the Halt instruction object code conour microcomputer, and in many other microcomputers, since unused memory words frequently contain bits This is done with good reason, all while being debugged, makes a wild jump and tries to exbits In the event that a program, all no instructions exist, there is a very good in some area of memory where ecute instructions which will cause the pronext instruction object code
sists of

chance

that

it

will pick

gram

to simply stop,

up all Os for the and do as little harm as possible.

will be,

The

Halt instruction

mnemonic

appropriately:

HALT

AN INSTRUCTION SET SUMMARY

You
microcomputers provide tables that will find that books describing individual These summary tables summarize the microcomputer instruction set cryptically. general understanding of assembly are very useful. Assuming that you have a you need to know about operalanguages, two or three pages tell you everything
tions performed

when any

instruction

is

executed.

We

instruction set with summary Table are going to summarize our hypothetical the instruction sets for real 7-1. In Volume 2 similar tables will summarize

microcomputers.

7-53

In

Table 7-1, symbols are used as follows

Accumulator

ACO
AC1

ACO
address

Accumulator AC1

ADDR
C

A
An

16-bit

memory

Carry status
8-bit binary data unit

DATA
DCO
DC1

Data Counter

DCO
DC2

Data Counter DC1 Data Counter

DC2

OCX
DISP

Any

data counter

An

8-bit signed binary address

displacement

DST
I

Any
Any

destination register
status indicator

Overflow status

An
Any

I/O port number

PC
R S

Program Counter
register

Sign status

SP

Stack Pointer

SRC

Any source
Statuses

register

SW
z

Zero Status
Contents of location enclosed within brackets. If a register designation is enclosed within the brackets, then the designated register's contents are specified If an I/O port number is enclosed within the brackets, then the I/O port contents are specified If a memory address is enclosed within the brackets, then the contents of the addressed

memory
[[]]
Implied

location are specified.

memory

addressing; the contents of the

memory

contents of a

location designated by the

register.

A
V

Logical
Logical

AND
OR OR
in

V
*~
<

logical Exclusive

Data

is
is

transferred

the direction of the arrow.

either side of the arrow.
in

Data

exchanged between the two locations designated on

of

Under the heading

STATUSES

in

Table 7-

course of the instructions' execution. If there it had before the instruction was executed.

an X indicates statuses which are modified

the

is

no

X.

it

means

that the status maintains the value

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7-59

APPENDIX A

STANDARD CHARACTER CODES

Hexadecimal
Representation

ASCII
(7 bit)

EBCDIC
(8 bit)

Hexadecimal
Representation
3F

ASCII
<7bit)
?

EBCDIC
(8 bit)

40
2 3

@
A
B

blank

41

4
5

6
7

8
9

42 43 44 45 46 47 48
49

C D
E
F

G H
I

A
B

4A
4B
,4C

K
L
<
(

D
E
F

4D
4E
4F

M
N
P

+
1

10
11

50
51

&

12

Q
R S

13
14 15 16
17

52

53 54 55 56 57 58 59

U V

18 19

w
X
Y z
[

1A
IB

5A
5B 5C

1C

$
*

1D
1E 1F

\
) I

5D
blank
l

20
21

5E 5F 60
61
a

22

23 24 25

#
$

62 63 64

b
c

%
e
(

d
e
f

26 27 28 29

65 66 67 68 69

g
h
i

2A
2B 2C

+
I

6A
6B 6C

k
1

2D
2E

%
> ?

6D
6E 6F

m
n

2F 30
31

o
1

70
71

P
q
r

32 33

3
4
5

72

34 35 36 37 38 39

73 74
75

s
t

6
7

u V

76
77

8 9

w
X

78 79

3A
3B

V
z

7A
<

3C

3D
3E
>

7B 7C

# @

7D

A-1

APPENDIX A
Hexadecimal
Representation
7E 7F

(continued)

ASCII
(7 bit)

EBCDIC
(8 bit)

Hexadecimal
Representation
BF

ASCII
(7bit)

EBCDIC
(8 bit)

CO
C1
a

80
81

A
B

82

b
c

83 84 85 86 87 88 89

d e
f

C2 C3 C4 C5 C6
C7

D
E F

G
H
I

g
h
i

C8 C9

CA
CB

8A
8B 8C

CC

CD
CE CF

8D
8E 8F

DO
D1
J

90
91
]

D2
k
I

K
L

92

93 94 95 96 97 98 99

m
n

P
q
r

D3 D4 D5 D6 D7 D8 D9

M
N
P

Q
R

DA
DB DC DD
DE DF
EO
E1

9A
9B 9C

9D
9E
9F

AO
A1

E2
s
t

A2 A3 A4 A5 A6 A7 A8 A9

u V

E3 E4 E5 E6
E7 E8 E9

S T

w
X Y
z

w
X y
z

EA
EB EC

AA
AB AC

ED
EE EF FO
F1
1

AD
AE AF
BO
B1

F2 F3

2 3

B2

B3 B4 B5 B6 B7 B8 B9

F4
F5

4
5

F6
F7 F8

6
7

8 9

F9

FA
FB FC

BA
BB BC

FD
FE
FF

BD
BE

A-2

AN INTRODUCTION TO MICROCOMPUTERS

\WFil

BY

ADAM OSBORNE

TO ORDER ADDITIONAL COPIES Adresser touts commande a

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