ISO5500

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2.5 A Isolated IGBT, MOSFET Gate Driver

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1

FEATURES
2.5 A Maximum Peak Output Current Drives IGBTs up to IC = 150 A, VCE = 1200 V Capacitive Isolated Fault Feedback CMOS/TTL Compatible Inputs 300 ns Maximum Propagation Delay Soft IGBT Turn-off Integrated Fail-safe IGBT Protection High VCE (DESAT) Detection Under-Voltage Lockout (UVLO) Protection with Hysteresis User Configurable Functions Inverting, Non-inverting Inputs Auto-Reset Auto-Shutdown Wide VCC1 Range: 3 V to 5.5 V Wide VCC2 Range: 15 V to 30 V Operating Temperature: 40C to 125C Wide-body SO-16 Package 50 kV/us Transient Immunity Typical 6000 VPeak Isolation Regulatory Approvals: UL1577 Approved; CSA, DIN EN 60747-5-2, IEC 60950-1 and 61010-1 Pending

APPLICATIONS
Isolated IGBT and MOSFET Drives in Motor Control Motion Control Industrial Inverters Switched-Mode Power Supplies

DESCRIPTION
The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to IC = 150 A and VCE = 1200 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO2), isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates ground, and prevents noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The device provides over-current protection (DESAT) to an IGBT or MOSFET while an Undervoltage Lockout circuit (UVLO) monitors the output power supply to ensure sufficient gate drive voltage. If the output supply drops below 12 V, the UVLO turns the power transistor off by driving the gate drive output to a logic low state. For a DESAT fault, the ISO5500 initiates a soft shutdown procedure that slowly reduces the IGBT/MOSFET current to zero while preventing large di/dt induced voltage spikes. A fault signal is then transmitted across the isolation barrier, actively driving the open-drain FAULT output low and disabling the device inputs. The inputs are blocked as long as the FAULT-pin is low. FAULT remains low until the inputs are configured for an output low state, followed by a logic low input on the RESET pin. The ISO5500 is available in a 16-pin SOIC package and is specified for operating temperatures from 40C to 125C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

VCC1

VREG

ISO5500
-

VCC2
UVLO

VIN+ V INDELAY
ISO - Barri er

+ +

VC DESAT
DESAT 12 .3V

Gate Drive and

7.2 V

FAULT
Q S R

Fault Logic

Q1b Q4

Q1a

VOUT VE
Q3

RESET

Q2b

Q2a

GND1

VEE-P VEE-L

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VIN+ VINVCC1 GND1 RESET FAULT NC GND1

1 2 ISOLATION 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

PIN FUNCTIONS
PIN NO. 1 2 3 4,8 5 6 7 9 10, 15 11 12 13 14 16 NAME VIN+ VIN VCC1 GND1 RESET FAULT NC VEE-P VEE-L VOUT VC VCC2 DESAT VE Non-inverting gate drive voltage control input Inverting gate drive voltage control input Positive input supply (3 V to 5.5 V) Input ground FAULT reset input Open-drain output. Connect to 3.3k pull-up resistor Not connected Most negative output-supply potential of the power output. Connect externally to pin 10. Most negative output-supply potential of the logic circuitry. Pin 10 and 15 are internally connected. Connect at least pin 10 externally to pin 9. Pin 15 can be floating. Gate drive output voltage Gate driver supply. Connect to VCC2. Most positive output supply potential Desaturation voltage input Gate drive common. Connect to IGBT Emitter. DESCRIPTION

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)
VALUE MIN Supply voltage, VCC1 Total output supply voltage, VOUT(total) Positive output supply Voltage, VOUT+ Negative output supply voltage, VOUTVoltage at Peak gate drive output voltage Collector voltage, VC Output current , IO
(1)

MAX 6 35 35 (VE VEE-P) VCC2 VCC2 6 VCC2 VCC2 2.8 20

UNIT V V V V V V V A mA kV kV V C C

0.5 (VCC2 VEE-P) (VCC2 VE) (VE VEE-P) DESAT VIN+, VIN, RESET Vo(peak) 0.5 0.5 0.5 VE 0.5 0.5 0.5 0.5

FAULT output current, IFL Electrostatic Discharge, ESD Human Body Model Charged Device Model Machine Model ESDA / JEDEC JS-001-2012 JEDEC JESD22-C101E JEDEC JESD22-A115-A -65 All pins

4 1.5 200 170 150

Maximum junction temperature, TJ Maximum storage temperature, TSTG (1) Maximum pulse width = 10 s, maximum duty cycle = 0.2%.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN VCC1 VOUT(total) VOUT+ VOUT VC tui tuiR VIH VIL fINP VSUP_SR TJ TA (1) (2) Supply voltage Total output supply voltage (VCC2 VEE-P) Positive output supply voltage (VCC2 VE) Negative output supply voltage (VE VEE-P) Collector voltage Input pulse width RESET Input pulse width High-level input voltage (VIN+, VIN, RESET) Low-level input voltage (VIN+, VIN, RESET) Input frequency Supply Slew Rate (VCC1 or VCC2 VEE-P) Junction temperature Ambient temperature
(2)

TYP

MAX 5.5 30 30V (VE VEE-P) 15 VCC2

UNIT V V V V V s s

3 15 15 0 VEE-P + 8 0.1 0.1 2 0

VCC 0.8 520 (1) 75

V V kHz V/ms C C

40 -40 25

150 125

If TA = 125C, VCC1= 5.5 V, VCC2 = 30 V, RG = 10 , CL = 1 nF If VCC1 skew is faster than 75 V/ms (especially for the falling edge) then VCC2 must be powered up after VCC1 and powered down before VCC1 to avoid output glitches.

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ELECTRICAL CHARACTERISTICS
All typical values are at TA = 25C, VCC1 = 5 V, VCC2 VE = 30 V, VE VEE-P = 0 V (unless otherwise noted)
PARAMETER ICC1 ICC2 ICH ICL IEH IEL IIH IIL IFH IFL VIT+(UVLO) VIT(UVLO) VHYS
(UVLO)

TEST CONDITIONS Quiescent 300 kHz Quiescent 300 kHz VI = VCC1 or 0 V, No load, See Figure 1, Figure 2, Figure 28, and Figure 29 VI = VCC1 or 0 V, No load, See Figure 3 through Figure 5, Figure 30, and Figure 31 IOUT = 0, See Figure 27 and Figure 30 IOUT = 650 A, See Figure 27 and Figure 30 See Figure 27 and Figure 31 See Figure 6 and Figure 40 See Figure 6 and Figure 41 IN from 0 to VCC VFAULT = VCC1, no pull-up, See Figure 33 VFAULT = 0.4 V, no pull-up, See Figure 34 See Figure 32

MIN

TYP 5.5 5.7 8.4 9

MAX 8.5 8.7 12 14 1.3 1.9 0.4

UNIT mA

Supply current

Supply current

mA

High-level collector current Low-level collector current VE High-level supply current VE Low-level supply current High-level input leakage Low-level input leakage High-level FAULT pin output current Low-level FAULT pin output current Positive-going UVLO threshold voltage Negative-going UVLO threshold voltage UVLO Hysteresis voltage (VIT+ VIT)

mA mA mA mA

0.5 0.8

0.3 0.53 10

10 10 5 11.6 12 12.3 11.1 0.7 1.2 1.6 13.5 12.4 10

A A mA

IOH

High-level output current

VOUT = VCC2 4 V (1), See Figure 7 and Figure 35 VOUT = VCC2 15 V , See Figure 7 and Figure 35 VOUT = VEE-P + 2.5 V (1), See Figure 8 and Figure 36 VOUT = VEE-P + 15 V , See Figure 8 and Figure 36 VOUT VEE-P = 14 V, See Figure 9 and Figure 37 IOUT = 100 mA, See Figure 10, Figure 11 and Figure 38 IOUT = 650 A, See Figure 10, Figure 11 and Figure 38 IOUT = 100 mA, See Figure 12, Figure 13 and Figure 39 VDESAT = 0 V to 6 V, See Figure 14 and Figure 42 VDESAT = 8 V, See Figure 42 (VCC2 VE) > VTH-(UVLO), See Figure 15 and Figure 42 VI = VCC1 or 0 V, VCM at 1500 V, See Figure 43 though Figure 46
(2) (2)

1 2.5 1 2.5 90 VC-1.5 VC-0.15

1.8 A

IOL

Low-level output current

IOF

Output-low fault current

140 VC-0.8

230

mA

VOH

High-level output voltage

V VC-0.05 0.2 180 20 6.7 25 270 45 7.2 50 7.7 0.5 380 V A mA V kV/S

VOL ICHG IDSCHG VDSTH CMTI

Low-level output voltage Blanking capacitor charging current Blanking capacitor discharge current DESAT threshold voltage Common mode transient immunity

(1) (2)

Maximum pulse width is 50 s, maximum duty cycle is 0.5% Maximum pulse width is 10 s, maximum duty cycle is 0.2%

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SWITCHING CHARACTERISTICS
All typical values are at TA = 25C, VCC1 = 5 V, VCC2 VE = 30 V, VE VEE-P = 0 V (unless otherwise noted)
PARAMETER tPLH, tPHL tsk-p tsk-pp tsk2-pp tr tf tDESAT (90%) tDESAT (10%) tDESAT (FAULT) tDESAT (LOW) tRESET (FAULT) tUVLO tUVLO tFS
(ON) (OFF)

TEST CONDITIONS RG = 10 , CG = 10 nF, 50 % duty cycle, 10 kHz input, VCC2 VEE = 30 V, VE VEE = 0 V, See Figure 16 through Figure 19, Figure 26, Figure 47, Figure 49, and Figure 50

MIN 150

TYP 200 1.7

MAX 300 10 45 50

UNIT ns ns ns ns ns ns

Propagation Delay Pulse Skew |tPHL tPLH| Part-to-part skew (1) Part-to-part skew (2) Output signal rise time Output signal fall time DESAT sense to 90% VOUT delay DESAT sense to 10% VOUT delay DESAT sense to FAULT low output delay DESAT sense to DESAT low propagation delay RESET to high-level FAULT signal delay UVLO to VOUT high delay UVLO to VOUT low delay Failsafe output delay time from input power loss

50 55 10 300

550 2.3 550

ns s ns ns

RG = 10 , CG = 10 nF, VCC2 VEE-P = 30 V, VE VEE-P = 0 V, See Figure 20 through Figure 25, Figure 48 and Figure 51 3 1ms ramp from 0 V to 30 V 1ms ramp from 30 V to 0 V

1.8 290 180 8.2 4 6 2.8

13

s s s s

(1)

tsk-pp is the maximum difference in same edge propagation delay times (either VIN+ to VOUT or VIN to VOUT) between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits.

i.e. max
(2)

tP HL-ma x VCC1, VCC2, TA tP LH-ma x VCC1, VCC2, TA

( (

))-

tPHL -m in VCC1, VCC2,TA , tPL H-m in VCC1, VCC2,TA

( (

) )

tsk2-pp is the propagation delay difference in high-to-low to low-to-high transition ( any of the combinations VIN+ to VOUT or VIN to VOUT) between two devices operating at the same supply voltage, same temperature, and having identical packages and test circuits. i.e. min = tPHL-min (VCC1, VCC2,TA ) - tPLH-max (VCC1 ,VCC2 ,TA )

max = tP HL -ma x (VCC1, VCC2,TA ) - tPL H-min (VCC1, VCC2,TA )

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TYPICAL CHARACTERISTICS
8 7

VCC1 SUPPLY CURRENT vs. TEMPERATURE

VCC1 SUPPLY CURRENT vs. FREQUENCY

ICC1 - Supply Current (mA)

6 5 4 3 2 1 0 -40 -20 0 20
VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V

ICC1 - Supply Current (mA)

6 5 4 3 2 1

VCC1 = 3.3 V VCC1 = 5 V

40

60

80
o

100

120

140

50

100

150

200

250

300

Ambient Temperature ( C)

Input Frequency (KHz)

Figure 1. VCC2 SUPPLY CURRENT vs. TEMPERATURE

Figure 2. VCC2 SUPPLY CURRENT vs. FREQUENCY

No Load

12 11

12

ICC2 - Supply Current (mA)

10 9 8 7 6 5 4 -40 -20 0 20 40 60 80
o

ICC2 - Supply Current (mA)

11 10 9 8 7 6
VCC2 = 15 V VCC2 = 20 V VCC2 = 30 V

VCC2 = 15 V VCC2 = 20 V VCC2 = 30 V

100

120

140

50

100

150

200

250

300

Ambient Temperature ( C)

Input Frequency (KHz)

Figure 3. VCC2 SUPPLY CURRENT vs. LOAD CAPACITANCE

RG = 10 W

Figure 4. VE SUPPLY CURRENT vs. TEMPERATURE

0

70

ICC2 - Supply Current (mA)

60 50 40 30 20 10 0 0

IEH, IEL - Supply Current (mA)

fINP = 20 kHz

-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8

IEH, VE - VEE = 0 V IEH, VE - VEE = 15 V IEL, VE - VEE = 0 V IEL, VE - VEE = 15 V

VCC2 = 15 V VCC2 = 30 V

20

40

60

80

100

-40

-20

20

40

60

80
o

100

120

140

Load Capacitance (nF)

Ambient Temperature ( C)

Figure 5.

Figure 6.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT DRIVE CURRENT vs. TEMPERATURE
0

OUTPUT SINK CURRENT vs. TEMPERATURE

8 7 6 5 4 3 2 1 0 -40
VOUT = 2.5 V VOUT = 15 V

IOH - Output Drive Current (A)

-0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -40 -20 0 20 40 60 80

o

VOUT = VC - 4 V VOUT = VC - 15 V

IOL - Output Sink Current (A)

100

120

140

-20

20

40

60

80
o

100

120

140

Ambient Temperature ( C)

Ambient Temperature ( C)

Figure 7. OUTPUT SINK CURRENT DURING A FAULT CONDITION vs. OUTPUT VOLTAGE
IOF - Output Sink Current During a Fault Condition (mA)
150 140 130 120 110 100 90 80 0 5 10 15 20 Output Voltage (V)
TA = -40oC TA = 25oC TA = 125oC

Figure 8.

HIGH OUTPUT VOLTAGE DROP vs. TEMPERATURE

VOH - VC - High Output Voltage Drop (V)
0.1 -0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 -40 -20 0 20 40 60 80
o

160

IOUT = -650 mA IOUT = -100 mA

25

30

100

120

140

Ambient Temperature ( C)

Figure 9. HIGH OUTPUT VOLTAGE vs. OUTPUT DRIVE CURRENT

30 29.5
TA = -40oC TA = 25oC TA = 125oC

Figure 10. LOW OUTPUT VOLTAGE vs. TEMPERATURE

0.35
IOUT = 100 mA

VOH - High Output Voltage (V)

VOL - Low Output Voltage (V)

29 28.5 28 27.5 27 26.5 26 25.5 25 0 0.2 0.4 0.6 0.8 1

0.3

0.25

0.2

0.15

1.2

1.4 1.5

0.1 -40

-20

20

40

60

80
o

100

120

140

Output Drive Current (A)

Ambient Temperature ( C)

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS (continued)

LOW OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
6

BLANKING CAPACITANCE CHARGING CURRENT vs. TEMPERATURE

-0.15

ICHG - Blanking Capacitor Charging Current (mA)

-0.17 -0.19 -0.21 -0.23 -0.25 -0.27 -0.29 -0.31 -0.33 -0.35 -40 -20 0 20 40 60 80
o

VOL - Low Output Voltage (V)

5 4 3 2 1 0 0 0.5 1 1.5 2 Output Sink Current (A)

TA = -40oC TA = 25oC TA = 125oC

2.5

100

120

140

Ambient Temperature ( C)

Figure 13. DESAT THRESHOLD vs. TEMPERATURE

7.9
240 230

Figure 14. PROPAGATION DELAY vs. TEMPERATURE

RG = 10 W, CL = 10 nF

VDSTH - Desat Threshold (V)

7.7 7.5 7.3 7.1 6.9 6.7 6.5 -40

Propagation Delay (ns)

220 210 200 190 180 -40

tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V

-20

20

40

60

80
o

100

120

140

-20

20

40

60

80
o

100

120

140

Ambient Temperature ( C)

Ambient Temperature ( C)

Figure 15. PROPAGATION DELAY vs. VCC1 SUPPLY VOLTAGE

225
RG = 10 W, CL = 10 nF

Figure 16. PROPAGATION DELAY vs. VCC2 SUPPLY VOLTAGE

230 225
RG = 10 W, CL = 10 nF

220

Propagation Delay (ns)

Propagation Delay (ns)

220 215 210 205 200 195 190 14

tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V

215

210

205
tPLH tPHL

200 3 3.5 4 4.5 5 5.5 VCC1 Supply Voltage (V)

16

18

20

22

24

26

28

30

VCC2 Supply Voltage (V)

Figure 17.

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

PROPAGATION DELAY vs. LOAD CAPACITANCE
1400

450

DESAT SENSE to 90% VOUT DELAY vs TEMPERATURE

RG = 10 W, CL = 10 nF

1200

Desat Sense to 90% VOUT Delay (ns)

RG = 10 W

400 350 300 250 200 150 -40

Propagation Delay (ns)

1000 800 600 400 200 0 0

tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.3 V tPLH at VCC1 = 5 V tPHL at VCC1 = 5 V

VCC2 = 15 V VCC2 = 30 V

10

20

30

40

50

60

70

80

90

100

-20

20

40

60

80
o

100

120

140

Load Capacitance (nF)

Ambient Temperature ( C)

Figure 19. DESAT SENSE to 90% VOUT DELAY vs LOAD CAPACITANCE

1600

Figure 20.

DESAT SENSE to 10% VOUT DELAY vs TEMPERATURE

2.5

Desat Sense to 90% VOUT Delay (ns)

Desat Sense to 10% VOUT Delay (ms)

1400 1200 1000 800 600 400 200 0 0

RG = 10 W

RG = 10 W,

CL = 10 nF

1.5

0.5
VCC2 = 15 V VCC2 = 30 V

VCC2 = 15 V VCC2 = 30 V

10

20

30

40

50

60

70

80

90

100

0 -40

-20

20

40

60

80
o

100

120

140

Load Capacitance (nF)

Ambient Temperature ( C)

Figure 21. DESAT SENSE to 10% VOUT DELAY vs LOAD CAPACITANCE

18

Figure 22.

DESAT SENSE to FAULT LOW DELAY vs TEMPERATURE

450

Desat Sense to 10% VOUT Delay (ms)

15 14 12 10 8 6 4 2 0 0

Desat Sense to Fault Low Delay (ns)

RG = 10 W

400 350 300 250 200 150 -40

VCC2 = 15 V VCC2 = 30 V

VCC2 = 15 V VCC2 = 30 V

10

20

30

40

50

60

70

80

90

100

-20

20

40

60

80
o

100

120

140

Load Capacitance (nF)

Ambient Temperature ( C)

Figure 23.

Figure 24.

10

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TYPICAL CHARACTERISTICS (continued)

RESET to FAULT DELAY vs TEMPERATURE
10 9.5
VCC2 - VEE = 30 V R G = 0 W, CL = 10 nF

OUTPUT WAVEFORM

Reset to Fault Delay (ms)

9 8.5 8 7.5

6.5 6 5.5 5 -40 -20 0 20 40 60 80

o

5 V / div

VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V

100

120

140

Time 125 ns / div

Ambient Temperature ( C)

Figure 25. VC SUPPLY CURRENT vs. TEMPERATURE

3

Figure 26.

ICH, ICL - Supply Current (mA)

2.5 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80

o

ICH, IOUT = -500 mA ICH, IOUT = -1 mA ICL, IOUT = -1 mA ICL, IOUT = -2 mA

100

120

140

Ambient Temperature ( C)

Figure 27.

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PARAMETER MEASUREMENT INFORMATION TEST CIRCUITS

SPACER

1 ICC1 5.5 V 0.1 F 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE 16 VEE-L 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE-L 10 VEE-P 9

5.5 V 0.1 F ICC1

1 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE 16 VEE-L 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE-L 10 VEE-P 9

Figure 28. ICC1H Test Circuit

SPACER SPACER

Figure 29. ICC1L Test Circuit

1 5V 0.1 F 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT

16 15 14 13 12 11 IOUT ICC2

1 2 3 4
IC

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 ICC2 IC

5
30 V 0.1 F

6 7 8

30 V

0.1 F

VEE-L 10 VEE-P
9

Figure 30. ICC2H, ICH Test Circuit

SPACER SPACER
1 5V 0.1 F 2 3 4 5 6 7 8 16 15 14 13 12 11 VOUT 10 9 0.1 F V2 0.1 F V1 Sweep 0.1 F

Figure 31. ICC2L, ICL Test Circuit

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

1 5.5 V 0.1 F 2 3 4 5 5.5 V IFAULT 7 8 6

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 30 V 0.1 F

Figure 32. VIT(UVLO) Test Circuit

SPACER

Figure 33. IFH Test Circuit

12

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PARAMETER MEASUREMENT INFORMATION (continued)

SPACER
1 3V 0.1 F 2 3 4 5 0.4 V IFAULT 7 8 6 16 15 14 13 12 11 10 9 30 V 0.1 F
5V 0.1 F

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

1 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 IOUT 30 V 0.1 F 4.7 F VPULSE

Figure 34. IFL Test Circuit

SPACER SPACER

Figure 35. IOH Test Circuit

1 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT

16 15 14 13 12 30 V 11 VPULSE IOUT 0.1 F 4.7 F

1 5V 0.1 F 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 IOUT 14 V 0.1 F

30 V

VEE-L 10 VEE-P
9

Figure 36. IOL Test Circuit

SPACER SPACER
1 5V 0.1 F 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IOUT VOUT 0.1 F 5V 0.1 F

Figure 37. IOF Test Circuit

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

1 2 3 4 5 30 V 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 VOUT 10 9 100 mA 0.1 F

30 V

Figure 38. VOH Test Circuit

SPACER SPACER

Figure 39. VOL Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

1 5V 0.1 F 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14

IE 0.1 F V1
0.1 F

1 5V 2 3

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14

IE 0.1 F V1

13 12 11 10 9 0.1 F V2

0.1 F

4 5 6 7 8

13 12 11 10 9 0.1 F V2

0.1 F

Figure 40. IEH Test Circuit

SPACER SPACER

Figure 41. IEL Test Circuit

1 5V 0.1 F 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10
100 pF

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 10 W 10 nF 0.1 F 4.7 F 30 V

SWEEP

0.1 F V1 0.1 F V2

5V

0.1 F

2 3

IDESAT

4 3k SCOPE 5 6 7 8

0.1 F

VCM

Figure 42. ICHG, IDSCHG, VDSTH Test Circuit

SPACER SPACER
1 5V 0.1 F 2 3 4 3k SCOPE 100 pF 5 6 7 8 16 15 14 13 12 11 10 9 10 W 10 nF 0.1 F 4.7 F 30 V 100 pF 3k 5V 0.1 F

Figure 43. CMTI VFH Test Circuit

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

1 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 10 W 10 nF SCOPE 0.1 F 4.7 F 30 V

VCM

VCM

Figure 44. CMTI VFL Test Circuit

SPACER

Figure 45. CMTI VOH Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

SPACER
1 5V 0.1 F 2 3 4 3k 5 6 100 pF 7 8 16 15 14 13 12 11 10 9 10 W 10 nF SCOPE 0.1 F 4.7 F 30 V
5V 0.1 F 3k

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

VIN GND1

1 2 3 4 5 6 7 8

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 10 W 10 nF VOUT V1 0.1 F 4.7 F

VCM

Figure 46. CMTI VOL Test Circuit

SPACER
1 VIN 2 3 4 5 6 5V 3k 0.1 F 7 8

Figure 47. tPLH, tPHL, tr, tf Test Circuit

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

VE VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

16 15 14 13 12 11 10 9 10 W 10 nF VOUT 0.1 F 4.7 F V2 DESAT V1 0.1 F 100 pF 0.1 F

Figure 48. tDESAT, tRESET Test Circuit

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PARAMETER MEASUREMENT INFORMATION (continued)

VIN0V VIN50 % VIN+ 50 % tr 50 % tf 90% 50% VOUT tPLH tPHL 10% VOUT tPLH tPHL VIN+ VCC1 tr tf 90% 50% 10% 50 %

Figure 49. VOUT Propagation Delay, Non-inverting Configuration

tDESAT (FAULT ) tDESAT (10%) 7.2V VDESAT tDESAT (LOW) 50% tDESAT (90%) VOUT 90% 10%

Figure 50. VOUT Propagation Delay, Inverting Configuration

FAULT

50 %

50 % tRESET (FAULT )

RESET

50%

Figure 51. DESAT, VOUT, FAULT, RESET Delays

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PARAMETER MEASUREMENT INFORMATION (continued) PACKAGE CHARACTERISTICS

PARAMETER L(I01) L(I02) Minimum air gap (clearance (1)) Minimum external tracking (creepage (1)) Minimum internal gap (internal clearance) CTI RIO CIO CI (1) Isolation resistance Barrier capacitance input-to-output Input capacitance to ground TEST CONDITIONS Shortest terminal to terminal distance through air Shortest terminal to terminal distance across the package surface Distance through the insulation Input to output, VIO = 500 V (2) VIO = 0.4 sin (2ft), f = 1 MHz (2) VI = VCC/2 + 0.4 sin (2 ft), f = 2 MHz, VCC = 5V MIN 8.3 8.1 0.012 400 >1012 1.25 2 TYP MAX UNIT mm mm mm V pF pF

Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1

(2)

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.space Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the isolation glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase their specification. All pins on each side of the barrier tied together creating a two-terminal device

INSULATION CHARACTERISTICS FOR DW-16 PACKAGE

Over recommended operating conditions (unless noted otherwise)
PARAMETER VIORM Maximum working insulation voltage per DIN EN 60747-5-2 After Input/Output safety test subgroup 2/3, VPR = 1.2 x VIORM, t = 10 sec, Partial discharge < 5 pC VPR Input to output test voltage per DIN EN 60747-5-2 Method a, After environmental tests subgroup 1, VPR = 1.6 VIORM, t = 10 sec (qualification) Partial discharge < 5pC Method b1, 100% Production test, VPR = 1.875 VIORM, t = 1 sec Partial discharge < 5pC VIOTM VISO RS Transient overvoltage per DIN EN 60747-5-2 Isolation voltage per UL 1577 Insulation resistance Pollution degree VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production) VTEST = VISO, t = 60 sec (qualification) VTEST = 1.2 VISO, t = 1 sec (100% production) VIO = 500 V at TS = 150C TEST CONDITIONS SPECIFICATION 1200/848 1440/1018 UNIT

1920/1358 VPEAK/ VRMS 2250/1591 6000/4243 6000/4243 7200/5092 > 109 2

REGULATORY INFORMATION
VDE CSA UL Recognized under 1577 Component Recognition Program Single Protection, 4243 VRMS File Number: E181974
(1)

Certified according to DIN EN 60747-5-2 and Approved under CSA Component EN 61010-1 Acceptance Notice 5A Basic Insulation Maximum Transient Overvoltage, 6000 VPK Maximum Working Voltage, 1200 VPK File Number: pending (1) Basic and Reinforced Insulation per CSA 60950-1-07 and IEC 60950-1 (2nd Ed) File Number: pending

Production tested 5092 VRMS for 1 second in accordance with UL 1577.

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IEC 60664-1 RATING TABLE

PARAMETER Basic Isolation Group Installation Classification Material Group Rated Mains Voltage 300 VRMS Rated Mains Voltage 600 VRMS Rated Mains Voltage 848 VRMS TEST CONDITIONS SPECIFICATION II I-IV I-III I-II

IEC SAFETY LIMITING VALUES

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER IS TS Safety Limiting Current Case Temperature TEST CONDITIONS JA = 76C/W, VI = 3.6 V, TJ = 170C, TA = 25C JA = 76C/W, VI = 5.5 V, TJ = 170C, TA = 25C JA = 76C/W, VI = 30 V, TJ = 170C, TA = 25C MIN TYP MAX 530 347 64 150 C mA UNIT

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
Safety Limiting Current - mA
600 500 400 300 200 100 0 0 50 100 Case Temperature - C
o

VCC1 = 3.6V

VCC1 = 5.5V VCC2 - VEE-P = 30 V

150

200

Figure 52. DW-16 JC Thermal Derating Curve per IEC 60747-5.2

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THERMAL INFORMATION
THERMAL METRIC (1) JA JCtop JB JT JB JCbot TSHDN+ TSHDNTSHDN-HYS PD Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance Thermal Shutdown Thermal Shutdown Hysteresis Power Dissipation See Equation 2 through Equation 6 ISO5500 DW (16) PIN 76 34 36 8 35 n/a 185 173 12 592 C C C mW C/W UNITS

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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BEHAVIORAL MODEL
Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input configuration and its corresponding timing diagram for normal operation, fault condition, and Reset.
+HV

ISO5500
PWM 1 VIN+
DIS ISO
+ -

DESAT
7.2V 270 A

14 CBLK

2 VINUVLO
+

VCC2
VREG 12.3V

13

3 VCC1 3.3V to 5V I/P 6 FAULT

DELAY

ISO - Barrie r

VC 12
Q1b Q1a

15V VOUT 11

FAULT
Q S R

VE
Q3 Q2b Q2a

O/P

5 RESET 4,8 GND1

16 15V

VREG

VCC2

VEE-P

VEE-L 10,15 -HV

Figure 53. ISO5500 Behavioral Model

Normal Operation VIN+ ISO

Fault Condition
5

Reset

Normal Operation

VDESAT VOUT FAULT

7.2V

DIS FAULT

RESET
6

Figure 54. Complete Timing Diagram

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DEVICE INFORMATION POWER SUPPLIES

VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art 3.3 V low-power controllers as well as legacy 5 V controllers. VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500. VEE-P is the supply return for the output driver and VEE-L is the return for the logic circuitry. With VEE-P as the main reference potential, VEE-L should always be directly connected to VEE-P. The supply voltage at VCC2 can range from 15 V up to 30 V with respect to VEE-P. A third voltage input, VE, serves as reference voltage input for the internal UVLO and DESAT comparators. VE also represents the common return path for the gate voltage of the external power device. The ISO5500 is designed for driving MOSFETs and IGBTs. Because MOSFETs do not require a negative gate-voltage, the voltage potential at VE with respect to VEE-P can range from 0 V for MOSFETs and up to 15 V for IGBTs.
ISO5500
VCC2 VCC1 3 V - 5.5 V ISOLATION VE 0 V-15 V 0-(-15 V) VEE-P VEE-L VEE-P VEE-L Power Device Common GND1 VC +15 V 15V 3 V - 5.5 V ISOLATION VE 0 V-15 V -15 V Power Device Common VCC1

ISO5500
VCC2 VC 15 V-30 V +15 V

GND1

Figure 55. Power Supply Configurations The output supply configuration on the left uses symmetrical 15 V supplies for VCC2 and VEE-P with respect to VE. This configuration is mostly applied when deriving the output supply from the input supply via an isolated DCDC converter with symmetrical voltage outputs. The configuration on the right, having both supplies referenced to VEE-P, is found in applications where the device output supply is derived from the high-voltage IGBT supplies.

CONTROL SIGNAL INPUTS

The two digital, TTL control inputs, VIN+ and VIN, allow for inverting and non-inverting control of the gate driver output. In the non-inverting configuration VIN+ receives the control input signal and VIN is connected to GND1. In the inverting configuration VIN is the control input while VIN+ is connected to VCC1.
ISO5500 3 V - 5.5 V PWM VCC1 VIN+
ISOLATION

ISO5500 VCC1 3 V - 5.5 V VINISOLATION

VIN+

VCC1

VIN+ VIN-

VIN-

GND1 PWM

VIN+ VIN-

GND1

VOUT

GND1 VOUT

Figure 56. Non-inverting (left) and Inverting (right) Input Configurations

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OUTPUT STAGE
The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the most positive potential, typically VCC2, and the most negative potential, VEE-P.
VCC2

ISO5500

VC VIN+ 15V 30V VOUT VOUT

VGE

Q1b On

Q1a

Gate Drive
Off Q3 Slow Off Q2b Q2a

Q1 0V +15V

Q2

Q1

Q3 Q2

VE 15V
VE VE

VEE-P VEE-L

VGE -15V

Figure 57. Output Stage Design and Timing This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair (Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and a MOSFET for close-to-rail switching capability. An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to prevent large di/dt voltage transients which potentially could damage the output circuitry. The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also includes a break-before-make function to prevent both transistor pairs from conducting at the same time. By introducing the reference potential for the IGBT emitter, VE, the final IGBT gate voltage, VGE, assumes positive and negative values with respect to VE. A positive VGE of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of short circuit currents of up to 510 times the rated collector current over a time span of up to 10 s. Negative values of VE, ranging from a required minimum of 5 V up to a recommended 15 V, are necessary to keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus allow the VE-pin to be directly connected to VEE-P. The timing diagram in Figure 57 shows that during normal operation VOUT follows the switching sequence of VIN+ (here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying VCC2 and VEE-P potential to the VOUT-pin respectively. In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3 turns on to slowly reduce VOUT in a controlled manner down to a level of approximately 2 V above VEE-P. At this voltage level, the strong Q2 pair then conducts holding VOUT at VEE-P potential.

UNDER VOLTAGE LOCKOUT (UVLO)

The Under Voltage Lockout feature prevents the application of insufficient gate voltage (VGE-ON) to the power device by forcing VOUT low (VOUT = VEE-P) during power-up and whenever else VCC2 VE drops below 12.3 V. IGBTs and MOSFETs typically require gate voltages of VGE = 15 V to achieve their rated, low saturation voltage, VCES. At gate voltages below 13 V typically, their VCE-ON increases drastically, especially at higher collector currents. At even lower voltages, i.e. VGE < 10 V, an IGBT starts operating in the linear region and quickly overheats. Figure 58 shows the principle operation of the UVLO feature.
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VCC2
-

VCC2

12.3V 11.1V 2V

UVLO
+

VC

On

15V VIN+ 12.3V

Q1b Q1a

Gate Drive

VOUT
VGE

VE
Off Q2b Q2a

VOUT

Failsafe Low 0V R PD Q2

Q1

Q2

Q1

Q2

Q1

15V VEE-P VEE-L

VE

+15V VGE -15V

VE

ISO5500

Figure 58. Under Voltage Lockout (UVLO) Function Because VCC2 with respect to VE represents the gate-on voltage, VGE-ON = VCC2 VE, the UVLO comparator compares VCC2 to a 12.3 V reference voltage that is also referenced to VE via the connection of the ISO5500 VEpin to the emitter potential of the power device. The comparator hysteresis is 1.2 V typical and the typical values for the positive and negative going input threshold voltages are VTH+ = 12.3 V and VTH = 11.1 V. The timing diagram shows that at VCC2 levels below 2 V VOUT is 0 V. Because none of the internal circuitry operates at such low supply levels, an internal 100 k pull-down resistor is used to pull VOUT down to VEE-P potential. This initial weak clamping, known as failsafe-low output, strengthens with rising VCC2. Above 2 V the Q2-pair starts conducting gradually until VCC2 reaches 12.3 V at which point the logic states of the control inputs VIN+ and VIN begin to determine the state of VOUT. Another UVLO event takes place should VCC2 drop slightly below 11 V while the IGBT is actively driven. At that moment the UVLO comparator output causes the gate-drive logic to turn off Q1 and turn on Q2. Now VOUT is clamped hard to VEE-P. This condition remains until VCC2 returns to above 12.3 V and normal operation commences. NOTE An Under Voltage Lockout does not indicate a Fault condition.

DESATURATION FAULT DETECTION (DESAT)

The DESAT fault detection prevents IGBT destruction due to excessive collector currents during a short circuit fault. Short circuits caused by user misconnect, bad wiring, or overload conditions induced by the load can cause a rapid increase in IGBT current, leading to excessive power dissipation and heating. IGBTs become damaged when the current load approaches the saturation current of the device and the collector-emitter voltage, VCE, rises above the saturation voltage level, VCE-sat. The drastically increased power dissipation overheats and destroys the IGBT. To prevent damage to IGBT applications, the implemented fault detection slowly reduces the overcurrent in a controlled manner during the fault condition.

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VCC2

ISO5500
+

VC DESAT

15V VIN+

DESAT
-

On

CBLK 7.2V
Q4 Q1b Q1a

VDESAT

7.2V

Q4

Gate Drive
Dschg

VOUT VE

VCE VOUT

Fault Off Slow Off Q3 Q2b Q2a

15V Fault VEE-P VEE-L

Figure 59. DESAT Fault Detection and Protection The DESAT fault detection involves a comparator that monitors the IGBTs VCE and compares it to an internal 7.2 V reference. If VCE exceeds this reference voltage, the comparator causes the gate-drive and fault-logic to initiate a fault shutdown sequence. This sequence starts with the immediate generation of a fault signal, which is transmitted across the isolation barrier towards the Fault indicator circuit at the input side of the ISO5500. At the same time the fault logic turns off the power-pair Q1 and turns on the small discharge MOSFETs, Q3 and Q4. Q3 slowly discharges the IGBT gate voltage which causes the high short-circuit current through the IGBT to gradually decrease, thereby preventing large di/dt induced voltage transients. Q4 discharges the blanking capacitor. Once VOUT is sufficiently close to VEE-P potential (at approximately 2 V), the large Q2-pair turns on in addition to Q3 to clamp the IGBT gate to VEE-P. NOTE The DESAT detection circuit is only active when the IGBT is turned on. When the IGBT is turned off, and its VCE is at maximum, the fault detection is simply disabled to prevent false triggering of fault signals.

DESAT BLANKING TIME

The DESAT fault detection must remain disabled for a short time period following the turn-on of the IGBT to allow its collector voltage to drop below the 7.2 V DESAT threshold. This time period, called the DESAT blanking time, tBLK, is controlled by an internal charge current of ICHG = 270 A, the 7.2 V DESAT threshold, VDSTH, and an external blanking capacitor, CBLK. The nominal blanking time with a recommended capacitor value of CBLK = 100 pF is calculated with:
tBL K = CBL K VDSTH ICHG = 100 pF 7.2 V 270 A = 2.7 s

(1)

The capacitor value can be scaled slightly to adjust the blanking time. However, because the blanking capacitor and the DESAT diode capacitance build a voltage divider that attenuates large voltage transients at DESAT, CBLK values smaller than 100 pF are not recommended. The nominal blanking time also represents the ISO5500 maximum response time to a DESAT fault condition. If a short circuit condition exists prior to the turn-on of the IGBT, (causing the IGBT switching into a short) the soft shutdown sequence begins after approximately 3 s. However, if a short circuit condition occurs while the IGBT is already on, the response time is significantly shorter due to the parasitic parallel capacitance of the DESAT diode. The recommended value of 100 pF however, provides sufficient blanking and fault response times for most applications.
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The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault condition. The use of VIN+ as control input implies non-inverting input configuration. During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges CBLK through the IGBT. In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and also produces a Fault signal that is fed back to the input side of the ISO5500.

FAULT ALARM
The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed. Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain output, it requires a pull-up resistor, RPU, in the order of 3.3 k to 10 k. The internal signals DIS, ISO, and FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.
VCC1 3.3V VIN+
DIS ISO ISO - Barrier

ISO5500

VIN+

IGBT On

PWM

ISO

VIN-

C
I/P

RPU DELAY FAULT

Q S R

Sh oc ort cu rs
3

FAULT
2 1

lay De

FAULT

DIS

O/P

RESET

FAULT

GND1

RESET

Figure 60. Fault Alarm Circuitry and Timing Sequence The timing diagram shows that the micro controller initiates an IGBT-on command by taking VIN+ high. After propagating across the isolation barrier ISO goes high, activating the output stage. 1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which sets the RS-FF driving the FAULT output active-low. 2. After a delay of approximately 3 s, the time required to shutdown the IGBT, DIS becomes high and blocks the control inputs 3. This in turn drives ISO low 4. which, after propagating through the output fault-logic, drives FAULT low. At this time both flip-flop inputs are low and the fault signal is stored. 5. Once the failure cause has been removed the micro controller must set the control inputs into an "Outputlow" state before applying the Reset pulse. 6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling FAULT high and releases the control inputs by driving DIS low

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APPLICATION INFORMATION TYPICAL APPLICATION

Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Threephase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high power applications such as High-Voltage DC (HVDC) power transmission. The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5500 devices that are connected to one of the three load terminals. The operation of the three switches is coordinated so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a sixstep line-to-line output waveform. In this type of applications carrier-based PWM techniques are applied to retain waveform envelope and cancel harmonics.
ISOLATION BARRIER ISO 5500

ISO

5500

PWM 3-PHASE INPUT

1 2 3 4 5 6

ISO

5500

C ISO 5500

FAULT ISO 5500

ISO

5500

Figure 61. Typical Motor Drive Application

RECOMMENDED ISO5500 APPLICATION CIRCUIT

The ISO5500 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 62 illustrates a typical gate drive implementation using the ISO5500. The four 0.1 F supply bypass capacitors provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, low current (20 mA) power supplies for VCC2 and VEE-P suffice. The 100 pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode and its 100 series resistor are important external protection components for the fault detection circuitry. The 10 gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times. The open-drain fault output has a passive 3.3 k pull-up resistor and a 330pF filtering capacitor. In this application, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the micro-controller applies a reset signal.

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1 2 3

V IN+ V INV CC1 GND1 RESET FAULT NC GND1

ISO5500

VE VEE -L DESAT V CC2 VC VOUT VEE -L V EE-P

16 15 14 13 12 11 10 9 0.1 F 15V Q2 + VCE 4.7 F 15V Rg 3-PHASE OUTPUT 100 0.1 pF F 0.1 F DS (opt.) 100 D DESAT + VF Q1 + VCE

3.3V 3.3 k

0.1 F

4 5 6

330 pF

7 8

Figure 62. Recommended Application Circuit

FAULT PIN CIRCUITRY

The FAULT pin is an open-drain output requiring a 3.3 k pull-up resistor to provide logic high when FAULT is inactive. Because fast common mode transients can alter the FAULT-pin voltage during high state, a 330 pF capacitor connected between FAULT and GND1 is recommended to provide sufficient noise margin at the specified CMTI of 50 kV/s. The added capacitance does not increase the FAULT response time during a fault condition.
1 2 3

VIN+ VINVCC1 GND1

ISO5500

5V 3.3 kW

0.1 F

4 5 6

RESET FAULT NC GND1

330 pF

7 8

Figure 63. FAULT Pin Circuitry for High CMTI

DRIVING THE CONTROL INPUTS

The amount of common-mode transient immunity (CMTI) is primarily determined by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5500. For maximum CMTI performance, the digital control inputs, VIN+ and VIN, must be actively driven by standard CMOS or TTL, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5500 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pull-up resistors, must be avoided.

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ISO5500
SLLSE64A SEPTEMBER 2011 REVISED JULY 2012 www.ti.com

LOCAL SHUTDOWN AND RESET

In applications with local shutdown and reset, the FAULT output of each gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition.
1 2 3

VIN+ VINVCC1

ISO5500

1 2 3

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

ISO5500

C RF

4 5 6 7 8

C GND1 RESET FAULT NC GND1 RF

4 5 6 7 8

Figure 64. Local Shutdown and Reset for Non-inverting (left) and Inverting Input Configuration (right)

GLOBAL-SHUTDOWN AND RESET

When configured for inverting operation, the ISO5500 can be configured to shutdown automatically in the event of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open drain FAULT outputs of multiple ISO5500 devices can be wired together forming a single, common fault bus for interfacing directly to the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FAULT output disables all six gate drivers simultaneously; thereby, providing protection against further catastrophic failures.
1 2 3

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

ISO5500

4 5 6 7 8

to other RESETs

to other FAULTs

Figure 65. Global Shutdown with Inverting Input Configuration

AUTO-RESET
Connecting RESET to the active control input (VIN+ for non-inverting, or VIN for inverting operation) configures the ISO5500 for automatic reset capability. In this case, the gate control signal at VIN is also applied to the RESET input to reset the fault latch every switching cycle. During normal IGBT operation, asserting RESET low has no effect on the output. For a fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the 'gate low' state and resets the fault latch. If the gate control signal is a continuous PWM signal, the fault latch will always be reset before VIN+ goes high again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next 'on' cycle. When the ISO5500 is configured for Auto Reset, the specified minimum FAULT signal pulse width is 3 s.

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ISO5500
www.ti.com SLLSE64A SEPTEMBER 2011 REVISED JULY 2012

1 2 3

VIN+ VINVCC1

ISO5500

1 2 3

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

ISO5500

4 5 6 7 8

C GND1 RESET FAULT NC GND1

4 5 6 7 8

Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration

RESETTING FOLLOWING A FAULT CONDITION

To resume normal switching operation following a fault condition (FAULT output low), the gate control signal must be driven into a 'gate low' state before asserting RESET low. This can be accomplished with a microcontroller, or an additional logic gate that synchronizes the RESET signal with the appropriate input signal.
1 2 3

VIN+ VINVCC1

ISO5500

1 2 3

VIN+ VINVCC1 GND1 RESET FAULT NC GND1

ISO5500

4 5 6 7 8

C GND1 RESET FAULT NC GND1

4 5 6 7 8

Figure 67. Auto Reset with Prior Gate-low Assertion for Non-inverting and Inverting Input Configuration

DESAT PIN PROTECTION

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100 to 1 k resistor is connected in series with the DESAT diode. The added resistance neither alters the DESAT threshold nor the DESAT blanking time. Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of the DESAT input to VE potential at low voltage levels.

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ISO5500
SLLSE64A SEPTEMBER 2011 REVISED JULY 2012 www.ti.com

ISO5500

VE

16 15 14 13 12 11 15V Rg + VFW-inst 100 pF + VFW DS (opt.) RS DDESAT

VEE-L DESAT VCC2 VC VOUT

VEE-L 10 VEE-P
9

15V

Figure 68. DESAT Pin Protection with Series Resistor and Optional Schottky Diode

DESAT DIODE AND DESAT THRESHOLD

The DESAT diodes function is to conduct forward current, allowing sensing of the IGBTs saturated collector-toemitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the IGBT. This results in a charging current ICHARGE = CD-DESAT x dVCE/dt, charging the blanking capacitor. To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ CBLANK / CD-DESAT. Table 1 lists a number of fast-recovery diodes suitable for the use as DESAT diodes. Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = VDESAT, the VCE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT(TH) = 7.2 V n x VF (where n is the number of DESAT diodes). When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be chosen. Table 1. Recommended DESAT Diodes
PART NUMBER STTH112 MUR100E MURS160T3 UF4007 BYM26E BYV26E BYV99 MANUFACTURER STM Motorola Motorola General Semi. Philips Philips Philips trr (ns) 75 75 75 75 75 75 75 VRRM-max (V) 1200 1000 600 1000 1000 1000 600 PACKAGE SMA, SMB, DO-41 59-04 (axial leaded) Case 403A (SMD) DO-204AL (axial leaded) SOD64 (axial leaded) SOD57 (axial leaded) SOD87 (axial leaded)

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ISO5500
www.ti.com SLLSE64A SEPTEMBER 2011 REVISED JULY 2012

DETERMINING THE MAXIMUM AVAILABLE, DYNAMIC OUTPUT POWER, POD-max

The ISO5500 total power consumption of PD = 592 mW consists of the total input power, PID, the total output power, POD, and the output power under load, POL:
PD = PID + POD + POL With: PID = VCC1-max ICC1-max = 5.5 V 8.5 mA = 47 mW, and: POD = (VCC2 VEE-P) x ICC2-q = 30 V 14 mA = 420 mW, then: POL = PD PID POD = 592 mW 47 mW 420 mW = 125 mW. (2) (3) (4) (5)

In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety of parameters:
POL-WC = 0.5 fINP QG

(VCC2

ron-max roff-max - VEE-P ) + roff-max + RG ron-max + R G

(6)

Where fINP = signal frequency at the control input VIN() QG = power device gate charge VCC2 = positive output supply with respect to VE VEE-P = negative output supply with respect to VE ron-max = worst case output resistance in the on-state: 4 roff-max = worst case output resistance in the off-state: 2.5 RG = gate resistor Once RG is determined, Equation 6 is to be used to verify whether POL-WC < POL. Figure 69 shows a simplified output stage model for calculating POL-WC.
ISO5500 VCC2 VC ron-max VOUT RG QG roff-max
15 V 15 V

VEE-P

Figure 69. Simplified Output Model for Calculating POL-WC

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ISO5500
SLLSE64A SEPTEMBER 2011 REVISED JULY 2012 www.ti.com

DETERMINING GATE RESISTOR, RG

The value of the gate resistor determines the peak charge and discharge currents, ION-PK and IOFF-PK. Due to the transient nature of these currents, their peak values only occur during the on-to-off and off-to-on transitions of the gate voltage. In order to calculate RG for the maximum peak current, ron and roff must be assumed zero. The resulting charge and discharge models are shown in Figure 70.
ISO5500 VCC2 VC
15 V

ISO5500 VCC2 VC
15 V

V CC2 - VEE-P VOUT Ion RG VE

15 V

V CC2 - VEE-P VOUT CG VE

15 V

Ioff RG CG

VEE-P

VEE-P

Figure 70. Simplified Gate Charge and Discharge Model Off-to-On Transition In the off-state, the upper plate of the gate capacitance, CG, assumes a steady-state potential of VEE-P with respect to VE. When turning on the power device, VCC2 is applied to VOUT and the voltage drop across RG results in a peak charge current of ION-PK = (VCC2 VEE-P)/RG. Solving for RG then provides the necessary resistor value for a desired on-current via: V - VEE-P RG = CC2 ION-PK (7) On-to-Off Transition When turning the power device off, the current and voltage relations are reversed but the equation for calculating RG remains the same. Once RG has been calculated, it is necessary to check whether the resulting, worst-case power consumption, POD-WC, (derived in Equation 6) is below the calculated maximum, POL = 125 mW (calculated in Equation 5).

Example
The example below considers an IGBT drive with the following parameters: ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE-P = 5 V Applying Equation 7, the value of the gate resistor is calculated with 15V - ( - 5V) RG = = 10 2A Then, calculating the worst-case output power consumption as a function of RG, using Equation 6 yields 4 2.5 POL-WC = 0.5 20 kHz 650 nC (15 V - ( - 5V)) + = 63 mW 4 + 10 2.5 + 10

(8)

(9)

Because POL-WC = 63 mW is well below the calculated maximum of POL = 125 mW, the resistor value of RG = 10 is fully suitable for this application.

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www.ti.com SLLSE64A SEPTEMBER 2011 REVISED JULY 2012

DETERMINING COLLECTOR RESISTOR, RC

Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK. Reducing ION-PK is accomplished by inserting an external resistor, RC, between the VC- pin and the VCC2- pin of the ISO5500.
ISO5500 VCC2 VC RC
15 V

ISO5500 VCC2

VC

C2 -

VC

VE

15 V

E- P

VOUT

Ion-pk RG CG

VOUT

Ioff-pk

VCC2 - VEE-P RG CG

VE
15 V

VE
15 V

VEE-P

VEE-P

Figure 71. Reducing ION-PK by Inserting Resistor RC Figure 71 (right) shows that during the on-transition, the (VCC2 VEE-P) voltage drop occurs across the series resistance of RC + RG, thus reducing the peak charge current to: ION-PK = (VCC2 VEE-P) /(RC + RG). Solving for RC provides: V - VEE-P RC = CC2 - RG ION-PK (10) To stay below the maximum output power consumption, RG must be calculated first via:
RG = VCC2 - VEE-P IOFF-PK

(11)

and the necessary comparison of POL-WC versus POL must be completed. Once RG is determined, calculate RC for a desired on-current using Equation 10. Another method is to insert Equation 11 into Equation 10 and arriving at:
I RC = R G OFF-PK - 1 ION-PK

(12)

Example Reducing the peak charge current from the previous example to ION-PK = 1.5 A, requires a RC value of: 2A RC = 10 - 1 = 3.33 1.5 A

(13)

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SLLSE64A SEPTEMBER 2011 REVISED JULY 2012 www.ti.com

HIGHER OUTPUT CURRENT USING AN EXTERNAL CURRENT BUFFER

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 72) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.
ISO5500 VE
16 15 14 13 12 11 10 9 15 V 10 W 15 V MJD44H11 or D44VH10 4.5 W 2.5 W MJD45H11 or D45VH10 100 pF

VEE-L DESAT VCC2 VC VOUT VEE-L VEE-P

Figure 72. Current Buffer for Increased Drive Current Spacer

REVISION HISTORY
Changes from Original (September 2011) to Revision A Page

Changed the device From: Product Preview To: Production ................................................................................................ 1

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Aug-2012

PACKAGING INFORMATION
Orderable Device ISO5500DW ISO5500DWR Status
(1)

Package Type Package Drawing SOIC SOIC DW DW

Pins 16 16

Package Qty 40 2000

Eco Plan

(2)

Lead/ Ball Finish

MSL Peak Temp

(3)

Samples (Requires Login)

ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC DW 16

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 10.75

B0 (mm) 10.7

K0 (mm) 2.7

P1 (mm) 12.0

W Pin1 (mm) Quadrant 16.0 Q1

ISO5500DWR

2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Aug-2012

*All dimensions are nominal

Device ISO5500DWR

Package Type SOIC

Package Drawing DW

Pins 16

SPQ 2000

Length (mm) 367.0

Width (mm) 367.0

Height (mm) 38.0

Pack Materials-Page 2

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