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CS/APR2010/ITT430

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE EXAMINATION TIME

MICROPROCESSOR ITT430 APRIL 2010 3 HOURS

INSTRUCTIONS TO CANDIDATES The question paper consists of three (3) parts PART A (25 Questions) PART B (25 Questions) PART C (6 Questions)

Answer ALL questions from all three (3) parts. ) Answer Part A in the Objective Answer Sheet ) Answer Part B in the True / False Answer Sheet ) Answer Part C in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: the Question Paper an Answer Booklet - provided by the Faculty a True / False Answer Sheet - provided by the Faculty iv) an Objective Answer Sheet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

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PART A (25 MARKS) For each of the following questions, choose ONE (1) suitable answer and mark the answer on the Objective Answer Sheet provided.

1.

If the ASCII representation for character " f is 66H, what is the ASCII representation for character "t" ? A. B. C. D. 72H 73H 74H 75H

2.

The content of AH register to invoke the interrupt 21H so that it display a string of data to the screen is A. B. C. D. (AH)=03H (AH)=05H (AH)=07H (AH)=09H

3.

What is the duration of the bus cycle in the 8088-based microcomputer if the clock is 8 MHz and two wait states are inserted?

A. B. C. D.
4.

500 625 750 875

ns ns ns ns

The bus activity when the bus status code S2S1S0 equals 011 is A. B. C. D. read I/O port write I/O port halt instruction fetch

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5.

The timing properties defined for the read cycle of an EPROM will be I II III A. B. C. D. access time (tACc) chip-enable time (tCE) chip-deselect time (tDF) I I, II II, III I, II, III

6.

In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the address put on the bus during an output bus cycle is 800A16, the output port that the data will be written to will be A. B. C. D. Port 0 Port 2 Port 4 None of the above

7.

The flag tested for the loop instruction LOOPE is A. B. C. D. CF SF OF ZF

8.

The content of DX after executing the following instructions in the

DEBUG

trace is

MOV DX, 7676H MOV CL, 4 STC RCL DX, CL

A. B. C. D.

6763H 676BH 6767H 0767H

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9.

The following statements are all true EXCEPT A. B. C. D. I/O data transfers in the 8088 and 8086 microcomputers can be either bytewide or word-wide. In 8088 microcomputer, the word transfer is performed as two consecutive byte-wide data transfer and takes two bus cycles. In 8086 microcomputer, the word transfer takes one bus cycle. Word-wide I/O should be aligned at even-address boundaries.

10.

The status flags will be shown after executing the following instructions in the trace is .
MOV CMP ADD CMP AL, AL, AL, AL, -5 -9 7 -2

DEBUG

A. B. C. D.

NV NV NV NV

UP UP UP UP

DI DI DI DI

PL PL NG PL

NZ NZ ZR ZR

AC NA AC NA

PO PE PE PO

CY NC CY CY

11.

The key differences between NMI and the other external hardware initiated interrupts are _. I II III
A. B. C.

NMI is masked out by IF NMI is initiated from the NMI input lead instead of from the INTR input. NMI input is edge-triggered instead of level sensitive.
I, II I, III II, III

D.

I, II, III

12.

The number of bytes required to encode the instruction "MOV 1234H" is A. B. 3 bytes 4 bytes

[ D I ] + 123H,

C.
D.

5 bytes
6 bytes

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13.

The following statements are all true EXCEPT A. B. C. D. The read bus cycle begins with state J,. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start ofT,. Status bits S3 through S6 are output on the upper four address bus lines Ai 6 through A-,9 at the beginning of T2. Signal RD is switched to logic 1 at the later part of T2.

14.

The following statements are all true EXCEPT A. B. C. D. If an external device wants to take control of the system bus, it signals this fact to the MPU by switching HOLD to logic 1. In the hold state, signal lines AD0 through AD7 will be switched to logic 1. Other signal lines such as SSO, IO/M, DT/R, DEN and INTR are all put into high-Z state during the hold state. The 8088 signals external devices that the signal lines are in the high-Z state by switch its HLDA output to logic 1.

15.

If the content of (SP)=FF2EH, (AX)=3291H, (BX)=F43CH, and (CX)=09H. What is the content of the stack pointer after the execution of the following instructions? PUSH AX POP BX PUSH CX POP DX A. B. C. D. FF2EH FF2CH FF2AH FF28H

16.

What value must be written to the control register of the 82C55A to configure the device such that port A and port B are configured as output ports and port C is set up as input port in mode 0 operation ? A. 88H

B. C. D.

89H C8H C9H

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17.

This program is known as a delay program. In this program, the " J N Z instruction is executed for
MOV CX, 100H DEC CX NOP LOOP DLY

DLY"

DLY:

NXT:

A. B. C. D.
18.

128 255 256 277

times times times times

The content of AX after executing the following sequence of instructions is

MOV AH, FF MOV AL, F7 MOV BL, 2 IDIV BL A. B. C. D. (AX)=FFFAH (AX)=FFFBH (AX)=FFFCH (AX)=FFFDH

19.

The following statements are all true EXCEPT A. B. C. D. The maximum-mode configuration is mainly used for implementing a multiprocessor/coprocessor system environment. In the maximum-mode, 8088/8086 outputs a status code on three signal line S0, ST and S2 prior to the initialization of each bus cycle. The 3-bit bus status code identifies which type of bus cycle is to follow and are input to the external bus controller device, 8288. The 8088 produces one command signals for each bus cycle.

20.

When the instruction POP CX is executed, the address bus status code and memory bus cycle code output by the 8088 in a maximum mode microcomputer system are

A. B. C. D.

S4S3=01 andS2S1S0=101 S4S3=01 andS2S1S0=110 S4S3=10 and S2S1S0=101 S4S3=10 and S2S1S0=110

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CONFIDENTIAL 21.

CS/APR2010/ITT430

In the maximum-mode I/O interface of 8088 system, the logic levels of IORC, IOWC, and AIOWC during an output bus cycle are . A. B. C. D. IORC= IORC= IORC= IORC= 1, IOWC=0, and 1, IOWC=0, and 0, IOWC=1, and 0, IOWC=1, and AIOWC=0 AIOWC=0 AIOWC=1 AIOWC=1

22.

The address of the vector 47, CS47 and IP47 stored in the interrupt vector table is

A. B. C. D.

CS47=BCH CS47=BEH CS47=BCH CS47=BAH

and and and and

IP47=BEH IP47=BCH IP47=BAH IP47=BCH

23.

The following statements are all true EXCEPT A. B. C. D. The read bus cycle begins with state Ti. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start ofTi. Status bits S3 through S6 are output on the upper four address bus lines A16 through A19 at the beginning of T2. Signal RD is switched to logic 1 at the later part of T2.

24.

When the MPU recognizes the RESET input, it initiates its internal initialization routine and flags are all cleared. As a result of this process, the content of the CS register is .

A. B. C. D.
25.

0000H 00FFH FF00H FFFFH

The 8255A PPI has three 8-bit ports for implementing inputs or outputs. The I/O addresses where the ports PA, PB, and PC reside are . A. B. C. D. 005016, 005116, and0052 16 006016, 006116, and0062 16 007016, 007116, and0072 16 008016, 008116, and0082 16

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PART B (25 MARKS)

For each of the following questions, answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided.

1.

Pointer and index registers can be accessed either as a whole 16 bits for word data operations or as two 8-bit registers for byte-wide data operations. RET instruction will return execution to the main program by restoring IP and CS registers. CMP instruction alters the contents of it operands and status flags of the 8086/8066. An internal clock synchronises computer operations. When direct memory access (DMA) is working, the CPU is working too. In based addressing mode, the effective address is obtained from the contents of a base register and a displacement. In a LOOPZ instruction, the instruction will jump to the label if CX is not equal to zero and zero flag is set. All registers within the 8088/8086 microprocessor is located at the Execution Unit (EU). The SS and CS registers have their contents changed during the intrasegment jump. The reserved memory which are saved for the storage of the pointers that are used for the 8088's user-defined interrupts are located at 00014 16 - 0007F16. SRAM is normally used in application that requires a large amount of memory. The name given to the part of the I/O address space from 0000i6 through 00FFi6 is Page 0. The maximum number of repeats that can be implemented with a loop instruction is 65535. The interrupt function service routine specified by CS5:IP5 is overflow routine. A UART can be programmed to operate in "polled mode" or in "interrupt-driven" mode. When the I/O address on the bus is 800616, port 2 of the sixty-four-line parallel input circuit of an 8088-based microcomputer is selected.

2.

3. 4. 5. 6.

7.

8.

9. 10.

11. 12.

13.

14. 15.

16.

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17.

When the memory address on the bus is 0040216, Port B on PPI 0 is selected for memory-mapped 82C55A parallel I/O port in an 8088-based microcomputer. When a peripheral device wants to perform DMA operations, it makes a request for service at its DREQ input by switching it to logic 0. The storage array in the bulk-erase device is a single block, whereas the memory array in both the boot block and FlashFile is organized as multiple independently erasable blocks. In an 8086-based microcomputer system, the logic levels of Ao and BHE when a byte of data being written to I/O address 400216 is 0 and 1 respectively. If the contents of registers AL and BL are -1 and 4 respectively, then the content of AX is FFFCH after executing the instruction " I M U L BL". C416 is the control word of the 82C55A to configure the device such that port A is configured for bi-directional operation and port B is set up for mode 0 output operation. In a maximum mode system, 8288 device produces the input, output, and bus control signals for the I/O interface. If (AX)=8FFFH, the new contents of AX and DX are 8FFFH and FFFFH respectively after executing the instruction "CWD". A read bus cycle will have six clock states when it has two wait cycles.

18.

19.

20.

21.

22.

23.

24.

25.

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CONFIDENTIAL PART C (50 MARKS)

10

CS/APR2010/ITT430

Answer ALL questions.

QUESTION 1

Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. Assume that the opcode for the MOV, ADD and LEA operations are 100010, 000000 and 10001101 respectively.
a) MOV AX, [BP][SI] + 194H

(2 marks)
b) ADD [ D I ] , AX

(2 marks)
C) LEA D I , [SI + BX + 5H]

(2 marks) Table 1: Register Field Encoding REG 000 001 010 011 100 101 110 111

w=o
AL CL DL BL AH CH DH BH

W=1 AX CX DX BX SP BP SI DI

Table 2: Register/Memory Encoding Field MOD=1 1 R/M w=o 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH EFFECTIVE ADDRESS CALCULATIO N MOD=10 MOD=01 R/M MOD=00 (BX)+(SI)+D16 (BX)+(SI)+D8 000 (BX)+(SI) 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 010 (BP)+(SI)+D8 (BP)+(SI)+D16 (BP)+(SI) 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 100 (SI) (Sl)+D8 (Sl)+D16 101 (Dl)+D8 (Dl)+D16 (DI) 110 Dir. address (BP)+D8 (BP)+D16 (BX)+D16 111 (BX) (BX)+D8

W=1 AX CX DX BX SP BP SI DI

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CS/APR2010/ITT430

QUESTION 2

a)

Name and state TWO (2) functions of the internal processing units of 8088/8086 microprocessor. (3 marks) Name THREE (3) elements that belong to the above internal processing units. (3 marks) Define the signal applied to configure the 8088 microprocessor to work in minimummode and maximum-mode system. State the type of system and the number of microprocessor offered in both configurations. (3 marks)

b)

c)

QUESTION 3 Determine whether the following instructions can be executed by the 8086/8088 and state the reason.
a) SUB [ D I ] , 1234H;

(2 marks)
b) MOV DS, 1234H;

(2 marks)
C) IN BL, AL;

(2 marks) d) XCHG [ D I ] , [SI]; (2 marks) QUESTION 4 a) Define a bus cycle of the 8086/8088 microprocessor. Give the minimum clock period for a bus cycle required by 8086/8088 microprocessor. (2 marks) Define the bus cycle of the 8086/8088 microprocessor for a read cycle. (3 marks) c) Define the bus cycle of the 8086/8088 microprocessor for write cycle. (3 marks)
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b)

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CS/APR2010/ITT430

QUESTION 5 A memory-mapped 82C55A parallel I/O interface resides in the 1 Mbyte memory of the 8088 microprocessor. a) Determine the memory address of the control register for PPI4. (1 mark) b) Determine the control byte so that Port A is an input port, ports B and C are input ports and all three ports are configured for mode 0 operation. (1 mark) Determine the addresses of the three I/O ports on PPI4. (3 marks) QUESTION 6

c)

a)

Determine whether or not the jump will occur at the end of the following sets of instructions. Shows the final content of AL register. i) MOV XOR SHL JZ CL, 8 AL, AL AL, CL TARGET (2 marks) MOV MOV OR SHL JC BH, 65H AL, 1111 AL, BH AL, 1 TARGET (2 marks) iii) MOV SUB OR MOV AND SHR JNC AL, 27H DL, DL AL, DL CL, AH CL, OFH AL, CL TARGET (2 marks)

b)

Develop a program to COUNT the data byte in memory that equal to 43H starting at memory location 1000H through 1050H. Place the OUTPUT in BX register. (8 marks) END OF QUESTION PAPER

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