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MEDC-104 Vlsi Design Dec-2010

This document contains an exam for a VLSI design course. It includes 8 questions on various topics related to VLSI design. The questions cover topics such as threshold voltage calculation, CMOS fabrication processes, power dissipation, transistor sizing, noise margins, yield, FPGA architecture, logic families such as pass transistor logic and dynamic logic, data path operations, adder design, and concepts like MOS capacitors and logic gate design. Students are instructed to attempt any 5 of the 8 questions in the exam.

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Prakash Sinha
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255 views2 pages

MEDC-104 Vlsi Design Dec-2010

This document contains an exam for a VLSI design course. It includes 8 questions on various topics related to VLSI design. The questions cover topics such as threshold voltage calculation, CMOS fabrication processes, power dissipation, transistor sizing, noise margins, yield, FPGA architecture, logic families such as pass transistor logic and dynamic logic, data path operations, adder design, and concepts like MOS capacitors and logic gate design. Students are instructed to attempt any 5 of the 8 questions in the exam.

Uploaded by

Prakash Sinha
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal

MEDC-104 M.E./M.Tech. (First Semester) EXAMINATION, Dec 2010


(Grading/Non-Grading)

VLSI DESIGN
Time: Three Hours Maximum Marks: GS:70 Note: Attempt any five questions.

1. (a) Obtain the nMOS enhancement transistor threshold voltage equation. (b) Calculate native threshold voltage for a n-transistor at 3000K for a process with a Si substrate with NA = 1.5 1016 cm-3, a SiO2 gate oxide with thickness 200 . { Assume ms (work function) = - 0.9, fc = 0 }. 2. (a) What are the various processes of fabrication of CMOS? Explain any one of them with neat diagram. (b) Explain the following:
i. ii. Oxidation Ion implantation in brief

3. (a) Explain various power dissipations in a CMOS circuit.

(b) What is Transistor Sizing? Explain with examples. 4. (a) Explain noise margin of an invertor circuit with suitable diagram and expression. (b) Explain what is yield in the manufacture of VLSI structures. How do the various parameters affect it? 5. (a) Draw the architecture of field programmable gate arrays (FPGAs) and explain the following: i. Programmable interconnects ii. IOBs iii. CLBs (b) Give the applications of FPGAs. 6. (a) Explain the following: i. Pass Transistor Logic ii. Dynamic Logic iii. Pseudo-nMOS Logic 7. (a) Explain the data path operations in CMOS sub-system design. (b) Design a 32 bit parallel adder optimized for speed, single cycle operation and regularity of layout.

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Prakash Sinha

Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal

8. Write short notes on any three of the following: i. MOS capacitor ii. Sea of gates iii. FSM iv. Network Isomorphism v. NAND and NOR logic gate design using CMOS

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Prakash Sinha

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