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Fpga

This document discusses different Xilinx FPGA series including the XC3000, XC4000, and XC5000. It provides details on the structure of configurable logic blocks and how they are interconnected within each series. Specifically, it describes the 32-bit lookup tables and configurations available in the XC3000 CLB and improvements made in the XC4000 like adding two flip-flops and RAM per CLB along with more efficient interconnects. An example design is also implemented on the FPGA to demonstrate its usage.

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Priya Darshini
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142 views

Fpga

This document discusses different Xilinx FPGA series including the XC3000, XC4000, and XC5000. It provides details on the structure of configurable logic blocks and how they are interconnected within each series. Specifically, it describes the 32-bit lookup tables and configurations available in the XC3000 CLB and improvements made in the XC4000 like adding two flip-flops and RAM per CLB along with more efficient interconnects. An example design is also implemented on the FPGA to demonstrate its usage.

Uploaded by

Priya Darshini
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System Design Lecture 8: Xilinx FPGAs

Amir Masoud Gharehbaghi [email protected]

Table of Contents
Introduction Xilinx FPGAs
XC3000 XC4000 XC5000 New series

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Introduction
The largest manufacturer of SRAMbased FPGAs Main Families:
XC2000 XC3000 XC4000 XC5000

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Xilinx Series Comparison


I/O CLBs FFs Blocks XC2000 58-74 64-100 122174 XC3000 64-176 64-484 2561,320 XC4000 64-256 642561,024 2,569 XC5000 148196784244 484 1,936
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Series

Gate Count 8001,800 1,3009,000 1,60025,000 600015000


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Xilinx FPGA Structure


Fixed array of Configurabe Logic Blocks (CLBs) connectable by a system of passtransistors, driven by SRAM cells

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XC3000 CLB
32-bit (5-input) look-up table CLB propagation delay is fixed (LUT access time) and independent of the logic function 7 inputs to the XC3000 CLB:
5 CLB inputs (AE) 2 FF outputs (QX and QY)

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XC3000 CLB Configurations


Use 5 (of 7) inputs with the entire 32bit LUT (CLB outputs F and G are then identical) Split the 32-bit LUT in half to implement 2 functions (F and G) of 4 variables each; choose 4 inputs (from 7) Split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that switches between F and G (to implement some functions of 6 and 7 variables)

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Methods of Interconnection
Direct interconnect: Adjacent CLBs are wired together in the horizontal or vertical direction. The most efficient interconnect (< 1 ns delay) General-purpose interconnect: used mainly for longer connections or for signals with a moderate fan-out
Few, so problem in fitting a large design into XC3000, and 2000

Long line interconnect: for time critical signals (e.g. clock signal need be distributed to many CLBs)

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Design Example
Q2* = Q2 Q1 + Q2 Q0 Q1* = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0 Q0* = Q0 Z = X Q1 + X Q1

Functions have maximum 4 variables


4 LUT of 4 variables 3 FFs 2 CLB required

FPGA Implementation
Q2*, Q0* in one CLB Q1*, Z in one CLB

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Design Example Implementation

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Xilinx 4000 Series

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Xilinx 4000 Specs


Two FF per CLB + Two per I/O cell 25 gates per CLB for logic 32 bits of RAM per CLB Special fast carry logic between CLBs Interconnects:
Direct and general-purpose wires replaced with more efficient single-length and double-length lines. Sufficient resources for most applications.

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Xilinx 4000 CLB

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CLB Function Generators


Use RAM for truth tables
F, G: 4 input -> 16 bits of RAM (each) H: 3 input > 8 bits of RAM RAM is loaded at system initialization from external PROM

MUX control logic maps 4 control inputs into 4 inputs:


LUT input H1 Direct In (DIN) Enable Clock (EC) Set/Reset control (S/R) for FFs Control F,G LUTs as 32 bit SRAM

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CLB Function Generators (cont.)


Broad capability:
Any 2 functions of 4 variables plus a function of 3 variables Any function of 5 variables Any function of 4 variables plus some functions of 6 variables Some functions of 9 variables
Parity 4-bit cascadable equality checking

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CLB input and output connections

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Programmable Switch Matrix

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XC5200 Logic Block


Similar to CLBs in XC2000/3000 /4000, but simpler A group of 4 Logic Cells (LCs) is a CLB in XC5200 LC contains 4-input LUT
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State-of-the-art FPGAs
XCS00/XL (Spartan)
5v, 3v 2,000-40,000 typical gate

XC2S00/XL (Spartan-II)
2.5v 6,000-150,000 typical gate

XCV00 (Virtex)
2.5v 34,000-1,124,000 typical gate
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State-of-the-art FPGAs (cont.)


1999: Virtex-E 2000: Virtex-II 2002: Vitex-II Pro
125,136 logic cell 10 Mb RAM 556 18*18 Multiplier Up to 4 PowerPC 405 cores
300 MHz+, 420 MIPS

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