Name seed fetch:ifqsize fetch:mplat bpred bpred:bimod bpred:2lev ll1size bpred:2lev l2size bpred:2lev hist_size decode:width issue:width issue:inorder

issue:wrongpath ruu:size lsq:size cache:dl1 cache:dl1 cache:dl1 cache:dl1 cache:dl1lat cache:dl2 cache:dl2 cache:dl2 cache:dl2 cache:dl2lat cache:il1 cache:il1 cache:il1 cache:il1 cache:il1lat cache:il2 cache:il2 cache:il2 cache:il2 cache:il2lat cache:flush cache:icompress mem:lat mem:lat mem:width tlb:itlb tlb:itlb tlb:itlb

Value

Description 1 Random number generator

4 Instruction fetch queue size 2lev

3 extra branch mis-perdiction latency branch predictor type (nottaken|taken|perfect|bimod|2lev) 0 Bimodal predictor 16 2-level predictor config l1size param 256 2-level predictor config l2size param 8 2-level predictor config hist_size param 4 instruction decode B/W (insts/cycle) 4 instruction issue B/W (insts/cycle) run pipeline with in-order issue issue instruction down wrong execution paths 32 register update unit (RUU) size 16 load/store queue (LSQ) size 64 l1 data cache config 32 l1 data cache config 4 l1 data cache config l1 data cache config 2 l1 data cache hit latency (in cycles) 2048 l2 data cache config 64 l2 data cache config 8 l2 data cache config l2 data cache config 5 l2 data cache hit latency (in cycles) 128 l1 inst cache config 32 l1 inst cache config 2 l1 inst cache config l1 inst cache config 1 l1 inst cache hit latency (in cycles) l2 inst cache config l2 inst cache config l2 inst cache config l2 inst cache config 5 l2 inst cache hit latency (in cycles) flush caches on system calls convert 64-bit inst address to 32-bit inst equivalence 100 memory latency first_chunk 20 memory latency inter_chunk 8 memory access bus width (in byte) 16 instruction TLB config 4096 instruction TLB config 4 instruction TLB config

false true

f
dl2

false false

tlb:itlb tlb:dtlb tlb:dtlb tlb:dtlb tlb:dtlb tlb:lat res:ialu res:imult res:memport res:fpalu res:fpmult bugcompat Branch Target Buffer (BTB)

false

instruction TLB config 32 data TLB config 4096 data TLB config 4 data TLB config data TLB config 100 inst/data TLB miss latancy 2 total number of integer ALUs available 1 total number of integer multiplier/dividers available 2 total number of memory system ports available (to CPU) 2 total number of floating point ALUs available 1 total number of floating point multiplier/dividers available operate in backward-compatible bugs mode (for testing only)

256 the total number of entries in BTB

Comment ignored for complexity estimation fetch band width ignored for complexity estimation select the type of the branch prediction. At 2lev not specified if Pag or Pap number of bimodal predictor entries size of the 1st level table size of the 2nd level table pattern width in bits decode band width issue band width ignored for complexity estimation ignored for complexity estimation number of entries in the Register Update Unit number of entries in the Load Store Queue (LSQ) number of sets byte per line associativity replacement strategy (only LRU implemented) latency is ignored for complexity estimation number of sets byte per line associativity replacement strategy (only LRU implemented) latency is ignored for complexity estimation number of sets byte per line associativity replacement strategy (only lru implemented) latency is ignored for complexity estimation number of sets byte per line associativity replacement strategy (only lru implemented) latency is ignored for complexity estimation ignored for complexity estimation ignored for complexity estimation ignored for complexity estimation ignored for complexity estimation ignored for complexity estimation number of lines system page size associativity

replacement strategy (only lru implemented) number of lines system page size associativity replacement strategy (only lru implemented) ignored for complexity estimation number of simple integer units number of complex integer units number of memory ports number of simple floating point units number of complex floation point units ignored for complexity estimation

Width 1 2 4 8

MIPS 1073.98 1251.5 1315.28 1175.67

CC1 TEST BENCH-MIPS vs

1400 1200 1000 800 600 400 200 0 0 1 2 3 4 5

WIDTH 1 2 4 8

MIPS MIPS2 1525.92 1073.98 1958.46 1251.5 2255.53 1315.28 2073 1175.67

Equake Test BENCH-MIPS

2500 2000 1500 1000 500 0 0 MIPS MIPS2

width 1 2 4

AREA ### ### ###

43500000000 43000000000

AREA vs Machine

###
43500000000 43000000000 42500000000 42000000000 41500000000 41000000000 40500000000 40000000000 0

AREA vs Machine

width 1 2 4 8

TRANSISTOR 89736311 89907750 90250628 90936348

TRANSISTOR vs Mac
91500000 91000000 90500000 90000000 89500000 89000000

NCH-MIPS vs MACHINE WIDTH

Equake Test BENCH-MIPS vs Machin ENCH-MIPS vs Machine Widths

2500 2000 1500 1000 500 0 0 MIPS MIPS2

REA vs Machine Widths

REA vs Machine Widths

STOR vs Machine Widths

S vs Machine Widths

Parameter Register Floating point registers Integer registers Bits Address Floating Point register Integer register Word Program counter Transistors Read Port Write Port SRAM-Bit Fetch unit Decode unit Issue unit Write back logic Commit logic Integer ALU Integer MUL Floating point ALU Floating point MUL Load store unit Sizes of Units in square lambda Fetch unit Decode unit (dispatch) Issue unit (scheduler logic) Write back logic Commit logic Integer ALU Integer MUL Floating point ALU Floating point MUL Load store unit Register cell width Register cell height Wire track width Transistor Density Transistor density of logic Transistor density of HP-PA8000 Transistor density of Sparc64

Value

32 32

32 32 32 32 32

1 2 4 19,893 18,363 24,484 12,242 13,466 46,513 93,026 61,211 107,118 91,816

32,500,000 30,000,000 40,000,000 20,000,000 22,000,000 75,988,500 151,977,000 100,000,000 175,000,000 150,000,000 32 24 8

0.0006121050 0.0005209000 0.0007033100

Formula

Fixed Value Fixed Value

Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value

Fixed Value Fixed Value Fixed Value FUBasicSizeInLam * LogTransDens DecUBasicSizeInLam * LogTransDens IssUBasicSizeInLam * LogTransDens WbBasicSizeInLam * LogTransDens CmtUBasicSizeInLam * LogTransDens IntUSizeInLam * LogTransDens CpxIntUSizeInLam * LogTransDens FpUSizeInLam * LogTransDens CpxFpUSizeInLam * LogTransDens LsUBasicSizeInLam * LogTransDens

Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value Fixed Value

(HP8000LogTransDens + Sparc64LogTransDens) / 2 Fixed Value Fixed Value

Description

number of floating point registers number of integer registers

Simple Scalar architecture Simple Scalar architecture Simple Scalar architecture Simple Scalar architecture Simple Scalar architecture

number of transistors per read port number of transistors per write port number of transistors per basic SRAM cell number of transistors of a basic fetch unit number of transistors of a basic decode unit number of transistors of a basic issue unit number of transistors of the write back logic number of transistors of the commit logic number of transistors of a basic simple integer ALU number of transistors of a basic complex integer ALU number of transistors of a basic simple floating point ALU number of transistors of a basic complex floating point ALU number of transistors of a basic load store unit

basic size of the fetch unit logic in lambda (measured of PowerPC604) basic size of the decode unit logic in lambda (measured of PowerPC604) basic size of the issue unit logic in lambda (measured of PowerPC604) basic size of the write back logic in lambda (measured of PowerPC604) basic size of the completion logic in lambda (measured of PowerPC604) basic size of a simple integer ALU in lambda (measured of PowerPC604) basic size of a complex integer ALU in lambda (measured of PowerPC604) basic size of a simple floating point unit in lambda (measured of PowerPC604) basic size of a complex floating point ALU in lambda (measured of PowerPC604) basic size of the load store unit logic in lambda (measured of PowerPC604) width of a register cell without ports (depending on the technology / insert value for asumed tech.) height of a register cell without ports (depending on the technology / insert value for asumed tech.) assumption of a wire track width (depending on the technology / insert value for asumed tech.)

Average of the HP-PA8000 and SPARC64 Measured from floor plan Measured from floor plan

Unit Branch Prediction BTB read ports BTB write ports Register Floating point register read ports Floating point register write ports Integer register read ports Integer register write ports LSQ LSQ read ports LSQ write ports RUU RUU read ports RUU write ports TLBs I-TLB read ports I-TLB write ports D-TLB read ports D-TLB write ports Cache Level 1 i-cache read ports Level 1 i-cache write ports Level 1 d-cache read ports Level 1 d-cache write ports Level 2 i-cache read ports Level 2 i-cache write ports Level 2 d-cache read ports Level 2 d-cache write ports

Ports

4 4

8 4 10 4

8 8

14 10

1 1 2 2

1 1 2 2 #DIV/0! #DIV/0! 2 2

Formula

FWid FWid

(NuFpAlu + NuFpMul) * 2 + NuMemPort FWid (NuIntAlu + NuIntMul) * 2 + NuMemPort * 2 FWid

NuMemPort * 2 + FWid NuMemPort + NuIntAlu + NuIntMul + NuFpAlu + NuFpMul

NuIntAlu + NuIntMul + NuFpAlu + NuFpMul + IssWid + FWid NuIntAlu + NuIntMul + NuFpAlu + NuFpMul + DecWid

ROUNDUP(FWid * 4 / Lev1ICacheBytePerLn,0) ROUNDUP(FWid * 4 / Lev1ICacheBytePerLn,0) NuMemPort NuMemPort

ROUNDUP(FWid * 4 / Lev1ICacheBytePerLn,0) ROUNDUP(FWid * 4 / Lev1ICacheBytePerLn,0) NuMemPort NuMemPort ROUNDUP(FWid * 4 / Lev2ICacheBytePerLn,0) ROUNDUP(FWid * 4 / Lev2ICacheBytePerLn,0) NuMemPort NuMemPort

Unit Branch Prediction BTB bimodal Registers Floating point registers Integer registers Total register bits LSQ RUU identification bits LSQ entry bits LSQ total bits RUU Register identification bits Execution unit identification bits RUU Entry bits Total RUU bits

Bit

1,024 1,024 2,048

5 72 1,152

6 3 154 4,928

D-TLB D-TLB virtual page offset bits D-TLB index bits D-TLB address bits D-TLB tag bits D-TLB total bits I-TLB I-TLB virtual page offset bits I-TLB index bits I-TLB address bits I-TLB tag bits I-TLB total bits Level 1 d-cache Level 1 d-cache data bits Level 1 d-cache tag bits Level 1 d-cache offset bits Level 1 d-cache index bits Level 1 d-cache lru bits Level 1 d-cache total bits Level 1 i-cache Level 1 i-cache data bits Level 1 i-cache tag bits Level 1 i-cache offset bits Level 1 i-cache index bits Level 1 i-cache lru bits Level 1 i-cache total bits Level 2 d-cache Level 2 d-cache data bits Level 2 d-cache tag bits Level 2 d-cache offset bits

12 5 2,560 1,920 4,480

12 4 1,280 1,024 2,304

65,536 6,656 2 6 2 72,192

65,536 6,144 2 7 1 71,680

8,388,608 344,064 3

Level 2 d-cache index bits Level 2 d-cache lru bits Level 2 d-cache total bits Level 2 i-cache Level 2 i-cache data bits Level 2 i-cache tag bits Level 2 i-cache offset bits Level 2 i-cache index bits Level 2 i-cache lru bits Level 2 i-cache total bits Summary Integer registers Floating point register LSQ RUU D-TLB I-TLB Level 1 d-cache Level 1 i-cache Level 2 d-cache Level 2 i-cache

11 3 8,732,672

0 Err:502 Err:502 Err:502 Err:502 Err:502

1,024 1,024 1,152 4,928 4,480 2,304 72,192 71,680 8,732,672 Err:502

Formula

2 * NuBtbEnt

NuFpReg * BitPerFpReg NuIntReg * BitPerIntReg BitPerIntRegSet + BitPerFpRegSet

ROUNDUP(LOG(RuuEnt,2),0) BitPerRuuId + 3 + AddInBit + WordInBit BitPerLsqEnt * LsqEnt

ROUNDUP(LOG((NuIntReg + NuFpReg),2),0) ROUNDUP(LOG((NuIntAlu + NuIntMul + NuFpAlu + NuFpMul + NuMemPort),2),0) 3 * (BitPerRegId + WordInBit + 1) + BitPerPC + BitPerExUId + 2 RuuEnt * BitPerRuuEnt

LOG(DTlbBytePerPg,2) LOG(DTlbSet,2) (AddInBit-BitPerDTlbPgOff) * DTlbAss * DTlbSet (AddInBit - (BitPerDTlbPgOff + BitPerDTlbIdx)) * DTlbAss * DTlbSet BitOfDTlbAdd + BitOfDTlbTag

LOG(ITlbBytePerPg,2) LOG(ITlbSet,2) (AddInBit - BitPerITlbPgOff) * ITlbAss * ITlbSet (AddInBit - (BitPerITlbPgOff + BitPerITlbIdx)) * ITlbAss * ITlbSet BitOfITlbAdd + BitOfITlbTag

Lev1DCacheSet * Lev1DCacheBytePerLn * Lev1DCacheAss * 8 (AddInBit + BitPerLev1DCacheLru - (BitPerLev1DCacheIdx + BitPerLev1DCacheOff)) * Lev1DCacheSet * Lev1DCacheAs LOG(Lev1DCacheBytePerLn / 8,2) LOG(Lev1DCacheSet,2) ROUNDUP(LOG(Lev1DCacheAss,2),0) Lev1DCacheDataBit + Lev1DCacheTagBit

Lev1ICacheSet * Lev1ICacheBytePerLn * Lev1ICacheAss * 8 (AddInBit + BitPerLev1ICacheLru - (BitPerLev1ICacheIdx + BitPerLev1ICacheOff)) * Lev1ICacheSet * Lev1ICacheAss LOG(Lev1ICacheBytePerLn / 8,2) LOG(Lev1ICacheSet,2) ROUNDUP(LOG(Lev1ICacheAss,2),0) Lev1ICacheDataBit + Lev1ICacheTagBit

Lev2DCacheSet * Lev2DCacheBytePerLn * Lev2DCacheAss * 8 (AddInBit + BitPerLev2DCacheLru -(BitPerLev2DCacheIdx+BitPerLev2DCacheOff)) * Lev2DCacheSet * Lev2DCacheAss LOG(Lev2DCacheBytePerLn / 8,2)

LOG(Lev2DCacheSet,2) ROUNDUP(LOG(Lev2DCacheAss,2),0) Lev2DCacheDataBit + Lev2DCacheTagBit

Lev2ICacheSet * Lev2ICacheBytePerLn * Lev2ICacheAss * 8 (AddInBit + BitPerLev2ICacheLru - (BitPerLev2ICacheIdx + BitPerLev2ICacheOff)) * Lev2ICacheSet * Lev2ICacheAss LOG(Lev2ICacheBytePerLn / 8,2) LOG(Lev2ICacheSet,2) ROUNDUP(LOG(Lev2ICacheAss,2),0) Lev2ICacheDataBit + Lev2ICacheTagBit

BitPerIntRegSet BitPerFpRegSet BitPerLsq BitPerRuu BitPerDTlb BitPerITlb BitPerLev1DCache BitPerLev1ICache BitPerLev2DCache BitPerLev2ICache

Unit Branch Prediction BTB (bimodal predictor) Registers Floatingpoint registers Integer registers Total registers LSQ RUU TLBs I-TLB D-TLB Total tlbs Caches Level 1 i-cache data transistors Level 1 i-cache tag transistors Total level 1 i-cache transistors Level 1 d-cache data transistors Level 1 d-cache tag transistors Total level 1 d-cache transistors Level 2 i-cache data transistors Level 2 i-cache tag transistors Total level 2 i-cache transistors Level 2 d-cache data transistors Level 2 d-cache tag transistors Total level 2 d-cache transistors

Evaluated Value

20,480 22,528 43,008 32,256 187,264

16,128 44,800 60,928

458,752 43,008 501,760 655,360 66,560 721,920 #DIV/0! #DIV/0! #DIV/0! 83,886,080 3,440,640 87,326,720

Instruction fetch unit Instruction decode unit Issue unit Write back unit Commit unit Execution units Simple integer ALU Complex integer ALU Simple floating point ALU Complex floating point ALU Load Store units Total execution units

79,574 73,453 97,937 97,937 53,865

93,026 93,026 122,421 107,118 183,632 599,223

2 level Predictor 2lev predictor Branch Target Buffer BTB

10,240.0

176,128

Summary Registers LSQ RUU I-TLB D-TLB Level 1 i-cache Level 1 d-cache Level 2 i-cache Level 2 d-cache total transistor

43,008 32,256 187,264 16,128 44,800 501,760 721,920 #DIV/0! 87,326,720 90,062,212

Formula

BitPerBtb * (TransPerSRBit + TransPerWrtPort * BtbWrtPort + TransPerReadPort * BtbReadPort)

BitPerFpRegSet * (TransPerSRBit + TransPerWrtPort * FpRegWrtPort + TransPerReadPort*FpRegReadPort) BitPerIntRegSet * (TransPerSRBit + TransPerWrtPort * IntRegWrtPort + TransPerReadPort * IntRegReadPort) TransPerFpRegSet + TransPerIntRegSet BitPerLsq * (TransPerSRBit + TransPerWrtPort * LsqWrtPort + TransPerReadPort * LsqReadPort) BitPerRuu * (TransPerSRBit + TransPerWrtPort * RuuWrtPort + TransPerReadPort * RuuReadPort)

BitPerITlb * (TransPerSRBit + TransPerWrtPort * ITlbWrtPort + TransPerReadPort * ITlbReadPort) BitPerDTlb * (TransPerSRBit + TransPerWrtPort * DTlbWrtPort + TransPerReadPort * DTlbReadPort) TransITlb + TransDTlb

Lev1ICacheDataBit * (TransPerSRBit + TransPerWrtPort * Lev1ICacheWrtPort + TransPerReadPort * Lev1ICacheReadPo Lev1ICacheTagBit * (TransPerSRBit + TransPerWrtPort * Lev1ICacheWrtPort + TransPerReadPort * Lev1ICacheReadPo TransLev1ICacheData + TransLev1ICacheTag Lev1DCacheDataBit * (TransPerSRBit + TransPerWrtPort * Lev1DCacheWrtPort + TransPerReadPort * Lev1DCacheRea Lev1DCacheTagBit * (TransPerSRBit + TransPerWrtPort * Lev1DCacheWrtPort + TransPerReadPort * Lev1DCacheRead TransLev1DCacheData + TransLev1DCacheTag Lev2ICacheDataBit * (TransPerSRBit + TransPerWrtPort * Lev2ICacheWrtPort + TransPerReadPort * Lev2ICacheReadPo Lev2ICacheTagBit * (TransPerSRBit + TransPerWrtPort * Lev2ICacheWrtPort + TransPerReadPort * Lev2ICacheReadPo TransLev2ICacheData + TransLev2ICacheTag Lev2DCacheDataBit * (TransPerSRBit + TransPerWrtPort * Lev2DCacheWrtPort + TransPerReadPort * Lev2DCacheRea Lev2DCacheTagBit * (TransPerSRBit + TransPerWrtPort * Lev2DCacheWrtPort + TransPerReadPort * Lev2DCacheRead TransLev2DCacheData + TransLev2DCacheTag

FWid * TransPerBasicFU DecWid *TransPerBasicDecU IssWid * TransPerBasicIssU (NuIntAlu + NuIntMul + NuFpAlu + NuFpMul + NuMemPort) * TransPerBasicWbU TransPerBasicCmtU * FWid

NuIntAlu * TransPerBasicIntU NuIntMul * TransPerBasicCpxIntU NuFpAlu * TransPerBasicFpU NuFpMul * TransPerBasicCpxFpU TransPerBasicLSU * NuMemPort TransIntU + TransCpxIntU + TransFpU + TransCpxFpU + TransLSU

total bits * (TransPerSRBit + TransPerWrtPort * BtbWrtPort + TransPerReadPort * BtbReadPort)

BitPerBTB * (TransPerSRBit + TransPerWrtPort * BtbWrtPort + TransPerReadPort * BtbReadPort)

TransReg TransLsq TransRuu TransITlb TransDTlb TransLev1ICache TransLev1DCache TransLev2ICache TransLev2DCache

Unit

Area in

Bimodal Branch Predictor BTB cell height BTB cell width BTB area Register Integer register cell height Integer register cell width Integer register area Floating point register cell height Floating point register cell width Floating point register area Total register area LSQ LSQ cell height LSQ cell width LSQ area RUU RUU cell height RUU cell width RUU area TLBs ITLB ITLB cell heigth ITLB cell width ITLB area DTLB DTLB cell height DTLB cell width DTLB area Total TLB area Caches Level 1 i-cache Level 1 i-cache cell height Level 1 i-cache cell width Level 1 i-cache data area Level 1 i-cache tag area Total level 1 i-cache area Level 1 d-cache Level 1 d-cache cell height Level 1 d-cache cell width Level 1 d-cache data area Level 1 d-cache tag area Total level 1 d-cache area Level 2 i-cache Level 2 i-cache cell height

88.0 128.0 0.0

136.0 176.0 24,510,464.0 120.0 160.0 19,660,800.0 44,171,264.0

152.0 224.0 39,223,296.0

216.0 304.0 323,592,192.0

40.0 56.0 5,160,960.0 56.0 80.0 20,070,400.0 25,231,360.0

40.0 56.0 146,800,640.0 13,762,560.0 160,563,200.0

56.0 80.0 293,601,280.0 29,818,880.0 323,420,160.0

#DIV/0!

Level 2 i-cache cell width Level 2 i-cache data area Level 2 i-cache tag area Total level 2 i-cache area Level 2 d-cache Level 2 d-cache cell height Level 2 d-cache cell width Level 2 d-cache data area Level 2 d-cache tag area Total level 2 d-cache area

#DIV/0! #DIV/0! Err:502 #DIV/0!

56.0 80.0 37,580,963,840.0 1,541,406,720.0 39,122,370,560.0

Instruction fetch Instruction decode Issue unit Write back unit Commit unit

130,000,000.0 120,000,000.0 160,000,000.0 160,000,000.0 88,000,000.0

Execution units Integer ALU Integer multiplier Floating point ALU Floating point multipliers Load store unit Total execution units

151,977,000.0 151,977,000.0 200,000,000.0 175,000,000.0 300,000,000.0 978,954,000.0

2 level Predictor 2 level predictor cell height 2 level predictor cell width 2 level predictor area

88.0 128.0 3,604,480.0

Branch Target Buffer BTB cell height BTB cell width BTB area

88.0 2,752.0 61,997,056.0

Summary Instruction fetch Instruction decode BTB FUs TLBs Register Busses and control Latches Level 1 Cache Total

Err:508 Err:508 Err:508 Err:508 Err:508 Err:508 Err:508 Err:508 Err:508 41,741,127,568.0

Formula

SRCellBasicHghtInLam + (BtbReadPort + BtbWrtPort) *WtWidInLam SRCellBasicWidInLam + (BtbReadPort + 2 * BtbWrtPort) * WtWidInLam BitPerBtb * BtbCellHght * BtbCellWid

SRCellBasicHghtInLam + (IntRegReadPort + IntRegWrtPort) * WtWidInLam SRCellBasicWidInLam + (IntRegReadPort + 2 * IntRegWrtPort) * WtWidInLam BitPerIntRegSet * IntRegCellHght * IntRegCellWid SRCellBasicHghtInLam + (FpRegReadPort + FpRegWrtPort) * WtWidInLam SRCellBasicWidInLam + (FpRegReadPort + 2 * FpRegWrtPort) *WtWidInLam BitPerFpRegSet * FpRegCellWid * FpRegCellHght IntRegArea + FpRegArea

SRCellBasicHghtInLam + (LsqReadPort + LsqWrtPort) * WtWidInLam SRCellBasicWidInLam + (LsqReadPort + 2 * LsqWrtPort) * WtWidInLam BitPerLsq * LsqCellWid * LSQCellHght

SRCellBasicHghtInLam + (RuuReadPort + RuuWrtPort) * WtWidInLam SRCellBasicWidInLam + (RuuReadPort + 2 * RuuWrtPort) * WtWidInLam BitPerRuu * RuuCellHght * RuuCellWid

SRCellBasicHghtInLam + (ITlbReadPort + ITlbWrtPort) * WtWidInLam SRCellBasicWidInLam + (ITlbReadPort + 2 * ITlbWrtPort) * WtWidInLam BitPerITlb * ITlbCellWid * ITlbCellHght SRCellBasicHghtInLam + (DTlbReadPort + DTlbWrtPort) * WtWidInLam SRCellBasicWidInLam + (DTlbReadPort + 2 * DTlbWrtPort) * WtWidInLam BitPerDTlb * DTlbCellWid * DTlbCellHght ITlbArea + DTlbArea

SRCellBasicHghtInLam + (Lev1ICacheReadPort + Lev1ICacheWrtPort) * WtWidInLam SRCellBasicWidInLam + (Lev1ICacheReadPort + 2 * Lev1ICacheWrtPort) * WtWidInLam Lev1ICacheDataBit * Lev1ICacheCellHght * Lev1ICacheCellWid Lev1ICacheTagBit * Lev1ICacheCellHght * Lev1ICacheCellWid Lev1ICacheDataArea + Lev1ICacheTagArea

SRCellBasicHghtInLam + (Lev1DCacheReadPort + Lev1DCacheWrtPort) * WtWidInLam SRCellBasicWidInLam + (Lev1DCacheReadPort + 2 * Lev1DCacheWrtPort) * WtWidInLam Lev1DCacheDataBit * Lev1DCacheCellHght * Lev1DCacheCellWid Lev1DCacheTagBit * Lev1DCacheCellHght * Lev1DCacheCellWid Lev1DCacheDataArea + Lev1DCacheTagArea

SRCellBasicHghtInLam + (Lev2ICacheReadPort + Lev2ICacheWrtPort) * WtWidInLam

SRCellBasicWidInLam + (Lev2ICacheReadPort + 2 * Lev2ICacheWrtPort) * WtWidInLam Lev2ICacheDataBit * Lev2ICacheCellHght * Lev2ICacheCellWid Lev2ICacheTagBit * Lev2ICacheCellHght * Lev2ICacheCellWid Lev2ICacheDataArea + Lev2ICacheTagArea

SRCellBasicHghtInLam + (Lev2DCacheReadPort + Lev2DCacheWrtPort) * WtWidInLam SRCellBasicWidInLam + (Lev2DCacheReadPort + 2 * Lev2DCacheWrtPort) * WtWidInLam Lev2DCacheDataBit * Lev2DCacheCellHght * Lev2DCacheCellWid Lev2DCacheTagBit * Lev2DCacheCellHght * Lev2DCacheCellWid Lev2DCacheDataArea + Lev2DCacheTagArea

FWid * FUBasicSizeInLam DecWid * DecUBasicSizeInLam IssWid * IssUBasicSizeInLam (NuIntAlu+NuIntMul+NuFpAlu+NuFpMul+NuMemPort) * WbBasicSizeInLam FWid * CmtUBasicSizeInLam

NuIntAlu * IntUSizeInLam NuIntMul * CpxIntUSizeInLam NuFpAlu * FpUSizeInLam NuFpMul * CpxFpUSizeInLam NuMemPort * LsUBasicSizeInLam IntUArea + CpxIntUArea + FpUArea + CpxFpUArea + LSUArea

SRCellBasicHghtInLam + (BtbReadPort + BtbWrtPort) *WtWidInLam SRCellBasicWidInLam + (BtbReadPort + 2 * BtbWrtPort) * WtWidInLam (L2 size * cell height * cell width) + (L1 size * cell height * history_size/2 * cell width)

the same as that of Bimodal predictor 21.5 times to that of Bimodal predictor (43 address bits) BTB cell height * BTB cell width * BTB entries

IFAreaInRbe IDecAreaInRbe BimBpredBtbAreaInRbe TotFuAreaInRbe TotTlbAreaInRbe TotRegAreaInRbe (TotRegAreaInRbe + TotTlbAreaInRbe + TotFuAreaInRbe + IDecAreaInRbe + IFAreaInRbe + BimBpredBtbAreaInRbe) * ( (TotRegAreaInRbe + TotTlbAreaInRbe + TotFuAreaInRbe + IDecAreaInRbe + IFAreaInRbe + BimBpredBtbAreaInRbe) * ( TotLev1ICacheAreaInRbe + TotLev1DCacheAreaInRbe Total Area

Transistors Analytical estimated BTB Registers LSQ RUU TLBs Level 1 i-cache Level 1 d-cache Level 2 i-cache Level 2 d-cache Empirical estimated Fetch unit Decode unit (dispatch) Issue (scheduler) Write back unit Commit unit Integer units Floating point units Load strore units Summary Total without caches Total with l1 caches Total with all caches 79,574 73,453 97,937 97,937 53,865 93,026 122,421 183,632 0 43,008 32,256 187,264 60,928 501,760 721,920 #DIV/0! 87,326,720

M 2

0.00 44.17 39.22 323.59 25.23 160.56 323.42 #DIV/0! 39,122.37

130.00 120.00 160.00 160.00 88.00 303.95 375.00 300.00

1,125,299 2,348,979 #DIV/0!

2,069.17 2,553.16 #DIV/0!

Expression Access Address ALU And Area Associativity Base Basic Bimodal Bit Branch predictor BTB (Brach Target Buffer) Busese Byte Cache Cell Commit Control Data Decode Entry Equivalent Execution Fetch Floating Point Height History In Index Instruction Integer Issue Lambda Latches Level Lines Logic LSQ Multiplier Number Of Offset Page per Percent Port Processor rbe Read Register

Acronym Acc Add Alu And Area Ass Base Basic Bim Bit Bprd Btb Bus Byte Cache Cell Cmt Ctrl D Dec Ent Equi Ex F Fp Hght His In Idx I Int Iss Lam Ltch Lev Ln Lgc Lsq Mul Nu Of Off Pg Per Pct Port Proc Rbe Read Reg

RegisterRename SDRAM - bit Set Size Square lambda Square mm Strategy Tag TLB Total Transistor Type Unit Virtual Width

Ruu SDBit Set Size Lam2 Mm2 Strt Tag Tlb Tot Trans Type U Virt Wid