Parity Checker Example
A string of bits has even parity if the number of 1s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd:
Formal Design Process
EECS150 - Digital Design Lecture 9 - Finite State Machines 1
February 19, 2002 John Wawrzynek
Can you guess a circuit that performs this function?
State Transition Diagram
circuit is in one of two states. transition on each cycle with each new input over exactly one arc (edge). Output depends on which state the circuit is in.
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Formal Design Process
State Transition Table:
present next state OUT IN state EVEN EVEN ODD ODD 0 0 1 1 0 1 0 1 EVEN ODD ODD EVEN
Formal Design Process
Logic equations from table:
OUT = PS NS = PS xor IN
Finite State Machines (FSMs )
Type of sequential circuit :
output depends on present and past inputs effect of past inputs is represented by the current state
Circuit Diagram:
Review of Design Steps: 1. Circuit functional specification 2. State Transition Diagram 3. Symbolic State Transition Table 4. Encoded State Transition Table 5. Derive Logic Equations 6. Circuit Diagram
FFs for state CL for NS and OUT
Invent a code to represent states:
Let 0 = EVEN state, 1 = ODD state
present state (p s) 0 0 1 1
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ps Derive logic equations from table (how?):
OUT = PS NS = PS xor IN
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ns
OUT 0 0 1 1
IN 0 1 0 1
next state (ns) 0 1 1 0
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Behavior is represented by State Transition Diagram:
xor gate for ns calculation DFF to hold present state no logic needed for output
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traverse one edge per cycle.
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FSM Implementation
Combination Lock Example
Exam Friday
Announcements
5-8pm, lectures 1-8, closed book/notes
Review Session Tonight
8pm, Woz Lounge, Soda Hall
Interesting Seminar Tomorrow
"The Sight & Sound of Information - Defining the Future Beyond the PC" Brian Halla, CEO, National Semiconductor Corporation Used to allow entry to a locked room: FFs form state register number of FFs at most log2(number of states) CL implements calculates next state and output
2-bit serial combination. Example 01,11: 1. Set switches to 01, press ENTER 2. Set switches to 11, press ENTER 3. OPEN is asserted (OPEN=1). If wrong code, ERROR is asserted (after second combo word entry). Press Reset at anytime to try again.
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Combinational Lock STD
RESET 0 0 0 0 0 0 0 0 0 0 1
Symbolic State Transition Table
EN TE CO R M1 CO M PS 2 2 PS 1 PS 0 NS 2
Encoded ST Table
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ENTER 0 1 1 0 1 1 * 0 1 * *
COM1 COM2 Preset State * * START 0 * START 1 * START * * OK1 * 0 OK1 * 1 OK1 * * OK2 * * BAD1 * * BAD1 * * BAD2 * * *
Next State START BAD1 OK1 OK1 BAD2 OK2 OK2 BAD1 BAD2 BAD2 START
OPEN ERROR 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
NS 1 NS 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Assign states:
START=000, OK1=001, OK2=011 BAD1=100, BAD2=101
Omit reset. Assume that primitive flipflops has reset input. Rows not shown have dont cares in output. Correspond to invalid PS values.
ef ab = 10 10 11 10 00 10 11 10 0 0 01 11 ab = 01 10 11 10 0 0 01 11 ab = 00 10 11 10 00 10 ab = 00 10 11 10 00 00 10 ab = 01 10 11 10 0 0 01 11 10 ab = 00 10 11 10 00 00 0 0 01 11 10 ab = 11 10 11 10 0 0 01 11 10 ab = 01 10 11 10 0 0 01 11 10 00 00 cd 0 0 01 11
NS2 10
ab = 10 10
ef 00 10 11
cd
0 0 01 11
NS110
ab = 10 10
ef 00 10 11
cd
0 0 01 11
NS0
10
ab = 11
00
0 0 01 11
10 ab = 11 10 11 10
00
0 0 01 11
10
0 0 01 11
10
Decoder logic for checking combination (01,11):
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FSM Implementation Notes
General FSM form:
State Encoding
One-hot encoding of states. One FF per state.
One-hot encoded FSM
Even Parity Checker Circuit:
All examples so far generate output based only on the present state:
In general: # of possible state = 2# of FFs However, often more than log 2 (# of states) FFs are used, to simplify logic at the cost of more FFs. Extreme example is one -hot state encoding.
Commonly name Moore Machine
Simple design procedure. Circuit matches state transition diagram. Can be costly for FSMs with large number of states
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In General:
FFs must be initialized for correct operation (only one 1)
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One-hot encoded combination lock
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