EXP 6 Serial Adder
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ubuntu 13.04EXP 6 Serial Adder
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ubuntu 13.04K Electronic Engineering Department
Logic Circuits II LAB
Introduction/Preliminary work
EXPERIMENT 6: SERIAL ADDER
In this experiment we will realize a serial adder circuit which had been examined in class. It will be used two universal shift registers where two numbers to be added are stored by parallel loading. The resulting sum value will be shifted in one of the existing registers in order to save one register IC. In the serial adder design, there are one D FF, one EX-OR and two shift register ICs. Below given serial adder should be simulated on proteus before coming to LAB.
Procedure:
1.
Set up the below circuit on your breadboard.
15 14 13 12
Q0 Q1 Q2 Q3
U1
74194 SR SL CLK S0 S1 MR
U2A
1 3 2 2 74HC86 1
U2B
3
D0 D1 D2 D3
3 4 5 6
2 7 11 9 10 1
74HC86
U3:B
4 6 10 9 7400 3 2 15 14 13 12
U3:A
1
D CLK
2 3
U3:C
U4:A
Q 5
7400
Q0 Q1 Q2 Q3
U5
74194 SR SL CLK S0 S1 MR
7400
7474
3 4 5 6
D0 D1 D2 D3
2.
Do not forget power and ground connections. 3. Connect D FF preset input to 5V, and clear input to a switch in order to set the initial state. 4. The numbers to be added will be applied through parallel inputs of the shift registers by switches. 5. Shift registers clear and s0 control mode inputs should be connected to logic 1 (5V) while s1 mode input connected to a switch. 6. Shift registers and D FF outputs could be observed by LEDs. 7. Use a pulsar switch for central clock input. 8. D FF initial state (first carry bit) should be arranged as 0 by clear and preset inputs. Then these inputs should set to input accepted mode. In this mode D FF behaves as it is defined. 9. Addition procedures first step is to parallel load the numbers to the registers. This is done through the s0, s1 mode selection inputs as shown in the 74194 datasheet. 10. In the second step, parallel loaded numbers should be shifted right into the serial adder input by consequence four clock pulses. Before this process, registers should be in shift right mode (data sheet). 11. Serial adder sum output is connected to one of the registers serial in input. In order to observe the four bit sum result, consequent 4 clock pulses are applied in through pulsar switch. 12. Perform the below table additions on your circuit and record the results.
Components: Two 74194 Universal register, One 7474 D FF, One 7486 EX-OR, One 7400 NAND Updated: October 2009 Page 1
2 7 11 9 10 1
K Electronic Engineering Department
Logic Circuits II LAB
EXPERIMENT 6 REPORT: SERIAL ADDER
Date: Student Name: Surname
Session: Name: Surname
Group Name: Surname
Decimal added A 10 9 14 15
numbers
to B 4 7 13 15
be A in binary B in binary
A Shift register data
B Shift register data
D output
FF
Questions 1. Compare serial and parallel adders which have been designed to add two 4-bit binary numbers in terms of numbers of components and processing time? 2. What are limits of the input and output numbers bits for the circuit you realized. What causes this limitation? 3. What is the highest sum number you could observe in this adder? 4. Where could you see the most significant bit? 5. How could you use this adder for subtraction? 6. How can you increase your addition circuit capacity?
Updated: October 2009
Page 2
