Data Sheet

FEATURES
Digital IS interface with high precision 24-bit data High SNR of 61 dBA High sensitivity of 26 dBFS Flat frequency response from 60 Hz to 15 kHz Low current consumption of 1.4 mA High PSR of 75 dBFS Small 4.72 mm 3.76 mm 1 mm surface-mount package Compatible with Sn/Pb and Pb-free solder processes RoHS/WEEE compliant

Omnidirectional Microphone with Bottom Port and I2S Digital Output ADMP441
FUNCTIONAL BLOCK DIAGRAM
ADMP441
ADC FILTER I2S SERIAL PORT HARDWARE CONTROL SCK SD WS

POWER MANAGEMENT

GND

GND

GND

CHIPEN

VDD

L/R

Figure 1.

APPLICATIONS
Teleconferencing systems Gaming consoles Mobile devices Laptops Tablets Security systems

09568-001

BOTTOM

TOP

Figure 2. Isometric Views of ADMP441 Microphone Package

GENERAL DESCRIPTION
The ADMP4411 is a high performance, low power, digital output, omnidirectional MEMS microphone with a bottom port. The complete ADMP441 solution consists of a MEMS sensor, signal conditioning, an analog-to-digital converter, antialiasing filters, power management, and an industry standard 24-bit IS interface. The IS interface allows the ADMP441 to connect directly to digital processors, such as DSPs and microcontrollers, without the need for an audio codec in the system. The ADMP441 has a high SNR and high sensitivity, making it an excellent choice for far field applications. The ADMP441 has a flat wideband frequency response, resulting in natural sound with high intelligibility. The ADMP441 is available in a thin 4.72 mm 3.76 mm 1 mm surface-mount package. It is reflow solder compatible with no sensitivity degradation. The ADMP441 is halide free.

Protected by U.S. Patents 7,449,356; 7,825,484; 7,885,423; and 7,961,897. Other patents are pending.

Rev. B

Document Feedback One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 20112012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

09568-015

ADMP441 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 IS Digital Input/Output .............................................................. 4 Timing Diagram ........................................................................... 4 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8

Data Sheet
Understanding Sensitivity ............................................................8 Power Management.......................................................................8 Startup .............................................................................................8 IS Data Interface ..........................................................................8 Digital Filter Characteristics ..................................................... 10 Applications Information .............................................................. 11 Power Supply Decoupling ......................................................... 11 Handling Instructions................................................................ 11 Supporting Documentation ...................................................... 11 Layout and Design Recommendations........................................ 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13

REVISION HISTORY
10/12Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Pick-and-Place Equipment Section, Evaluation Board User Guide Section, Circuit Note Section, and Application Note Section ............................................................... 11 1/12Rev. 0 to Rev. A Changes to Circuit Note Title ....................................................... 11 Updated Outline Dimensions ....................................................... 13 Deleted Figure 18............................................................................ 13 10/11Revision 0: Initial Version

Rev. B | Page 2 of 16

Data Sheet SPECIFICATIONS

ADMP441

TA = 25C, VDD = 2.4 V, SCK = 3.072 MHz, SPL = 104 dB (3.16 Pa rms), unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. Table 1.
Parameter PERFORMANCE Directionality Sensitivity at 94 dB SPL 1 Signal-to-Noise Ratio Equivalent Input Noise Dynamic Range Frequency Response 2 Symbol Test Conditions/Comments Min Typ Omni 26 61 33 87 60 15 3/+2 75 120 87 1.8 3.3 Max Unit

SNR EIN

Total Harmonic Distortion Power Supply Rejection Maximum Acoustic Input Noise Floor POWER SUPPLY Supply Voltage Supply Current VDD = 1.8 V Normal Mode Standby Power-Down VDD = 3.3 V Normal Mode Standby Power-Down DIGITAL FILTER Group Delay

THD PSR

1 kHz, 104 dB SPL 20 kHz bandwidth, A-weighted 20 kHz bandwidth, A-weighted Derived from EIN and maximum acoustic input Low frequency 3 dB point High frequency 3 dB point Deviation limits from flat response within pass band 104 dB SPL 217 Hz, 100 mV p-p square wave superimposed on VDD Peak 20 Hz to 20 kHz, A-weighted, rms

29

23

dBFS dBA dBA SPL dB Hz kHz dB % dBFS dB SPL dBFS V

VDD IDD

1.4

1.6 0.8 2 2.5 0.8 4.5

mA mA A mA mA A sec s s dB dB kHz

2.2

fS = 48 kHz fS = 16 kHz Pass-Band Ripple Stop-Band Attenuation Pass Band

1

17.25/fS 359 1078 0.04 60 20.3

0.423 fS

The peak-to-peak amplitude is relative to peak-to-peak amplitude of 224 1. The stimulus is a 104 dB SPL sinusoid having rms amplitude of 3.1623 Pa. Sensitivity is relative to 1 Pa. 2 See Figure 6 and Figure 8.

Rev. B | Page 3 of 16

ADMP441
IS DIGITAL INPUT/OUTPUT
40C < TA < +85C, 1.8 V < VDD < 3.3 V, unless otherwise noted. Table 2.
Parameter DIGITAL INPUT Voltage Input Low (L/R, WS, SCK) Voltage Input High (L/R, WS, SCK) SD DIGITAL OUTPUT Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High
1

Data Sheet

Symbol VIL VIH VOL VOL VOH VOH VOL VOL VOH VOH

Test Conditions/Comments

Min 0 0.7 VDD

Limit 1 Max
0.25 VDD

Unit V V V V V V V V V V

VDD 0.1 VDD 0.3 VDD

VDD = 1.8 V, ISINK = 0.25 mA VDD = 1.8 V, ISINK = 0.7 mA VDD = 1.8 V, ISINK = 0.7 mA VDD = 1.8 V, ISINK = 0.25 mA VDD = 3.3 V, ISINK = 0.5 mA VDD = 3.3 V, ISINK = 1.7 mA VDD = 3.3 V, ISINK = 1.7 mA VDD = 3.3 V, ISINK = 0.5 mA

0.7 VDD 0.9 VDD 0.1 VDD 0.3 VDD 0.7 VDD 0.9 VDD

Limits based on characterization results; not production tested.

Table 3. Serial Data Port Timing Specifications

Parameter tSCH tSCL tSCP fSCK tWSS tWSH fWS Description SCK high SCK low SCK period SCK frequency WS setup WS hold WS frequency Min 50 50 312 0.5 0 20 7.8 Max Unit ns ns ns MHz ns ns kHz

3.2

49.3

TIMING DIAGRAM
tSCP tSCH
SCK

tWSS
WS

tSCL

tWSH

SD

Figure 3. Serial Data Port Timing

Rev. B | Page 4 of 16

09568-103

Data Sheet ABSOLUTE MAXIMUM RATINGS

Table 4.
Parameter Supply Voltage (VDD) Sound Pressure Level Mechanical Shock Vibration Operating Temperature Range Digital Pin Input Voltage Rating 0.3 V to +3.6 V 160 dB 10,000 g Per MIL-STD-883 Method 2007, Test Condition B 40C to +85C 0.3 V to VDD + 0.3 V or 3.6 V, whichever is less

ADMP441

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

TP RAMP-UP

tP

CRITICAL ZONE TL TO TP

TEMPERATURE

TL

TSMAX TSMIN

tL

tS
PREHEAT

RAMP-DOWN

t25C TO PEAK
TIME

Figure 4. Recommended Soldering Profile Limits

Table 5. Recommended Soldering Profile Limits

Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX), tS Ramp-Up Rate (TSMAX to TL) Time Maintained Above Liquidous (tL) Liquidous Temperature (TL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25C (t25C) to Peak Temperature Sn63/Pb37 1.25C/sec max 100C 150C 60 sec to 75 sec 1.25C/sec 45 sec to 75 sec 183C 215C +3C/3C 20 sec to 30 sec 3C/sec max 5 minute max Pb-Free 1.25C/sec max 100C 200C 60 sec to 75 sec 1.25C/sec ~50 sec 217C 260C +0C/5C 20 sec to 30 sec 3C/sec max 5 minute max

Rev. B | Page 5 of 16

09568-002

ADMP441 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADMP441

Data Sheet

L/R 4

6 GND

SD 2

GND 5

WS 3

7 VDD

8 CHIPEN

SCK 1 BOTTOM VIEW (Not to Scale)

9 GND
09568-003

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic SCK SD WS L/R GND GND VDD CHIPEN GND Type Input Output Input Input Ground Ground Power Input Ground Description Serial Data Clock for IS Interface. Serial Data Output for IS Interface. This pin tristates when not actively driving the appropriate output channel. The SD trace should have a 100 k pull-down resistor to discharge the line during the time that all microphones on the bus have tristated their outputs. Serial Data-Word Select for IS Interface. Left/Right Channel Select. When set low, the microphone outputs its signal in the left channel of the IS frame; when set high, the microphone outputs its signal in the right channel. Ground. Connect to ground on the PCB. Ground. Connect to ground on the PCB. Power, 1.8 to 3.3 V. This pin should be decoupled to Pin 6 with a 0.1 F capacitor. Microphone Enable. When set low (ground), the microphone is disabled and put in power-down mode. When set high (VDD), the microphone is enabled. Ground. Connect to ground on the PCB.

Rev. B | Page 6 of 16

Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS

10 8 6
10

ADMP441

SENSITIVITY (dB)

2 0 2 4 6 8
09568-009

AMPLITUDE (dB)

10

100

1k FREQUENCY (Hz)

10k

100

1k FREQUENCY (Hz)

10k

Figure 6. Frequency Response Mask

0 10 20 30

Figure 8. Typical Frequency Response (Measured)

PSR (dB)

40 50 60 70 80 100

1k FREQUENCY (Hz)

10k

Figure 7. Typical Power Supply Rejection vs. Frequency

09568-010

Rev. B | Page 7 of 16

09568-011

10 50

20 10

ADMP441 THEORY OF OPERATION

The ADMP441 is a high performance, low power, digital output, omnidirectional MEMS microphone with a bottom port. The complete ADMP441 solution consists of a MEMS sensor, signal conditioning, an analog-to-digital converter, antialiasing filters, power management, and an industry standard 24-bit IS interface. The ADMP441 complies with the TIA-920 Telecommunications Telephone Terminal Equipment Transmission Requirements for Wideband Digital Wireline Telephones standard.

Data Sheet
Power-Down Mode
The microphone enters power-down mode when CHIPEN is low, regardless of the SCK operation. Normal mode operation resumes 217 SCK clock cycles (43 ms with SCK at 3.072 MHz) after CHIPEN returns high while SCK is active. It always takes 217 clock cycles to restart the ADMP441 after VDD is applied. It is not recommended to supply active clocks (WS and SCK) to the ADMP441 while there is no power supplied to VDD. Doing this continuously turns on ESD protection diodes, which may affect long-term reliability of the microphone.

UNDERSTANDING SENSITIVITY
The casual user of digital microphones may have difficulty understanding the sensitivity specification. Unlike an analog microphone (whose specification is easily confirmed with an oscilloscope), the digital microphone output has no obvious unit of measure. The ADMP441 has a nominal sensitivity of 26 dBFS at 1 kHz with an applied sound pressure level of 94 dB. The units are in decibels referred to full scale. The ADMP441 default full-scale peak output word is 223 1 (integer representation), and 26 dBFS of that scale is (223 1) 10(26/20) = 420,426. A pure acoustic tone at 1 kHz having a 1 Pa rms amplitude results in an output digital signal whose peak amplitude is 420,426. Although the industry uses a standard specification of 94 dB SPL, the ADMP441 test method applies a 104 dB SPL signal. The higher sound pressure level reduces noise and improves repeatability. The ADMP441 has excellent gain linearity, and the sensitivity test result at 94 dB is derived with very high confidence from the test data.

STARTUP
The microphones have zero output for the first 218 SCK clock cycles (85 ms with SCK at 3.072 MHz) following power-up.

IS DATA INTERFACE
The slave serial data ports format is IS, 24-bit, twos complement. There must be 64 SCK cycles in each WS stereo frame, or 32 SCK cycles per data-word. The L/R control pin determines whether the ADMP441 outputs data in the left or right channel. For a stereo application, the SD pins of the left and right ADMP441 microphones should be tied together as shown in Figure 9. The format of a stereo IS data stream is shown in Figure 10. Figure 11 and Figure 12 show the formats of a mono microphone data stream for left and right microphones, respectively.

Data Output Mode

The output data pin (SD) is tristated when it is not actively driving IS output data. SD immediately tristates after the LSB is output so that another microphone can drive the common data line. The SD trace should have a pull-down resistor to discharge the line during the time that all microphones on the bus have tristated their outputs. A 100 k resistor is sufficient for this, as shown in Figure 9.

POWER MANAGEMENT
The ADMP441 has three different power states: normal operation, standby mode, and power-down mode.

Normal Operation
The microphone becomes operational 218 clock cycles (85 ms with SCK at 3.072 MHz) after initial power-up. The CHIPEN pin then controls the power modes. The part is in normal operation mode when SCK is active and the CHIPEN pin is high.

Data-Word Length
The output data-word length is 24 bits per channel. The ADMP441 must always have 64 clock cycles for every stereo data-word (fSCK = 64 fWS).

Standby Mode
The microphone enters standby mode when the serial data clock SCK stops and CHIPEN is high. Normal operation resumes 214 clock cycles (5 ms with SCK at 3.072 MHz) after SCK restarts. The ADMP441 should not be transitioned from standby to power-down mode, or vice versa. Standby mode is only intended to be entered from the normal operation state.

Data-Word Format
The default data format is IS (twos complement), MSB-first. In this format, the MSB of each word is delayed by one SCK cycle from the start of each half-frame.

Rev. B | Page 8 of 16

Data Sheet
FROM VOLTAGE REGULATOR (1.8V TO 3.3V) SYSTEM MASTER (DSP, MICROCONTROLLER, CODEC)

ADMP441

SCK

WS

0.1F VDD VDD CHIPEN SCK WS L/R

SD

0.1F VDD VDD SCK WS SD 100k CHIPEN

LEFT

ADMP441
GND GND GND

SD

RIGHT

ADMP441
GND GND GND

L/R

Figure 9. System Block Diagram

WS SCK (64 fS)

24

25

26

32

33

34

35

36

56

09568-004

57

58

64

MSB HIGH-Z LEFT CHANNEL

LSB HIGH-Z

MSB RIGHT CHANNEL

LSB HIGH-Z

Figure 10. Stereo Output IS Format

WS SCK (64 fS)

24

25

26

32

33

34

35

36

56

57

58

64

MSB HIGH-Z LEFT CHANNEL

LSB HIGH-Z

Figure 11. Mono Output IS Format Left Channel (L/R = 0)

WS SCK (64 fS)

24

25

26

32

33

34

35

36

56

57

58

64

MSB HIGH-Z RIGHT CHANNEL

LSB HIGH-Z

Figure 12. Mono Output IS Format Right Channel (L/R = 1)

Rev. B | Page 9 of 16

09568-007

SD (24-BIT)

09568-006

SD (24-BIT)

09568-005

SD (24-BIT)

ADMP441
DIGITAL FILTER CHARACTERISTICS
The ADMP441 has an internal digital band-pass filter. A high-pass filter eliminates unwanted low frequency signals. A low-pass filter allows the user to scale the pass band with the sampling frequency as well as perform required noise reduction.

Data Sheet
wide dynamic range. However, it does require a good quality low-pass filter to eliminate the high frequency noise. Figure 13 shows the response of this digital low-pass filter included in the microphone. The pass band of the filter extends to 0.423 fS and, in that band, has an unnoticeable 0.04 dB of ripple. The high frequency cutoff of 6 dB occurs at 0.5 fS. A 48 kHz sampling rate results in a pass band of 20.3 kHz and a half amplitude corner at 24 kHz; the stop-band attenuation of the filter is greater than 60 dB. Note that these filter specifications scale with sampling frequency.
0 10

High-Pass Filter
The ADMP441 incorporates a high-pass filter to remove unwanted dc and very low frequency components. Table 7 shows the highpass characteristics for a nominal sampling rate of 48 kHz. The cutoff frequency scales with changes in sampling rate. Table 7. High-Pass Filter Characteristics
Frequency 3.7 Hz 10.4 Hz 21.6 Hz Attenuation 3.0 dB 0.5 dB 0.1 dB

20

MAGNITUDE (dB)

30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
09568-008

This digital filter response is in addition to the natural highpass response of the ADMP441 MEMS acoustic transducer that has a 3 dB cutoff of 60 Hz.

Low-Pass Filter
The analog-to-digital converter in the ADMP441 is a single-bit, high order, sigma-delta (-) running at a high oversampling ratio. The noise shaping of the converter pushes the majority of the noise well above the audio band and gives the microphone a

NORMALIZED FREQUENCY (fS)

Figure 13. Digital Low-Pass Filter Magnitude Response

Rev. B | Page 10 of 16

Data Sheet APPLICATIONS INFORMATION

POWER SUPPLY DECOUPLING
For best performance and to avoid potential parasitic artifacts, placing a 0.1 F ceramic type X7R or better capacitor between Pin 7 (VDD) and ground is strongly recommended. The capacitor should be placed as close to Pin 7 as possible. The connections to each side of the capacitor should be as short as possible, and the trace should stay on a single layer with no vias. For maximum effectiveness, locate the capacitor equidistant from the power and ground pins or, when equidistant placement is not possible, slightly closer to the power pin. Thermal connections to the ground planes should be made on the far side of the capacitor, as shown in Figure 14.
VDD GND

ADMP441
Reflow Solder
For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used to attach the MEMS microphone to the PCB. It is recommended that the solder reflow profile does not exceed the limit conditions specified in Figure 4 and Table 5.

Board Wash
When washing the PCB, ensure that water does not make contact with the microphone port. Blow-off procedures and ultrasonic cleaning must not be used.

SUPPORTING DOCUMENTATION
Evaluation Board User Guide
UG-303, EVAL-ADMP441Z-FLEX: Bottom-Port I2S Output MEMS Microphone Evaluation Board

CAPACITOR

UG-362, EVAL-ADMP441Z SDP Daughter Board for the ADMP441 I2S MEMS Microphone

Circuit Note
TO VDD
09568-012

CN-0208, High Performance Digital MEMS Microphone's Simple Interface to SigmaDSP Audio Processor with I2S Output
TO GND

Figure 14. Recommended Power Supply Bypass Capacitor Layout

CN-0266, High Performance Digital MEMS Microphone Standard Digital Audio Interface to Blackfin DSP

HANDLING INSTRUCTIONS
Pick-and-Place Equipment
The MEMS microphone can be handled using standard pickand-place and chip shooting equipment. Care should be taken to avoid damage to the MEMS microphone structure as follows: Use a standard pickup tool to handle the microphone. Because the microphone hole is on the bottom of the package, the pickup tool can make contact with any part of the lid surface. Do not pick up the microphone with a vacuum tool that makes contact with the bottom side of the microphone. Do not pull air out of or blow air into the microphone port. Do not use excessive force to place the microphone on the PCB.

Application Notes
AN-1003 Application Note, Recommendations for Mounting and Connecting Analog Devices, Inc., Bottom-Ported MEMS Microphones AN-1068 Application Note, Reflow Soldering of the MEMS Microphone AN-1112 Application Note, Microphone Specifications and Terms Explained AN-1124 Application Note, Recommendations for Sealing Analog Devices, Inc., Bottom-Port MEMS Microphones from Dust and Liquid Ingress AN-1140 Application Note, Microphone Array Beamfoaming For additional information, visit www.analog.com/mic.

Rev. B | Page 11 of 16

ADMP441 LAYOUT AND DESIGN RECOMMENDATIONS

1.05 (6)

Data Sheet

0.25 DIA. (THRU HOLE) 2.66 (4)

0.96 1.56

1.33 (2)

DIMENSIONS SHOWN IN MILLIMETERS

Figure 15. Recommended Printed Circuit Board Land Pattern (Dimensions shown in millimeters)

1.05 (6)

0.20

1.05 2.66 (4) 3.76

1.33 (2) 1.6

0.350 0.550 (8) 4.72

1.07

09568-013

0.40 0.60 (8)

3.16

DIMENSIONS SHOWN IN MILLIMETERS

Figure 16. Recommended Printed Circuit Board Solder Paste Mask Pattern (Dimensions shown in millimeters)

Rev. B | Page 12 of 16

09568-014

Data Sheet OUTLINE DIMENSIONS

4.82 4.72 4.62 4.10 REF
PIN 1 REFERENCE CORNER 0.40 0.60 (PINS 1-8)

ADMP441

0.30 1.05 BSC 1.07 1.56 DIA. 0.96 DIA.

1 4

3.86 3.76 3.66 3.14 REF

2.66 BSC
5

0.275 0.250 DIA. 0.225 1.33 BSC

TOP VIEW 1.05 0.98 0.88 0.73 REF

BOTTOM VIEW

SIDE VIEW

0.24 REF

Figure 17. 9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] 4.72 mm 3.76 mm 1 mm Body (CE-9-1) Dimensions shown in millimeters

ORDERING GUIDE
Model 1 ADMP441ACEZ-RL ADMP441ACEZ-RL7 EVAL-ADMP441Z EVAL-ADMP441Z-FLEX
1 2

Temperature Range 40C to +85C 40C to +85C

Package Description 9-Terminal LGA_CAV, 13 Tape and Reel 9-Terminal LGA_CAV, 7 Tape and Reel Evaluation Board Flex Evaluation Board

Package Option 2 CE-9-1 CE-9-1

Ordering Quantity 4,500 1,000

Z = RoHS Compliant Part. This package option is halide-free.

Rev. B | Page 13 of 16

12-19-2011-B

ADMP441 NOTES

Data Sheet

Rev. B | Page 14 of 16

Data Sheet NOTES

ADMP441

Rev. B | Page 15 of 16

ADMP441 NOTES

Data Sheet

20112012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09568-0-10/12(B)

Rev. B | Page 16 of 16