EC2207 - Digital Electronics LAB Mannual

EC2207 / Digital Electronics Lab
KODAIKANAL INSTITUTE OF TECHNOLOGY

Machur - Kodaikanal
ANNA UNIVERSITY 2008 REGULATION
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.
EC2207 DIGITAL ELECTRONICS LABORATORY

(II Year B.E III Semester 2011 Batch)
Dept of Electronics & Communication Engineering
EC2207 DIGITAL ELECTRONICS LAB
LT PC 0 03 2
1.
Design and implementation of Adders and Subtractors using logic gates. (i) BCD to excess-3 code and vice versa. (ii) Binary to gray and vice-versa.
2. Design and implementation of code converters using logic gates
3.
Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using IC 7483. Design and implementation of 2 Bit Magnitude Comparator using logic gates & 8 Bit Magnitude Comparator using IC 7485. Design and implementation of 4- bit odd/even parity checker /generator using IC74180. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters. Design and implementation of 3-bit synchronous up/down counter. flops.
4.
5.
6.
7.
8.
9.
10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip11.
Design of experiments 1, 6, 8, and 10 using Verilog Hardware Description Language.
TOTAL= 45 PERIODS
INDEX
EXP.NO. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. . 12. 13. 14. 15 16
LIST OF THE EXPERIMENT Study of Logic Gates. Design of Adder & Subtractor. Design & Implementation of Code Converter. Design of 4-bit Binary Adder / Subtractor. Design & Implementation of Magnitude Comparator. 16-bit Odd/ Even parity Checker/Generator. Design & Implementation of Multiplexer & DeMultiplexer. Design & Implementation of Encoder & Decoder. Construction & Verification of 4-bit Ripple Counter, Mod 10/12 Ripple Counter. Design & Implementation of 3-bit Synch Up/Down counter. Design & Implementation of Shift Register. Study of Simulation Tools HDL Coding for Combinational circuits-Adders & Subtractors. HDL Coding for Sequential Circuits-Shift Registers. HDL Coding for Multiplexer & De-multiplexer. Carry Look Ahead Adder 2-bit binary multiplier
PAGE NO 4 10 17 32 38 44 48 54 60 64 68 73 78 84 90 96 98
1. STUDY OF LOGIC GATES 1.1 AIM: To study about logic gates and verify their truth tables. 1.2 APPARATUS REQUIRED:
1.3 THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these gates. 1.3.1 AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is low level when any one of the inputs is low. 1.3.2 OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low. 1.3.3 NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high. 1.3.4 NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high.
SL No. 1. 2. 3. 4. 5. 6. 7. 8. 9.
COMPONENT AND GATE OR GATE NOT GATE NAND GATE 2 I/P NOR GATE X-OR GATE NAND GATE 3 I/P IC TRAINER KIT PATCH CORD
SPECIFICATION IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 IC 7410 -
QTY 1 1 1 1 1 1 1 1 14
1.AND GATE: SYMBOL: PIN DIAGRAM:
1.3.5 NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high. 1.3.6 X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high. 1.4 PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
2.OR GATE:
3.NOT GATE: SYMBOL: PIN DIAGRAM:
4.X-OR GATE :
SYMBOL:
PIN DIAGRAM :
5. 2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:
6. 3-INPUT NAND GATE:
7. NOR GATE:
1.5 VIVA QUESTIONS: 1. Obtain AND gate using only NAND gates:
2. What are universal gates?
3. State Demorgans theorem:
4. Implement OR gate using only NAND gate:
5. Write the truth table for EX-OR gate:
6. What is a logic gate?
7. State the consensus theorem in Boolean algebra:
8. What are dont care conditions?
9. What is the need for Quine Mccluskey method?
10. What are minterm and maxterm?
1.6 RESULT: Thus the Logic gates are studied & truth tables are verified.
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2. DESIGN OF ADDER AND SUBTRACTOR

2.1 AIM: To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. 2.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 4. 5. 6. COMPONENT AND GATE X-OR GATE NOT GATE OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7404 IC 7432 QTY. 1 1 1 1 1 23
2.3 THEORY: 2.3.1 HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from the sum S and other from the carry c into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate. 2.3.2 FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate. 2.3.3 HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter. 2.3.4 FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
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output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR. 2.4 LOGIC DIAGRAM: 2.4.1 HALF ADDER
TRUTH TABLE: A 0 0 1 1 K-Map for SUM: B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0
K-Map for CARRY:
SUM = AB + AB
CARRY = AB
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LOGIC DIAGRAM: 2.4.2 FULL ADDER FULL ADDER USING TWO HALF ADDER
TRUTH TABLE: A 0 0 0 0 1 1 1 1 K-Map for SUM: B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1
SUM = ABC + ABC + ABC + ABC
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K-Map for CARRY:
CARRY = AB + BC + AC LOGIC DIAGRAM: 2.4.3 HALF SUBTRACTOR
TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW 0 1 0 0 DIFFERENCE 0 1 1 0
K-Map for DIFFERENCE:
DIFFERENCE = AB + AB
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K-Map for BORROW:
BORROW = AB LOGIC DIAGRAM: 2.4.4 FULL SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
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TRUTH TABLE: A 0 0 0 0 1 1 1 1 K-Map for Difference:
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
BORROW 0 1 1 1 0 0 0 1
DIFFERENCE 0 1 1 0 1 0 0 1
Difference = ABC + ABC + ABC + ABC K-Map for Borrow:
Borrow = AB + BC + AC 2.5 PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
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2.6 VIVA QUESTIONS: 1. What is half adder? 2. What do you mean by carry propagation delay? 3. What is the difference between serial adder and parallel adder? 4. What is Full adder? 5. What is a combinational circuit? 6. What is Half Subtractor? 7. What do you mean by carry propagation delay? 8. What is BCD adder? 9. What is Full Subtractor? 10. Write the design procedure for combinational circuit?
2.7 RESULT: Thus half adder, full adder, half subtractor and full subtractor circuits are constructed and the truth table are verified using logic gates.
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3. DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

3.1 AIM: To design and implement 4-bit (i) Binary to gray code converter (ii) Gray to binary code converter (iii) BCD to excess-3 code converter (iv) Excess-3 to BCD code converter 3.2 APPARATUS REQUIRED: SL.No. COMPONENT SPECIFICATION QTY. 1. X-OR GATE IC 7486 1 2. AND GATE IC 7408 1 3. OR GATE IC 7432 1 4. NOT GATE IC 7404 1 5. IC TRAINER KIT 1 6. PATCH CORDS 35 3.3 THEORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs. Binary to Gray code conversion:
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Binary code is representing a decimal number with the help of 8421 code, where the numbers show to us the weights of their respective positions.Only a single bit change from one code word to the next in sequence.And Gray code can be attained from the binary code as illustrated in the following example. Consider a binary number 1101 for which the corresponding Gray code is going to be found out. B3 B2 B1 B0 BINARY 1 1 0 1
GRAY 1
0 G3
1 G2
1 G1
1 G0
As can be clearly seen, Gray code generation follows some simple steps. The Most Significant Bit (MSB) of the binary code is retained as the MSB of the Gray code too. The next bit of the Gray code can be attained by adding the MSB and the adjacent bit of the binary code. The consequent bits of the Gray code can be attained in the same fashion. If this conversion is given a little more thought, one striking feature that one would find is that except for the MSB the consequent bits in the Gray code will be 1 if and only if the corresponding bit and the previous code of the Binary code are not the same. Using the observation we can write the following expressions: G3 = B3 G2 = B3 B2 G1 = B2 B1 G0 = B1 B0 Gray to Binary code conversion: A Gray code can also be converted into a binary code in almost a similar manner but with some deviations. With the help of an example this conversion is explained below. Consider a Gray code 1111 for which a binary is going to be found out.
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3.4 LOGIC DIAGRAM: 3.4.1 BINARY TO GRAY CODE CONVERTOR
K-Map for G3:
G3 = B3 K-Map for G2:
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G3 GRAY 1 1
G2 1
G1 1
G0 1
BINARY
B3 B2 B1 B0 By looking at the illustration it is very easy to understand that MSB of both the codes are the same whereas the consecutive bits of the binary is attained by adding the corresponding bit of the Gray code with the sum of the more significant bits. The expressions for the individual bits of the binary code in terms of the bits of the Gray code. B3 = G3 B2 = G3 G2 B1 = G3 G2 G1 B0 = G3 G2 G1 G0 BCD code to Excess-3 code conversion: Binary coded decimal code as the name itself conveys it is a code in which a decimal is represented by binary numbers. Whereas Excess-3 code is one in which a decimal value (X) is represented by a binary code, which corresponds to another decimal value whose value is 3 in excess (X + 3). The mathematical expression, which represents this conversion, is as follows. _______ E3 = B0B2 + B1B2 + B3 E1 = B0 B1 _ _ _ _ _ E2 = B0B2 + B1B2 + B0B1B2 E0 = B0 Excess3 code of decimal digit x is obtained by adding 3(0011) to the BCD code of decimal digit x. Excess3 is a sequential code because each succeeding code is one binary no. greater than its preceding code.Excess3 is a self complementing code. Example: Excess3 for (5)10 are:
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K-Map for G1:
K-Map for G0:
TRUTH TABLE: | Binary input B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
| G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Gray code output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
| G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 22
LOGIC DIAGRAM: 3.4.2 GRAY CODE TO BINARY CONVERTOR
K-Map for B3:
B3 = G3
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K-Map for B2:
K-Map for B1:
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K-Map for B0:
TRUTH TABLE: | Gray Code G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 | Binary Code B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 | B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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LOGIC DIAGRAM: 3.4.3 BCD TO EXCESS-3 CONVERTOR
K-Map for E3:
E3 = B3 + B2 (B0 + B1)
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K-Map for E2:
K-Map for E1:
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3.4.4 EXCESS-3 TO BCD CONVERTOR
K-Map for E0:
TRUTH TABLE: | BCD input
Excess 3 output
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B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
G3 0 0 0 0 0 1 1 1 1 1 x x x x x x
G2 0 1 1 1 1 0 0 0 0 1 x x x x x x
G1 1 0 0 1 1 0 0 1 1 0 x x x x x x
G0 1 0 1 0 1 0 1 0 1 0 x x x x x x
LOGIC DIAGRAM:
K-Map for A: A = X1 X2 + X3 X4 X1
K-Map for B:
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K-Map for C:
K-Map for D:
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TRUTH TABLE: | B3 0 0 0 0 0 1 1 1 1 1 Excess 3 Input B2 0 1 1 1 1 0 0 0 0 1 B1 1 0 0 1 1 0 0 1 1 0 | B0 1 0 1 0 1 0 1 0 1 0 G3 0 0 0 0 0 0 0 0 1 1 BCD Output G2 0 0 0 0 1 1 1 1 0 0 G1 0 0 1 1 0 0 1 1 0 0 | G0 0 1 0 1 0 1 0 1 0 1
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3.5 PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.
3.6 VIVA QUESTIONS: 1. What are code converters? 2. Distinguish between Boolean addition and Binary addition: 3. What is decoder? 4. What is encoder? 5. What is Priority Encoder?
3.7 RESULT: Thus 4-bit Code Converter circuits were designed and implemented using logic gates.
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4. DESIGN OF 4-BIT ADDER AND SUBTRACTOR

4.1 AIM: To design and implement 4-bit adder and subtractor using IC 7483. 4.2 APPARATUS REQUIRED: SL.No. COMPONENT SPECIFICATION QTY. 1. IC IC 7483 1 2. EX-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 3. IC TRAINER KIT 1 4. PATCH CORDS 40 4.3 THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4. 4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placed between each data input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction. 4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor. 4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
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4.4 PIN DIAGRAM FOR IC 7483:
4.5 LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR
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4.5.1 TRUTH TABLE:
Input Data A
Input Data B C 0 1 0 0 1 1 1
Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 B 1 1 0 0 0 0 0
Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1
A4 A3 A2 A1 B4 B3 B2 B1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1
4.5.2LOGIC DIAGRAM: BCD ADDER
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K-MAP:
Y = S4 (S3 + S2) 4.5.3 TRUTH TABLE: S4 0 0 BCD SUM S3 S2 0 0 0 0 S1 0 1 CARRY C 0 0 36
0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1
4.5.4 PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.
4.5.5 VIVA QUESTIONS: 1. What is the difference between Serial Adder & Parallel Adder?
2. How BCD Addition is performed? 3. Explain the logic how an IC7483 can be used as both Adder / Subtractor?
4. Explain the logic of EX-OR gate?
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5. Draw the pin configuration of Adder / Subtractor IC.
4.5.6 RESULT: Thus 4-bit adder and subtractor were designed and implemented using IC 7483.
5.4 LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR
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5. DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

5.1 AIM: To design and implement (i) (ii) 2 bit magnitude comparator using basic gates. 8 bit magnitude comparator using IC 7485.
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5.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT AND GATE X-OR GATE OR GATE NOT GATE 4-BIT MAGNITUDE COMPARATOR IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 IC 7485 QTY. 2 1 1 1 2 1 30
5.3 THEORY: The comparison of two numbers is an operator that determines one number is greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B. A = A3 A2 A1 A0 B = B3 B2 B1 B0 The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B). This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from most significant position. A is 0 and that of B is 0. We have A<B, the sequential comparison can be expanded as A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01 A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0 The same circuit can be used to compare the relative magnitude of two BCD digits. Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0) x3 K MAP x2 x1 x0
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5.5 TRUTH TABLE A1 A0 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1
A>B 0 0 0 0 1 0 0 0 1 1
A=B 1 0 0 0 0 1 0 0 0 0
A<B 0 1 1 1 0 0 1 1 0 0 41
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
0 0 1 1 1 0
1 0 0 0 0 1
0 1 0 0 0 0
5.7 LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR
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TRUTH TABLE:
A 0000 0000 0001 0001 0000 0000 5.8 PROCEDURE: (i) (ii) (iii)
B 0000 0000 0000 0000 0001 0001
A>B 0 1 0
A=B 1 0 0
A<B 0 0 1
Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
5.9 VIVA QUESTIONS: 1. What is a comparator? 2. What are the various applications of a comparator?
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3. Draw the pin configuration of IC 7485. 4. What is propagation delay? 5. Define Fan-in & Fan-out.
5.10 RESULT: Thus a 2 bit magnitude comparator using basic gates and 8- bit magnitude comparator using IC 7485 were designed and implemented.
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6.5 FUNCTION TABLE:
INPUTS Number of High Data Inputs (I0 I7) EVEN ODD EVEN ODD X X
PE 1 1 0 0 1 0
PO 0 0 1 1 1 0
OUTPUTS E O 1 0 0 1 0 1 0 1 1 0 0 1
6. 16-BIT ODD/EVEN PARITY CHECKER /GENERATOR

6.1 AIM: To design and implement 16 bit odd/even parity checker generator using IC 74180. 6.2 APPARATUS REQUIRED: SL.No. 1. 1. 2. 3. 6.3 THEORY: A parity bit is used for detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number is either even or odd. The COMPONENT NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7404 IC 74180 QTY. 1 2 1 30
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message including the parity bit is transmitted and then checked at the receiver ends for errors. An error is detected if the checked parity bit doesnt correspond to the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity, the added parity bit will make the total number is even amount. In odd parity, the added parity bit will make the total number is odd amount. The parity checker circuit checks for possible errors in the transmission. If the information is passed in even parity, then the bits required must have an even number of 1s. An error occur during transmission, if the received bits have an odd number of 1s indicating that one bit has changed in value during transmission.
6.6 LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY CHECKER
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TRUTH TABLE: I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 I7 0 0 0 I6 0 0 0 I5 0 0 0 I4 I3 0 0 0 0 0 0 I2 11 I0 0 0 0 1 1 0 1 1 0 Active 1 0 1 E 1 1 0 O 0 0 1
LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY GENERATOR
TRUTH TABLE:
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I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 6.7 PROCEDURE: (i) (ii) (iii)
I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Active 1 0 0
E 1 0 1
O 0 1 0
Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
6.8 RESULT: Thus a 16 bit odd/even parity checker / generator were designed and implemented using IC 74180.
7.4 BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
7.4.1 FUNCTION TABLE: S1 0 0 1 1 S0 0 1 0 1 INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0 48
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
7. DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

7.1 AIM: To design and implement multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154. 7.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 2. 3. COMPONENT 3 I/P AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7411 IC 7432 IC 7404 QTY. 2 1 1 1 32
7.3 THEORY: MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected. DEMULTIPLEXER:
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The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.
7.4.2 CIRCUIT DIAGRAM FOR MULTIPLEXER:
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7.4.3 TRUTH TABLE: S1 0 0 1 1 S0 0 1 0 1 Y = OUTPUT D0 D1 D2 D3
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7.5.1 BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
7.5.2 FUNCTION TABLE:
S1 0 0 1 1
S0 0 1 0 1
INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0
Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0
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7.5.3 LOGIC DIAGRAM FOR DEMULTIPLEXER:
7.5.4 TRUTH TABLE: S1 0 0 0 0 1 1 1 1 INPUT S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1
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7.8 PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
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7.9 VIVA QUESTIONS: 1. What is a multiplexer?
2. What are the applications of multiplexer?
3. What is the difference between multiplexer & demultiplexer?
4. In 2n: 1 multiplexer how many selection lines are used?
5. Draw a 2 to 1 multiplexer circuit
6. Draw a 1 to 2 demultiplexer circuit.
7. What is the difference between a decoder and a demultiplexer?
7.10 RESULT: Thus design and implementation of multiplexer and demultiplexer circuits were performed using logic gates and IC 74150 and IC 74154 were studied.
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8. DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

8.1 AIM: To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147. 8.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 4. 5. COMPONENT 3 I/P NAND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7410 IC 7432 IC 7404 QTY. 2 3 1 1 27
8.3 THEORY: ENCODER: An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguity that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1. DECODER: A decoder is a multiple input multiple output logic circuits which converts coded input into coded output where input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n 1.
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8.4 PIN DIAGRAM FOR IC 7445: BCD TO DECIMAL DECODER:
PIN DIAGRAM FOR IC 74147:
8.5 LOGIC DIAGRAM FOR ENCODER:
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TRUTH TABLE: Y1 1 0 0 0 0 0 0 Y2 0 1 0 0 0 0 0 Y3 0 0 1 0 0 0 0 INPUT Y4 Y5 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Y6 0 0 0 0 0 1 0 Y7 0 0 0 0 0 0 1 A 0 0 0 1 1 1 1 OUTPUT B 0 1 1 0 0 1 1 C 1 0 1 0 1 0 1
8.6 LOGIC DIAGRAM FOR DECODER:
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TRUTH TABLE: INPUT A 0 0 0 1 1 OUTPUT D1 D2 1 1 1 1 0 1 1 0 1 1
E 1 0 0 0 0
B 0 0 1 0 1
D0 1 0 1 1 1
D3 1 1 1 1 0
8.7 PROCEDURE: (i) Connections are given as per circuit diagram.
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(ii) (iii)
Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
8.8 VIVA QUESTIONS: 1. Define Encoder.
2. Define Decoder.
3. List the features of IC7445 & IC74147.
4. Differentiate Encoder & Multiplexer.
5. Give the applications of Encoder & Decoder.
8.9 RESULT: Thus design and implementation of encoder and decoder circuits were performed using logic gates and IC 7445 and IC 74147 were studied.
9.5.1 LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
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9.5.2 TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
9. CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER
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9.1 AIM: To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter. 9.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 4. COMPONENT JK FLIP FLOP NAND GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7476 IC 7400 QTY. 2 1 1 30
9.3 THEORY: A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation. 9.4 PIN DIAGRAM FOR IC 7476:
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9.6.1 LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
9.6.2 TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 QA 0 1 0 1 0 1 0 1 0 1 0 QB 0 0 1 1 0 0 1 1 0 0 0 QC 0 0 0 0 1 1 1 1 0 0 0 QD 0 0 0 0 0 0 0 0 1 1 0
9.7.1 LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
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9.7.2 TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 0 0 QD 0 0 0 0 0 0 0 0 1 1 1 1 0
9.8 PROCEDURE: (i) (ii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram.
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(iii)
Observe the output and verify the truth table.
9.9 VIVA QUESTIONS: 1. What is the difference between Register & counter?
2. What is Ripple Counter?
3. What is MOD-N counter?
4. Which flip flop is used in counters?
5. What is D flip flop? Draw its truth table.
6. What is T flip flop? Draw its truth table.
9.10 RESULT: Thus 4 - bit ripple counter, mod 10/ mod 12 ripple counters were designed and implemented using IC7476.
10. DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

10.1 AIM: To design and implement 3 bit synchronous up/down counter. 10.2 APPARATUS REQUIRED: SL.No. COMPONENT SPECIFICATION QTY. 65
1. 2. 3. 4. 5. 6. 7.
JK FLIP FLOP 3 I/P AND GATE OR GATE XOR GATE NOT GATE IC TRAINER KIT PATCH CORDS
IC 7476 IC 7411 IC 7432 IC 7486 IC 7404 -
2 1 1 1 1 1 35
10.3 THEORY: A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down signal. When this signal is high counter goes through up sequence and when up/down signal is low counter follows reverse sequence. 10.4 K MAP
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10.5 STATE DIAGRAM:
10.6 CHARACTERISTICS TABLE: Q 0 0 1 1 Qt+1 0 1 0 1 J 0 1 X X K X X 1 0
10.7 LOGIC DIAGRAM:
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10.8 TRUTH TABLE: Input Present State Up/Down QA QB QC 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Next State QA+1 Q B+1 QC+1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
A JA 1 X X X X 0 0 0 0 0 0 1 X X X X KA X 0 0 0 1 X X X X X X X 0 0 0 1 JB 1 X X 0 1 X X 0 0 1 X X 0 1 X X
B KB X 0 1 X X 0 1 X X X 0 1 X X 0 1 JC 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X
C KC X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1
10.9 PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
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10.10 VIVA QUESTIONS: 1. Define Counter.
2. What is the difference between Combinational & Sequential circuit?
3. Differentiate Synchronous & Asynchronous sequential circuit?
4. What is Up/Down Counter?
5. Name the circuit which outputs based on Flip Flops.
10.11 RESULT: Thus a 3-bit synchronous up/down counter was designed and implemented Using IC7476.
11. DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

11.1 AIM: To design and implement (i) Serial in serial out (ii) Serial in parallel out
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(iii) (iv)
Parallel in serial out Parallel in parallel out.
11.2 APPARATUS REQUIRED: SL.No. 1. 2. 3. 4. COMPONENT D FLIP FLOP OR GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7474 IC 7432 QTY. 2 1 1 35
11.3 THEORY: A register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right. 11.4 PIN DIAGRAM:
11.5 LOGIC DIAGRAM: 11.5.1 SERIAL IN SERIAL OUT:
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TRUTH TABLE: Serial in CLK 1 2 3 4 5 6 7 1 0 0 1 X X X 0 0 0 1 0 0 1 Serial out
LOGIC DIAGRAM: 11.5.2 SERIAL IN PARALLEL OUT:
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TRUTH TABLE: CLK 1 2 3 4 DATA 1 0 0 1 QA 1 0 0 1 OUTPUT QB QC 0 0 1 0 0 1 0 0 QD 0 0 1 1
LOGIC DIAGRAM: 11.5.3 PARALLEL IN SERIAL OUT:
TRUTH TABLE: CLK 0 Q3 1 Q2 0 Q1 0 Q0 1 O/P 1
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1 0 2 0 3 0 LOGIC DIAGRAM:
0 0 0
0 0 0
0 0 0
0 0 1
11.5.4 PARALLEL IN PARALLEL OUT:
TRUTH TABLE: CLK 1 2 DA 1 1 DATA INPUT DB DC 0 0 0 1 DD 1 0 QA 1 1 OUTPUT QB QC 0 0 0 1 QD 1 0
11.6 PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
11.7 VIVA QUESTIONS: 1. What is a register? 2. What are the applications of shift register?
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3. Which flip flop is used in shift register?
4. What is a universal shift register?
5. How many flip flops are needed to build an 8 bit shift register?
11.8 RESULT: Thus the various types of Shift Registers were designed and implemented using IC7474.
STUDY OF SIMULATION TOOLS THEORY: Creating a Test Bench for Simulation:
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In this section, you will create a test bench waveform containing input stimulus you can use to simulate the counter module. This test bench waveform is a graphical view of a test bench. It is used with a simulator to verify that the counter design meets both behavioral and timing design requirements. You will use the Waveform Editor to create a test bench waveform (TBW) file. 1. Select the counter HDL file in the Sources in Project window. 2. Create a new source by selecting Project _ New Source. 3. In the New Source window, select Test Bench Waveform as the source type, and type test bench in the File Name field. 4. Click Next. 5. The Source File dialog box shows that you are associating the test bench with the source file: counter. Click Next. 6. Click Finish. You need to set initial values for your test bench waveform in the Initialize Timing dialog box before the test bench waveform editing window opens. 7. Fill in the fields in the Initialize Timing dialog box using the information below: Clock Time High: 20 ns. Clock Time Low: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Initial Offset: 0 ns Global Signals: GSR (FPGA) Leave the remaining fields with their default values. 8. Click OK to open the waveform editor. The blue shaded areas are associated with each input signal and correspond to the Input Setup Time in the Initialize Timing dialog box. In this tutorial, the input transitions occur at the edge of the blue cells located under each rising edge of the CLOCK input.
Fig 2: Waveform Editor - Test Bench
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Fig 3:Waveform Editor - Expected Results 9. In this design, the only stimulus that you will provide is on the DIRECTION port. Make the transitions as shown below for the DIRECTION port: Click on the blue cell at approximately the 300 ns clock transition. The signal switches to high at this point. Click on the blue cell at approximately the 900 ns clock transition. The signal switches back to low. Click on the blue cell at approximately the 1400 ns clock transition. The signal switches to high again. 10. Select File _ Save to save the waveform. In the Sources in Project window, the TBW file is automatically added to your project. 11. Close the Waveform Editor window. Adding Expected Results to the Test Bench Waveform: In this step you will create a self-checking test bench with expected outputs that correspond to your inputs. The input setup and output delay numbers that were entered into the Initialize Timing dialog when you started the waveform editor are evaluated against actual results when the design is simulated. This can be useful in the Simulate Post- Place & Route HDL Model process, to verify that the design behaves as expected in the target device both in terms of functionality and timing. To create a self-checking test bench, you can edit output transitions manually, or you can run the Generate Expected Results process:
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1. Select the testbench.tbw file in the Sources in Project window. 2. Double-click the Generate Expected Simulation Results process. This process converts the TBW into HDL and then simulates it in a background process. 3. The Expected Results dialog box will open. Select Yes to post the results in the waveform editor. 4. Click the + to expand the COUNT_OUT bus and view the transitions that correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing dialog box. 5. Select File _ Save to save the waveform. 6. Close the Waveform Editor.Now that you have a test bench, you are ready to simulate your design. Simulating the Behavioral Model (ISE Simulator): If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. If you wish to simulate your design with a ModelSim simulator, skip this section and proceed to the Simulating the Behavioral Model (ModelSim) section.
Fig 4:Simulator Processes for Test Bench
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Fig 5:Behavioral Simulation in ISE Simulator To run the integrated simulation processes in ISE: 1. Select the test bench waveform in the Sources in Project window. You can see the Xilinx ISE Simulator processes in the Processes for Source window. 2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To see your simulation results, select the test bench tab and zoom in on the transitions. You can use the zoom icons in the waveform view, or right click and select a zoom command.The ISE window, including the waveform view. 4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 5. Close the waveform view window. You have completed simulation of your design using the ISE Simulator. Skip past the ModelSim section below and proceed to the Creating and Editing Timing and Area Constraintssection. Simulating the Behavioral Model (ModelSim): If you have a ModelSim simulator installed, you can simulate your design using the integrated ModelSim flow. You can run processes from within ISE which launches the installed ModelSim simulator. To run the integrated simulation processes in ISE: 1. Select the test bench in the Sources in Project window. You can see ModelSim Simulator processes in the Processes for Source window in Fig 6.
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Fig 6: Simulator Processes for Test Bench
Fig 7:Behavioral Simulation in ModelSim 2. Double-click the Simulate Behavioral Model process. The ModelSim simulator opens and runs your simulation to the end of the test bench. The ModelSim window, including the waveform, should look like Fig 7. To see your simulation results, view the Wave window. 1. Right-click in the Wave window and select a zoom command. 2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 3. Close the ModelSim window.
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12. HDL CODING FOR COMBINATIONAL CIRCUITS

ADDERS AND SUBTRACTORS 12.1.1 AIM: To develop the source code for adders and subtractors by using VERILOG. 12.1.2 ALGORITM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. HALF ADDER: LOGIC DIAGRAM: TRUTH TABLE:
A 0 0 1 1
B 0 1 0 1
SUM CARRY 0 1 1 0 0 0 0 1
12.1.3 VERILOG SOURCE CODE: Behavioral Modeling: module ha_behv(a, b, s, ca); input a; input b; output s; output ca; reg s,ca; always @ (a or b) begin s=a^b;
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ca=a&b; end endmodule 12.1.4 Simulation output:
HALF SUBTRACTOR: LOGIC DIAGRAM: TRUTH TABLE:
A 0 0 1 1
B 0 1 0 1
DIFFERENCE 0 1 1 0
BORROW 0 1 0 0
12.2.1 VERILOG SOURCE CODE: Behavioral Modeling: module hs_behv(a, b, dif, bor); input a; input b; output dif; output bor; reg dif,bor; reg abar;
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always@(a or b) begin abar=~a; dif=a^b; bor=b&abar; end endmodule 12.2.2 Simulation output:
FULL ADDER: LOGIC DIAGRAM: TRUTH TABLE:
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
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12.3.1 VERILOG SOURCE CODE: Behavioral Modeling: module fulad behavioral(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; reg sum,carry; reg t1,t2,t3; always @ (a or b or c) begin sum = (a^b)^c; t1=a & b; t2=b & c; t3=a & c; carry=(t1 | t2) | t3; end endmodule 12.3.2 Simulation output:
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FULL SUBTRACTOR: LOGIC DIAGRAM: A 0 0 0 0 1 1 1 1 TRUTH TABLE: B C DIFFERENCE 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 BORROW 0 1 1 1 0 0 0 1
12.4.1 VERILOG SOURCE CODE: Behavioral Modeling: module fulsub behavioral(a, b, cin, diff, borrow); input a; input b; input cin; output diff; output borrow; reg t1,t2,t3; reg diff,borrow; reg abar; always @ (a or b or cin) begin abar= ~ a; diff = (a^b)^cin; t1=abar & b; t2=b & cin; t3=cin & abar; borrow=(t1 | t2) | t3;
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end endmodule 12.4.2 Simulation output:
12.5 VIVA QUESTIONS: 1. What is HDL? 2. What is logic simulation? 3. What is logic synthesis? 4. What is UDP? 5. What is Gate level modeling? 6. What is Dataflow modeling? 7. What is Behavioral modeling? 12.6 RESULT: Thus, the source code for adders and subtractors was simulated by using VERILOG.
13. HDL CODING FOR SEQUENTIAL CIRCUITS

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SHIFT REGISTERS 13.1.1 AIM: To develop the source code for shifters unit by using VERILOG and obtain the simulation. 13.1.2 ALGORITM: Step1: Define the specifications and initialize the design. Step2: Write the source code in VERILOG. Step3: Check the syntax and debug the errors if found, obtain the synthesis report. Step4: Verify the output by simulating the source code. Step5: Write all possible combinations of input using the test bench. SERIAL-IN SERIAL-OUT SHIFT REGISTER: 13.1.3 LOGIC DIAGRAM :
13.1.4 VERILOG SOURCE CODE: Behavioral Modeling: module siso(din, clk, rst, dout); input din; input clk; input rst; output dout; reg dout; reg [7:0]x; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1)
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begin dout=8'hzz; end else begin x={x[6:0],din}; dout=x[7]; end end endmodule Simulation output:
SERIAL IN PARALLEL OUT SHIFT REGISTER: 13.2.1 LOGIC DIAGRAM:
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13.2.2 VERILOG SOURCE CODE: Behavioral Modeling: module sipo(din, clk, rst, dout); input din; input clk; input rst; output [7:0] dout; reg[7:0]dout; reg[7:0]x; always @ (posedge(clk) or posedge(rst)) begin if(rst) dout=8'hzz; else begin x={x[6:0],din}; dout=x; end end endmodule
Simulation output:
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PARALLEL-IN PARELLEL-OUT SHIFT REGISTER: 13.3.1 LOGIC DIAGRAM:
13.3.2 VERILOG SOURCE CODE: Behavioral Modeling: module pipo(clk, rst, din, dout); input clk; input rst; input [7:0] din; output [7:0] dout; reg [7:0] dout; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin dout=8'hzz; end else begin
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dout=din; end end endmodule Simulation output:
PARALLEL-IN SERIAL-OUT SHIFT REGISTER: 13.4.1 LOGIC DIAGRAM :
13.4.2 VERILOG SOURCE CODE: Behavioral Modeling: module piso(din, clk, rst, load, dout); input [7:0] din; input clk; input rst; input load; output dout; reg dout;
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reg [8:0]x; always @(posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin dout=1'bz; end else begin if (load==1'b0) begin x=din; end else x={x[7:0],1'hz}; dout=x[8]; end end endmodule Simulation output:
13.1.5 RESULT: Thus, the source code for shifters unit was written and simulated using VERILOG.
14. MULTIPLEXER & DEMULTIPLEXER

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14.1 AIM: To implement Multiplexer & Demultiplexer using Verilog HDL. 14.2 APPARATUS REQUIRED: PC with Windows XP. XILINX, ModelSim software. 14.3 PROCEDURE: Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained.
Multiplexer:
Output:
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# # # # # # # # # # #
4to1 Multiplexer ----------------------------------------------Input=1011 ----------------------------------------------Selector Output ----------------------------------------------{0,0} 1 {1,0} 0 {0,1} 1 {1,1} 1 -----------------------------------------------
14.4 PROGRAM:
Multiplexer: // Module Name: Mux4to1 module Mux4to1(i0, i1, i2, i3, s0, s1, out); input i0; input i1; input i2; input i3; input s0; input s1; output out; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not (s0n,s0); and (y0,i0,s1n,s0n); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); or (out,y0,y1,y2,y3); endmodule // Module Name: Stimulus.v module Stimulus_v;
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// Inputs reg i0; reg i1; reg i2; reg i3; reg s0; reg s1; // Outputs wire out; // Instantiate the Unit Under Test (UUT) Mux4to1 uut ( .i0(i0), .i1(i1), .i2(i2), .i3(i3), .s0(s0), .s1(s1), .out(out) ); Demultiplexer:
initial begin
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$display("\t\t\t 4to1 Multiplexer"); $display("\t\t------------------------------------"); #1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3); $display("\t\t------------------------------------"); $display("\t\tSelector\t\t\t\tOutput"); $display("\t\t------------------------------------"); $monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out); #4 $display("\t\t------------------------------------"); end initial begin i0=1; i1=0; i2=1; i3=1; #1 s0=0; s1=0; #1 s0=1; s1=0; #1 s0=0; s1=1; #1 s0=1; s1=1; #1 $stop; end endmodule Demultiplexer: // Module Name: Dux1to4 module Dux1to4(in, s0, s1, out0, out1, out2, out3); input in; input s0; input s1; output out0; output out1; output out2; output out3; wire s0n,s1n; not(s0n,s0); not(s1n,s1); and (out0,in,s1n,s0n); and (out1,in,s1n,s0); and (out2,in,s1,s0n); and (out3,in,s1,s0); endmodule // Module Name: stimulus.v module stimulus_v; // Inputs
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Output: # # # # # # # # # # #
1to4 Demultiplexer ----------------------------------------------Input=1 ----------------------------------------------Status Output ----------------------------------------------{0,0} 1000 {0,1} 0100 {1,0} 0010 {1,1} 0001 ---------------------------------------------
reg in; reg s0; reg s1; // Outputs wire out0; wire out1; wire out2; wire out3; // Instantiate the Unit Under Test (UUT) Dux1to4 uut ( .in(in), .s0(s0), .s1(s1), .out0(out0), .out1(out1), .out2(out2),
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.out3(out3) ); initial begin $display("\t\t 1to4 Demultiplexer"); $display("\t\t------------------------------------"); #1 $display("\t\t\t\tInput=%b",in); $display("\t\t------------------------------------"); $display("\t\tStatus\t\t\t\tOutput"); $display("\t\t------------------------------------"); $monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3); #4 $display("\t\t------------------------------------"); end initial begin in=1; #1 s1=0;s0=0; #1 s1=0;s0=1; #1 s1=1;s0=0; #1 s1=1;s0=1; #1 $stop; end endmodule 14.5 RESULT:
Thus the source code to implement Multiplexer & Demultiplexer circuits was written and executed using Verilog HDL.
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15.CARRY LOOK AHEAD ADDER 15.1Aim To design and study the circuit of Carry Look ahead adder 15.2 Circuit Diagram
15.3 Theory A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple carry adderfor which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits (see adder for detail on ripple carry adders). The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits.
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Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this. In the descriptions below, the word digit can be replaced by bit when referring to binary addition. The addition of two 1-digit inputs A and B is said to generate if the addition will always carry, regardless of whether there is an input carry (equivalently, regardless of whether any less significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition of the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless of whether the ones digit carries (in the example, the ones digit does not carry (2+7=9)). In the case of binary addition, we write if generates if and only if both A and B are 1. If
to represent the binary predicate that is true if and only generates, we have:
The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry (equivalently, when the next less significant digit in the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones were to carry (which in this example, it does not). Note that propagate and generate are defined with respect to a single digit of addition and do not depend on any other digits in the sum. In the case of binary addition, of A or B is 1. If we write if and only if propagates if and only if at least one to represent the binary predicate that is true
propagates, we have:
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Sometimes a slightly different definition of propagate is used. By this definition A + B is said to propagate if the addition will carry whenever there is an input carry, but will not carry if there is no input carry. It turns out that the way in which generate and propagate bits are used by the carry lookahead logic, it doesn't matter which definition is used. In the case of binary addition, this definition is expressed by:
For binary arithmetic, or is faster than xor and takes fewer transistors to implement. However, for a multiple-level carry lookahead adder, it is simpler to use .
Given these concepts of generate and propagate, when will a digit of addition carry? It will carry precisely when either the addition generates or the next less significant bit carries and the addition propagates. Written in boolean algebra, with and and the carry bit of digit i, the propagate and generate bits of digit i respectively,
Result Thus carry lookahead adder was designed and studied.
100
16. 2-BIT MULTIPLIER 16.1 Aim To design and study the circuit of 2-bit multiplier 16.2 Circuit Diagram
Theory A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. A
binary computer does exactly the same, but with binary numbers. In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is
101
much easier than in decimal, as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two binary numbers comes down to calculating partial products (which are 0 or the first number), shifting them left, and then adding them together (a binary addition, of course): 1011 x 1110 ====== 0000 1011 the left) 1011 to the left) + 1011 to the left) ========= 10011010 (this is 11 in binary) (this is 14 in binary) (this is 1011 x 0) (this is 1011 x 1, shifted one position to (this is 1011 x 1, shifted two positions (this is 1011 x 1, shifted three positions (this is 154 in binary)
Result Thus 2-bit multiplier is designed
102

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EC2207 / Digital Electronics Lab

KODAIKANAL INSTITUTE OF TECHNOLOGY

ANNA UNIVERSITY 2008 REGULATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.

EC2207 DIGITAL ELECTRONICS LABORATORY

Dept of Electronics & Communication Engineering