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Pedroni MITPress 1stedition SolutionSamples

This document provides solutions to selected exercises from the textbook "Circuit Design with VHDL" by Volnei A. Pedroni. The solutions address exercises on topics like multiplexers, data types, operators, adders, encoders, and flip-flops. Code snippets are included with the solutions along with any relevant simulation results.

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Trần Anh Dũng
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0% found this document useful (0 votes)
189 views14 pages

Pedroni MITPress 1stedition SolutionSamples

This document provides solutions to selected exercises from the textbook "Circuit Design with VHDL" by Volnei A. Pedroni. The solutions address exercises on topics like multiplexers, data types, operators, adders, encoders, and flip-flops. Code snippets are included with the solutions along with any relevant simulation results.

Uploaded by

Trần Anh Dũng
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CircuitDesignwithVHDL

1stedition
VolneiA.Pedroni
MITPress,2004
Bookweb:www.vhdl.us

SolutionstoSelectedExercises

Selectedexercises:2.1,3.2,4.1,5.4,5.6,6.4,6.17,7.6,8.2,8.6,10.2,11.1,12.4

Problem2.1:Multiplexer

-------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------ENTITY mux IS
PORT (a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
c: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END mux;
-------------------------------------------------ARCHITECTURE example OF mux IS
BEGIN
PROCESS (a, b, sel)
BEGIN
IF (sel="00") THEN
c <= "00000000";
ELSIF (sel="01") THEN
c <= a;
ELSIF (sel="10") THEN
c <= b;
ELSE
c <= (OTHERS => 'Z'); --or c<="ZZZZZZZZ";
END IF;
END PROCESS;
END example;
--------------------------------------------------

Problem3.2:Dealingwithdatatypes

First,recallfigure3.1,whichshowsfourtypesofdatastructures.Fromit,weconcludethefollowing:
a:ascalaroftypeBIT
b:ascalaroftypeSTD_LOGIC
x:a1Darray(avector)oftypeARRAY1,whose8individualelementsareoftypeSTD_LOGIC

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

y:a2Darray(amatrix)oftypeARRAY2,whose4x8=32individualelementsareoftypeSTD_LOGIC
w:a1Dx1Darray(anothermatrix)oftypeARRAY3,whose4individual8elementvectorsareoftypeARRAY1
z:another1Darray(anothervector)whose8individualelementsareagainoftypeSTD_LOGIC
Therefore:

a <= x(2);

a:scalar,typeBIT
x(2):scalar,typeSTD_LOGIC
Assignmentisillegal(typemismatch)

b <= x(2);

b:scalar,typeSTD_LOGIC
x(2):scalar,typeSTD_LOGIC
Assignmentislegal

b <= y(3,5);

b:scalar,typeSTD_LOGIC
y(3,5):scalar,typeSTD_LOGIC,withvalidindexing
Assignmentislegal

b <= w(5)(3);

b:scalar,typeSTD_LOGIC
w(5,3):scalar,typeSTD_LOGIC,but5isoutofbounds
Assignmentisillegal

y(1)(0) <= z(7);

y(1)(0):scalar,typeSTD_LOGIC,butindexingisincorrectbecauseyis2D(itshouldbey(1,0))
z(7):scalar,typeSTD_LOGIC
Assignmentisillegal

x(0) <= y(0,0);

x(0):scalar,typeSTD_LOGIC
y(0,0):scalar,typeSTD_LOGIC,validindexing
Assignmentislegal

x <= 1110000;

x:8bitvector(1D)
Assignmentwouldbelegalifitcontained8valuesinsteadof7

a <= 0000000;

a:scalar,socanonlyhaveonebit
Assignmentisillegal

y(1) <= x;

y(1):inprinciple,an8elementvector,extractedfroma2Dmatrix,whoseindividualelementsareoftype
STD_LOGIC;however,theindexing(slicing)ofyisnotvalid,becausethematrixis2D,not1Dx1D
x:an8elementvectoroftypeARRAY1
Assignmentisillegal(invalidslicing+typemismatch)

w(0) <= y;

w(0):row0ofa1Dx1Dmatrix,whichisan8elementvectoroftypeARRAY1
y:a4x8(2D)matrix
Assignmentisillegal(size+typemismatches)

w(1) <= (7=>'1', OTHERS=>'0');

w(1):row1ofa1Dx1Dmatrix
Assignmentislegal(w(1)<=10000000)

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

y(1) <= (0=>'0', OTHERS=>'1');

y(1):inprinciple,row1ofamatrix,buttheindexingisinvalid,becausethematrixis2D,not1Dx1D
Assignmenty(1)<=11111110isillegal

w(2)(7 DOWNTO 0) <= x;

w(2)(7DOWNTO0):row2ofa1Dx1Dmatrix,whichisan8elementvectoroftypeARRAY1
x:an8elementvectoroftypeARRAY1
Assignmentislegal
Note:w(2)<=xwouldbefinetoo

w(0)(7 DOWNTO 6) <= z(5 DOWNTO 4);

w(0)(7DOWNTO6):theleftmost2elementsofrow0ofa1Dx1Dmatrix,beingeachrowan8element
vectoroftypeARRAY1
z(5DOWNTO4):2elementsofan8elementSTD_LOGIC_VECTOR
Assignmentisillegal(typemismatch)

x(3) <= x(5 DOWNTO 5);

x(3):ascalaroftypeSTD_LOGIC
x(5DOWNTO5):alsoascalaroftypeSTD_LOGIC
Assignmentislegal

b <= x(5 DOWNTO 5)

b:ascalaroftypeSTD_LOGIC
x(5DOWNTO5):alsoascalaroftypeSTD_LOGIC
Assignmentislegal

y <= ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), 10000001);

yisa2Dmatrix
Assignmentislegal.
Note:Sinceyis2D,someoldercompilersmightnotacceptthevectorlikeassignmentsabove,thusrequiringthe
assignmenttobemadeelementbyelement(withGENERATE,forexample).
Note:Theassignmentbelowisalsolegal.
y <= (('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('1','0','0','0','0','0','0','1'));

z(6) <= x(5);

z(6):scalaroftypeSTD_LOGIC
x(5):alsoascalaroftypeSTD_LOGIC(thoughasavectorxisoftypeARRAY1,asascalar(basetype)itisSTD_LOGIC)

z(6 DOWNTO 4) <= x(5 DOWNTO 3);

z(6DOWNTO4):3elementvectoroftypeSTD_LOGIC_VECTOR
x(5DOWNTO3):3elementvectoroftypeARRAY1
Assignmentisillegal(typemismatch)

z(6 DOWNTO 4) <= y(5 DOWNTO 3);

Theindexingofyisinvalid(slicing2Darrayisgenerallynotallowed)
Assignmentisillegal

y(6 DOWNTO 4) <= x(3 TO 5);

Theindexingofyisinvalid(slicing2Darrayisgenerallynotallowed)
Indexingofxisinthewrongdirection
Assignmentisillegal

y(0, 7 DOWNTO 0) <= z;

y(0,7DOWNTO0):inprinciple,row0ofamatrix,butslicing2Darraysisgenerallynotsupported

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

Assignmentisillegal

w(2,2) <= '1';

wis1Dx1D,soindexingshouldbew(2)(2)
Assignmentisillegal

Problem4.1:Operators

x1 <= a & c;
--x1 = 10010
x2 <= c & b;
--x2 = 00101100
x3 <= b XOR c;
--x3 = 1110
x4 <= a NOR b(3);
--x4 = '0'
x5 <= b sll 2;
--x5 = 0000
x6 <= b sla 2;
--x6 = 0000
x7 <= b rol 2;
--x7 = 0011;
x8 <= a AND NOT b(0) AND NOT c(1); --x8 = '0'
d <= (5=>'0', OTHERS=>'1');
--d = 11011111

Problem5.4:Unsignedadder

Inthesolutionbelow,theinputsandoutputsareconsideredtobeoftypeSTD_LOGIC(industrystandard).
Simulationresultsareincludedafterthecode.

-----------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; --allows arith. operations w/ STD_LOGIC
-----------------------------------------------------------------------ENTITY adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sum: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cout: OUT STD_LOGIC);
END adder;
-----------------------------------------------------------------------ARCHITECTURE adder OF adder IS
SIGNAL long_a, long_b, long_sum: STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
long_a <= '0' & a;
long_b <= '0' & b;
long_sum <= long_a + long_b;
sum <= long_sum(7 DOWNTO 0);
cout <= long_sum(8);
END adder;
------------------------------------------------------------------------

SimulationresultsforProblem5.4.

Problem5.6:BinarytoGraycodeconverter

Thegraycodewordg(N1:0)correspondingtoaregularbinarycodewordb(N1:0)canbeobtainedasfollows:
Fori=N1:g(i)=b(i)
Fori=N20:g(i)=b(i)b(i+1)

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

AcorrespondinggenericVHDLcode ispresentedbelow,followedbysimulationresultsforN=4.

--------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------ENTITY gray_encoder IS
GENERIC (N: INTEGER := 4);
PORT (b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
g: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END gray_encoder;
--------------------------------------------------------ARCHITECTURE gray_encoder OF gray_encoder IS
BEGIN
g(N-1) <= b(N-1);
g(N-2 DOWNTO 0) <= b(N-2 DOWNTO 0) XOR b(N-1 DOWNTO 1);
END gray_encoder;
---------------------------------------------------------

SimulationresultsforProblem5.6.

Problem6.4:Genericfrequencydivider

----Clock frequency is divided by n----------LIBRARY ieee;


USE ieee.std_logic_1164.all;
---------------------------------------------ENTITY clock_divider IS
GENERIC (n: POSITIVE := 7);
PORT (clkin: IN STD_LOGIC;
clkout: OUT STD_LOGIC);
END ENTITY;
---------------------------------------------ARCHITECTURE clock_divider OF clock_divider IS
BEGIN
PROCESS (clkin)
VARIABLE count: INTEGER RANGE 0 TO n;
BEGIN
IF (clkin'EVENT AND clkin='1') THEN
count := count + 1;
IF (count=n/2) THEN
clkout <= '1';
ELSIF (count=n) THEN
clkout <= '0';
count := 0;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
----------------------------------------------

SimulationresultsforN=4inProblem6.4.

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

Problem6.17:DFF

Architecture1:AtrulyDtypeflipflopwithasynchronousreset(sameasinExample6.1).

Architecture2:Onlytheclockappearsinthesensitivitylist,causingtheresettobesynchronous.

Architecture3: clkEVENTisnotassociatedwithatest(ANDclk=1,forexample).Somecompilersmightassumea
defaulttest(ANDclk=1),whileotherswillsimplyhalt.Thetestshouldalwaysbeexplicitlywritten.

Architecture4: Herethecontentsofsections6.10and7.5arehelpful.Noticethatnosignalassignmentismadeat
thetransitionofanothersignal,signifyingthat,inprinciple,noflipflopiswanted(thusacombinationalcircuit).
However,onlyoneoftheinputsignalsappearsinthesensitivitylist,andanincompletetruthtableforqisspecifiedin
thecode,causingtheinferenceofalatchtoholdthevalueofq(apseudocombinationalcircuit).

Architecture5:Thesituationhereisevenmoreawkwardthanthatabove.Besidesgeneratingagainalatch,changes
ofdalsocausetheprocesstoberun.Theresultisacircuitveryunlikelytobeofanyinterest.

Problem7.6:Genericaddressdecoder

Inthesolutionbelow,allportsareconsideredtobeoftypeSTD_LOGIC(industrystandard).Simulationresults(for
N=3)areincludedafterthecode.Regardingtheglitchesinthesimulationresults,recallthattheyarenormalin
combinationalcircuitswhenasignaldependsonmultiplebits,becausethevaluesofsuchbitsdonotchangeallat
exactlythesametime.

---------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
---------------------------------------------------------ENTITY address_decoder IS
GENERIC (N: POSITIVE := 3); --# of input bits
PORT (ena: IN STD_LOGIC;
address: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
wordline: OUT STD_LOGIC_VECTOR(2**N-1 DOWNTO 0));
END ENTITY;
---------------------------------------------------------ARCHITECTURE address_decoder OF address_decoder IS
BEGIN
PROCESS (ena, address)
VARIABLE internal: STD_LOGIC_VECTOR(2**N-1 DOWNTO 0);
VARIABLE addr: NATURAL RANGE 0 TO 2**N-1;
BEGIN
addr := CONV_INTEGER(address);
internal := (OTHERS => '1');
IF (ena='1') THEN
internal(addr) := '0';
END IF;
wordline <= internal;
END PROCESS;
END ARCHITECTURE;
---------------------------------------------------------

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

SimulationresultsforProblem7.6.

Problem8.2:Signalgenerator#1

Thesolutionthatfollowsisbasedonthearbitrarysignalgeneratordesigntechniqueintroducedinchapter15of[1].
Thecorrespondingsignalsaredepictedinthefigurebelow.

[1]V.A.Pedroni,DigitalElectronicsandDesignwithVHDL,Elsevier/MorganKaufmann,2008.

DetailsregardingthestatesmachinesofProblem8.2.

Inthisexercise,out1isverysimpletogenerate,becauseallofitstransitionsareatthesame(positive)clockedge.
However,thesameisnottrueforout2,whichcontainstransitionsatbothclockedges.Consequently,forthelatter,
thetechniqueintroducedin[1]isveryhelpful(indeed,theweirderthesignaltobegenerated,themoreusefulthat
approachis).Coincidently,theshapeofout2inthisexerciseisnotsubjecttoglitchesduringsignalconstruction,soto
betterillustratetheuseofthattechniqueaslightmodificationwillbeintroduced(seethewaveformrightbelowclk
inthefigureabove).Observethatnowxissubjecttoglitches,makingtheproblemamoregeneralcase.

TwoFSMsareemployedtocreatethedesiredsignal,eachassociatedwithamultiplexer.ThepairFSM1MUX1is
responsibleforgeneratingthesignal(possiblywithglitches),whilethepairFSM2MUX2isresponsibleforcleaningit
(recallthatinasignalgeneratorglitchesareneveracceptable).Asshowninthefigure,FSM1operatesatthepositive
clockedge,whileFSM2operatesatthenegativetransition.Thestates(forbothmachines)arecalledA,B,C,andD.

AcorrespondingVHDLcodeisshownbelow,followedbysimulationresults.Observeinthelattertheexpected
glitchesinx,whichdisappeariny.

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises
-------------------------------------------------------ENTITY signal_generator IS
PORT (clk: IN BIT;
x: BUFFER BIT;
y: OUT BIT);
END ENTITY;
-------------------------------------------------------ARCHITECTURE signal_generator OF signal_generator IS
TYPE state IS (A, B, C, D);
SIGNAL pr_state1, nx_state1: state;
SIGNAL pr_state2, nx_state2: state;
ATTRIBUTE enum_encoding: STRING;
ATTRIBUTE enum_encoding OF state: TYPE IS "sequential";
BEGIN
-----Lower section of FSM1:----PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
pr_state1 <= nx_state1;
END IF;
END PROCESS;
-----Upper section of FSM1:----PROCESS (pr_state1, clk)
BEGIN
CASE pr_state1 IS
WHEN A =>
x <= '1';
nx_state1 <= B;
WHEN B =>
x <= NOT clk;
nx_state1 <= C;
WHEN C =>
x <= '1';
nx_state1 <= D;
WHEN D =>
x <= '0';
nx_state1 <= A;
END CASE;
END PROCESS;
-----Lower section of FSM2:----PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='0') THEN
pr_state2 <= nx_state2;
END IF;
END PROCESS;
-----Upper section of FSM2:----PROCESS (pr_state1, pr_state2, x)
BEGIN
nx_state2 <= pr_state1; --synchronism
CASE pr_state2 IS
WHEN A =>
y <= x;
WHEN B =>
y <= '1';
WHEN C =>
y <= x;
WHEN D =>
y <= x;
END CASE;
END PROCESS;
END ARCHITECTURE;
-------------------------------------------------------

SimulationresultsforProblem8.2.

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

Problem8.6:SignalgeneratorofProblem8.2withoutFSMapproach

Physicalcircuits,design,andoperationofsequentialcircuitsaredescribedinchapter14of[1].Thesolutionthat
followsisbasedonthetheorypresentedthere.Thecorrespondingsignalsaredepictedinthefigurebelow.

SignalsemployedinthesolutionofProblem8.6.

Inthiscase(figureabove),threeauxiliarysignals(a,b,c)arecreated,fromwhichout1andout2arethenderived
usingconventionalgates.Asdescribedinchapter14of[1],thefundamentalpointhereistoguaranteethatthe
outputsarenotpronetoglitches.Toguaranteeglitchfreeoutputs,allthreeauxiliarysignalsareregistered(i.e.,
storedinDFFs);consequently,giventhatnotwosignalsthataffectthegatesoutputschangeatthesameclockedge,
glitchfreeoutputsareautomaticallygenerated.AcorrespondingVHDLfollows,alongwithsimulationresults.

---------------------------------------------------ENTITY signal_generator IS
PORT (clk: IN BIT;
out1, out2: OUT BIT);
END ENTITY;
---------------------------------------------------ARCHITECTURE signal_generator OF signal_generator IS
SIGNAL a, b, c: BIT;
SIGNAL counter: INTEGER RANGE 0 TO 3;
BEGIN
----Creating a counter:-----------PROCESS (clk)
VARIABLE count: INTEGER RANGE 0 TO 4;
BEGIN
IF (clk'EVENT AND clk='1') THEN
count := count + 1;
IF (count=4) THEN
count := 0;
END IF;
END IF;
counter <= count;
END PROCESS;
----Generating signal a:----------PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (counter=0) THEN
a <= '1';
ELSE
a <= '0';
END IF;
END IF;
END PROCESS;
----Generating signal b:----------PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='0') THEN
IF (counter=1) THEN
b <= '1';
ELSE
b <= '0';
END IF;

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises
END IF;
END PROCESS;
----Generating signal c:----------PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (counter=3) THEN
c <= '1';
ELSE
c <= '0';
END IF;
END IF;
END PROCESS;
----Generating the outputs:-------out1 <= c;
out2 <= (a AND b) OR c;
END ARCHITECTURE;
----------------------------------------------------

SimulationresultsforProblem8.6.

Problem10.2:Carryrippleadderconstructedwithcomponents
-----The component (full-adder unit):----------ENTITY FAU IS
PORT (a, b, cin: IN BIT;
s, cout: OUT BIT);
END FAU;
-----------------------------------------------ARCHITECTURE full_adder OF FAU IS
BEGIN
s <= a XOR b XOR cin;
cout <= (a AND b) OR (a AND cin) OR (b AND cin);
END full_adder;
----------------------------------------------------Main code:------------------------------------------ENTITY carry_ripple_adder IS
GENERIC (N : INTEGER := 8); --number of bits
PORT (a, b: IN BIT_VECTOR(N-1 DOWNTO 0);
cin: IN BIT;
s: OUT BIT_VECTOR(N-1 DOWNTO 0);
cout: OUT BIT);
END carry_ripple_adder;
----------------------------------------------------------ARCHITECTURE structural OF carry_ripple_adder IS
SIGNAL carry: BIT_VECTOR(N DOWNTO 0);
COMPONENT FAU IS
PORT (a, b, cin: IN BIT; s, cout: OUT BIT);
END COMPONENT;
BEGIN
carry(0) <= cin;
generate_adder: FOR i IN a'RANGE GENERATE
adder: FAU PORT MAP (a(i), b(i), carry(i), s(i), carry(i+1));
END GENERATE;
cout <= carry(N);
END structural;
-----------------------------------------------------------

10

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

11

Problem11.1:ConversiontoSTD_LOGIC_VECTOR

AVHDLcodeforthisexerciseisshownbelow.Totestit,justajumperfromtheinputtotheoutputwas
used,inwhichcasethecompilermustgiveequationsofthetypeoutput(i)=input(i),fori=0,1,,N1.Asimilar
functioncanbefoundinthestandardpackagestd_logic_arith,availableinthelibraryofyourVHDLsynthesis
software.Notethatinthesolutionbelowthefunctionwaslocatedinthemaincode;toinstallitinapackage,just
followtheinstructioninchapter11(seeexample11.4,forexample).

------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------ENTITY data_converter IS
GENERIC (N: NATURAL := 4); --number of bits
PORT (input: IN INTEGER RANGE 0 TO 2**N-1;
output: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END data_converter;
------------------------------------------------------ARCHITECTURE data_converter OF data_converter IS
SIGNAL x: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
------------------FUNCTION conv_std_logic(arg: INTEGER; size: POSITIVE)
RETURN STD_LOGIC_VECTOR IS
VARIABLE temp: INTEGER RANGE 0 TO 2**size-1;
VARIABLE result: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
BEGIN
temp := arg;
FOR i IN result'RANGE LOOP
IF (temp>=2**i) THEN
result(i) := '1';
temp := temp - 2**i;
ELSE
result(i) := '0';
END IF;
END LOOP;
RETURN result;
END conv_std_logic;
------------------BEGIN
output <= conv_std_logic(input, N);
END data_converter;
-------------------------------------------------------

Problem12.4:GeneralpurposeFIRfilter

Inthisexample,onlyintegersareemployed.Ablockdiagramforthecircuitisshownbelow.Itcontainstwoshift
registers,whichstoretheinputvalues(x)andthefiltercoefficients(c).Itcontainsalsoaregistertostorethe
accumulated(acc)value,producingthefilteroutput(y).Thetotalnumberoftapsisn,withmbitsusedtorepresentx
andc,and2mbitsfortheaftermultiplicationpaths.Henceatotalof2m(n+1)flipflopsarerequired.Observethat
thetapsareallalike,soCOMPONENTcanbeusedtoeasilyimplementthiscircuit.Aslightlymoredifficult(non
structural)solutionisshownbelow;thestructuraloption(withCOMPONENT)islefttothereader.Notethatthecode
includesoverflowcheck.Simulationresultsarealsoincluded.

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

----------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; --package needed for SIGNED
----------------------------------------------------------------ENTITY FIR IS
GENERIC (n: INTEGER := 4; --number of coefficients
m: INTEGER := 4); --number of bits per coefficient
PORT (clk, rst: IN STD_LOGIC;
load: STD_LOGIC; --to enter new coefficient values
run: STD_LOGIC;
--to compute the output
x_input, coef_input: IN SIGNED(m-1 DOWNTO 0);
y: OUT SIGNED(2*m-1 DOWNTO 0);
overflow: OUT STD_LOGIC);
END FIR;
----------------------------------------------------------------ARCHITECTURE FIR OF FIR IS
TYPE internal_array IS ARRAY (1 TO n) OF SIGNED(m-1 DOWNTO 0);
SIGNAL c: internal_array; --stored coefficients
SIGNAL x: internal_array; --stored input values
BEGIN
PROCESS (clk, rst)
VARIABLE prod, acc: SIGNED(2*m-1 DOWNTO 0) := (OTHERS=>'0');
VARIABLE sign_prod, sign_acc: STD_LOGIC;
BEGIN
--Reset:--------------------------------IF (rst='1') THEN
FOR i IN 1 TO n LOOP
FOR j IN m-1 DOWNTO 0 LOOP
x(i)(j) <= '0';
END LOOP;
END LOOP;
--Shift registers:----------------------ELSIF (clk'EVENT AND clk='1') THEN
IF (load='1') THEN
c <= (coef_input & c(1 TO n-1));
ELSIF (run='1') THEN
x <= (x_input & x(1 TO n-1));
END IF;
END IF;
--MACs and output (w/ overflow check):--acc := (OTHERS=>'0');
FOR i IN 1 TO n LOOP
prod := x(i)*c(i);
sign_prod := prod(2*m-1);
sign_acc := acc(2*m-1);
acc := prod + acc;
IF (sign_prod=sign_acc AND acc(2*m-1)/=sign_acc) THEN
overflow <= '1';
ELSE
overflow <= '0';
END IF;
END LOOP;
IF (clk'EVENT AND clk='1') THEN
y <= acc;
END IF;
END PROCESS;
END FIR;
-----------------------------------------------------------------

12

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

SimulationresultsforProblem12.4.

13

CircuitDesignwithVHDL,1stedition,VolneiA.Pedroni,MITPress,2004SolutionstoSelectedExercises

14

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