EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 1

EE247
Lecture 13
Data Converters
Data converter testing (continued)
Dynamic tests
Spectral testing (brief review)
Relationship between: DNL & SNR, INL & SFDR
Effective number of bits (ENOB)
D/A converters: Various Architectures
Resistor string DACs
Serial charge redistribution DACs
Charge scaling DACs
R-2R type DACs
Current based DACs
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 2
Data Converter Testing
(So Far)
Data Converters
Static Tests:
Measuring DNL & INL
Servo-loop
Code density testing (histogram testing)
Dynamic tests:
Spectral testingReveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
Direct Discrete Fourier Transform (DFT) based
measurements utilizing sinusoidal signals
DFT measurements including windowing
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 3
Spectral Testing: DFT Considerations
Integer Cycles versus Windowing
Sinusoidal inputs with integer number of cycles within the
observation window:
Signal energy for a single sinusoid falls into single DFT bin
Requires careful choice of f
in
:
# of cycles integer
N/cycles = f
s
/ f
in
non-integer (choose # of cycles integer and prime #)
Ideal for simulations
Measurements need to lock f
in
to f
s
(PLL)- not always possible
Windowing
No restrictions on f
in
no need to have the signal locked to f
s
Good for measurements w/o having the capability to lock f
in
to f
s
Signal energy and its harmonics distributed over several DFT bins
handle smeared-out harmonics with care!
Requires more samples for a given accuracy
Note that no windowing is equal to windowing with a rectangular
window!
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 4
Matlab Example:
ADC Spectral Testing
ADC with B bits
Full scale input level=2
B = 10;
delta = 2/2^B;
%sampled sinusoid
y = cos(2*pi*fx/fs*[0:N-1]);
%quantize samples to delta=1LSB
y=round(y/delta)*delta;
s = abs(fft(y)/N*2);
f = (0:length(s)-1) / N;
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 5
ADC Output Spectrum
N=2
11
Cycles=53 (integer & prime)
N/Cycles= f
s
/f
x
f
s
/f
x
=38.64. (non-integer)
Input signal bin:
Bx @ bin # (N * f
x
/f
s
+ 1)
(Matlab arrays start at 1)
A
signal
= 0dBFS
What is the SNR?
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
N=2048
A
m
p
l
i
t
u
d
e

[
d
B
F
S
]
f /f
s
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 6
Simulated ADC Output Spectrum
Noise bins: all except signal bin
bx = N*fx/fs + 1;
As = 20*log10(s(bx))
%set signal bin to 0
s(bx) = 0;
An = 10*log10(sum(s.^2))
SNR = As - An
MatlabSNR = 62dB (10 bits)
Computed SQNR =
6.02xN+1.76dB=61.96dB
Note: In a real circuit including thermal/flicker noise the measured
total noise is the sum of quantization & noise associated with the circuit
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
N=2048
A
m
p
l
i
t
u
d
e

[
d
b
F
S
]
f /f
s
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 7
Why is Noise Floor Not @ -62dB ?
DFT bins act like an analog
spectrum analyzer with
bandwidth per bin of f
s
/N
Assuming noise is uniformly
distributed, noise per bin:
(Total noise)/N/2
The DFT noise floor wrt total
noise:
-10log
10
(N/2) [dB]
below the actual noise floor
For N=2048:
-10log
10
(N/2) =-30 [dB]
0 0.1 0.2 0.3 0.4 0.5
-120
-40
-20
0
A
m
p
l
i
t
u
d
e

[
d
b
F
S
]
N=2048
30dB
-100
-80
-60
f /f
s
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 8
DFT Plot Annotation
Need to annotate DFT plot such that actual
noise floor can be readily computed by one of
these 3 ways:
1. Specify how many DFT points (N) are used
2. Shift DFT noise floor by 10log
10
(N/2) [dB]
3. Normalize to "noise power in 1Hz bandwidth
then noise is in the form of power spectral
density
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 9
Example:10Bit ADC FFT
For a real 10bit ADC
spectral test results:
SNR=55.9dB
A 3
rd
harmonic is barely
visible
Is better view of distortion
component possible?
-140
-120
-100
-80
-60
-40
-20
0
A
m
p
l
i
t
u
d
e


[

d
B
F
S

]
N = 4096
SNR = 55.9dB
SDR = 76.4dB
SNDR = 55.1dB
SFDR = 77.3dB
0 0.1 0.2 0.3 0.4 0.5
Frequency [ f / f
s
]
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 10
Example:10Bit ADC FFT
Increasing N, the number of
samples (and hence the
measurement or simulation
time) distributes the noise
over larger # of bins
Larger # of bins less
noise power per bin (total
noise stays constant)
Note the 3
rd
harmonic is
clearly visible when N is
increased
-150
-100
-50
0
A
m
p
l
i
t
u
d
e


[

d
B
F
S

]
N = 65536
SNR = 55.9dB SDR = 77.9dB
SNDR = 55.2dB SFDR = 78.5dB
0
0.1 0.2 0.3 0.4 0.5
Frequency [ f / f
s
]
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 11
Spectral Performance Metrics
ADC Including Non-Idealities
Signal S
DC
Distortion D
Noise N
Ideal ADC adds:
Quantization noise
Real ADC typically adds:
Thermal and flicker noise
Harmonic distortion
associated with circuit
nonlinearities
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 12
ADC Spectral Performance Metrics
SNR
Signal S
DC
Distortion D
Noise N
Signal-to-noise ratio
SNR = 10log[(Signal Power) /
(Noise Power)]
In Matlab: Noise power includes
power associated with all bins
except:
DC
Signal
Signal harmonics
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 13
ADC Spectral Performance Metrics
SDR & SNDR & SFDR
SDRSignal-to-distortion ratio
= 10log[(Signal Power) /
(Total Distortion Power)]
SNDRSignal-to-(noise+distortion)
= 10log[S / (N+D)]
SFDRSpurious-free dynamic
range
= 10log[(Signal )/
(Largest Harmonic)]
Typically SFDR > SDR
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 14
Harmonic Components
At multiples of f
x
Aliasing:
f
signal
= f
x
= 0.18 f
s
f
2
= 2 f
0
= 0.36 f
s
f
3
= 3 f
0
= 0.54 f
s
0.46 f
s
f
4
= 4 f
0
= 0.72 f
s
0.28 f
s
f
5
= 5 f
0
= 0.90 f
s
0.10 f
s
f
6
= 6 f
0
= 1.08 f
s
0.08 f
s
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 15
Relationship INL & SFDR/SNDR
ADC Transfer Curve
INL Input
Output
Quadratic shaped transfer function:
Gives rise to even order harmonics
Real
INL Input
Output
Cubic shaped transfer function:
Gives rise to odd order harmonics
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 16
Frequency Spectrum versus INL & DNL
-0.03
0
D
N
L


[
L
S
B
]
100 200 300 400 500 600 700 800 9001000
-2
-1
0
1
2
bin #
I
N
L


[
L
S
B
]
Good DNL and poor INL
suggests distortion
INLNot fully symmetric
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 17
Relationship INL & SFDR/SNDR
Nature of harmonics depend on "shape" of
INL curve
Rule of Thumb: SFDR ~ 20log(2
B
/INL)
E.g. 1LSB INL, 10bSFDR~60dB
Beware, this is of course only true under the
same conditions at which the INL was taken,
i.e. typically low input signal frequency
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 18
SNR Degradation due to DNL
Uniform quantization error pdf was assumed for ideal quantizer
over the range of: +/- A/2
Let's now add uniform DNL over +/- A/2 and repeat math...
Joint pdf for two uniform pdfs Triangular shape
[Source: Ion Opris]
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 19
SNR Degradation due to DNL
To find total noise Integrate triangular pdf:
Compare to ideal quantizer:
Error associated with DNL reduces overall SNR
6
) 1 ( 2
2
0
2
2
A
=
A
=
}
A +
de
e
e e
3dB
[dB] 25 . 1 02 . 6 = N SNR
12
2 2 /
2 /
2
2
A
=
A
=
}
A +
A
de
e
e
[dB] 76 . 1 02 . 6 + = N SNR
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 20
SNR Degradation due to DNL
More general case:
Uniform quantization error (ideal) 0.5A
Uniform DNL error DNL [LSB]
Convolution yields trapezoid shaped joint pdf
SQNR becomes:
3 12
2
2
2
1
2 2
2
DNL
SQNR
N
+
A
|
|
.
|

\
|
A
=
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 21
SNR Degradation due to DNL
Degradation in dB:
0 0.2 0.4 0.6 0.8 1
0
2
4
6
8
SNR
Degradation
[dB]
|DNL| [LSB]
(
(
(
(

+
=
3 12
1
8
1
log 10 76 . 1 deg _
2
DNL
SQNR
Valid only for cases where
no missing codes
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 22
Summary
INL & SFDR - DNL & SNR
INL & SFDR
Type of distortion depends on
"shape" of INL
Rule of Thumb:
SFDR ~ 20 log(2
B
/INL)
E.g. 1LSB INL, 10b
SFDR~60dB
DNL & SNR
Assumptions:
DNL pdf uniform
No missing codes
3 12
2
2
2
1
2 2
2
DNL
SQNR
N
+
A
|
|
.
|

\
|
A
=
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 23
Uniform DNL?
DNL distribution of measurement for 12-bit ADC test chip
Not quite uniform...
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
0
50
100
150
200
250
DNL
#

o
f

o
c
c
u
r
r
e
n
c
e
s
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 24
Effective Number of Bits (ENOB)
Is a 12-Bit converter with 68dB SNDR really a 12-Bit
converter?
Effective Number of Bits (ENOB)# of bit of an ideal
ADC with the same SQNR as the SNDR of the non-
ideal ADC
Above ADC is a 12bit ADC with ENOB=11bits
Bits 0 . 11
02 . 6
76 . 1 68
dB 02 . 6
dB 76 . 1
=

=
SNDR
ENOB
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 25
ENOB
At best, we get "ideal" ENOB only for
negligible thermal noise, DNL, INL
Low noise design is costly 4x penalty in
power per (ENOB-) bit or 6dB extra SNDR
Rule of thumb for good performance /power
tradeoff: ENOB < N-1
EECS 247 Lecture 12: Data Converters- Testing 2010 H. K. Page 26
ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on
Selected Areas in Communications, pp. 539-50, April 1999
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 27
Converter Testing
Practical Aspects
Equipment
requirements
Pitfalls
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 28
Direct ADC-DAC Test
Issues to beware of:
Linearity of the signal generator output has to be much better than ADC linearity
Spectrum analyzer nonlinearities
May need to build/purchase filters to address one or both above
problems
Clock generator signal jitter
V
in
Spectrum
Analyzer
Signal
Generator
Clock
Generator
Device Under Test (DUT)
Notch
Filter
Bandpass
or
Lowpass
Filter
ADC DAC
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 29
Example: State-Of-The-Art ADC (2001)
Testing a high performance converter may be just as
challenging as designing it!
Key to success is to be aware of test setup and
equipment limitations
[W. Yang et al., "A 3-V 340-mW
14-b 75-Msample/s CMOS ADC
with 85-dB SFDR at Nyquist
input," IEEE J. of Solid-State
Circuits, Dec. 2001]
0.35micron technology & 3V Supply
ENOB=12bit
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 30
Example: ADC Spectral Tests
SFDR
SDR
SNR
Ref: W. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR
at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 2001
f
s
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 31
Signal Source
Typical $40k signal source spec.s:
f=100kHz...3GHz
Harmonic distortion
(f>1MHz): -30dBc !
Still need a filter to
elliminate harmonic
distortion!
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 32
Filtering Out Harmonics
Given HD=-30dBc, we need a stopband
rejection > 65dB to get SFDR>95dB
0 ... f
Amplitude
BP Filter
f
in
...
2f
in
3f
in
4f
in
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 33
Available Filters
Fixed frequency filters!
Want to test at many frequencies Need to have many
different filters!
www.tte.com, or
www.allenavionics.com
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 34
Tunable Filter
www.klmicrowave.com
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 35
Filter Distortion
Beware: The filters themselves could
also introduce distortion
Distortion is usually not specified, need
to contact manufacturer directly!
Often guaranteed: HD<-85dBc,
Don't trust your filters blindly...
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 36
Filtering Input to Spectrum Analyzer
Prevent Signal Distortion Incurred by Spec. Analyzer
0 ... f
Notch (Band Reject) Filter
f
in
...
2f
in
3f
in
4f
in
0 ... f f
in
...
2f
in
3f
in
4f
in
DAC
Output Signal
Amplitude
Spectrum
Analyzer
Input
Signal
Amplitude
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 37
Clock Generator
The clock signal controls sampling instants which
we assumed to be precisely equi-distant in time
(period T)
Typically, clock signal generators output signal have
some level of variability in T called:
"Aperture Uncertainty" or "Aperture Jitter "
Variability in T causes loss of performance in Data
Converters
How much Jitter can be tolerated? (later)
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 38
D-to-A Converter Design
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 39
D/A Converter Transfer Characteristics
An ideal digital-to-
analog converter:
Accepts digital inputs
b
1
-b
n
Produces either an
analog output voltage
or current
Assumption
Uniform, binary digital
encoding
Unipolar output
ranging from 0 to V
FS

b
1
b
2
b
N
V
o
or I
o
MSB
LSB
FS
FS
N
FS
2
N # of bi t s
V f ul l scal e out put
mi n. st ep si ze 1LSB
V
2
V
or N l og resol ut i on
=
=
A =
A =
=
A
Nomenclature:
D/A
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 40
D/A Converters
Various D/A architecture
Resistor string DAC
Charge Redistribution DAC
Current source type
Static performance
Limited by component matching
Architectures
Unit element
Binary weighted
Segmented
Performance improvement via dynamic element matching
Dynamic performance
Limited by timing errors causing glitches
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 41
D/A Converters
Comprises voltage or charge or
current based elements
Examples for above three categories:
Resistor string voltage
Charge redistribution charge
Current source type current
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 42
Resistor String DAC
R
R
R
R
R
R
R
R
Voltage based:
A B-bit DAC requires:
2
B
resistors in series
All resistors values
equal
Generates 2
B
equally spaced
voltages ready to be
chosen based on the
digital input word
V
ref
3-Bit Resistor String DAC
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 43
R-String DAC
Example
Example:
Input code:
[d2 d1 d0]=101
V
out
= 5V
ref
/8
Assuming switch
resistance << R:
t
settling
= (3R||5R) x C
=0.23 x 8RC
V
ref
/8
2V
ref
/8
3V
ref
/8
4V
ref
/8
5V
ref
/8
6V
ref
/8
7V
ref
/8
C
R
V
ref
V
out
=
5V
ref
/8
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 44
R-String DAC
Advantages:
Takes full advantage of availability
of almost perfect switches in MOS
technologies
Simple, fast for <8-10bits
Inherently monotonic
Compatible with purely digital
technologies
Disadvantages:
2
B
resistors & ~2x2
B
switches for B
bits High element count & large
area for B >10bits
High settling time for high
resolution DACs:
t
max
~ 0.25 x 2
B
RC
C
Ref:
M. Pelgrom, A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer, JSSC, Dec. 1990, pp. 1347
V
ref
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 45
R-String DAC
Choice of resistor value:
Since maximum output
settling time:
t
max
~ 0.25 x 2
B
RC
Choice of resistor value
directly affects DAC maximum
operating speed f
max
~1/R
Power dissipation: function of
V
ref
2
/ (Rx2
B
)
Tradeoff between speed
and power dissipation
C
V
ref
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 46
R-String DAC
Resistor type:
Choice of resistive material
important
Diffusion type R high temp.
co. & voltage co.
Results in poor INL/DNL
Better choice is poly resistor
beware of poly R 1/f noise
At times, for high-frequency &
high performance DACs, metal
R (beware of high temp. co.) or
thin film R is used
C
V
ref
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 47
R-String DAC
Layout Considerations
Number of resistor segments 2
B
E.g. 10-bit R-string DAC 1024 resistors
Low INL/DNL dictates good R matching
Layout quite a challenge
Good matching mandates all R segments
either vertical or horizontal - not both
Matching of metal interconnect and contacts
Need to fold the string
Difficult to match corner segments to rest
Could result in large INL/DNL
.
.
.
.
.
.
.
.
R
-
S
t
r
i
n
g

L
a
y
o
u
t
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 48
R-String DAC
Including Interpolation
Resistor string DAC + Resistor string
interpolator increases resolution w/o drastic
increase in complexity
e.g. 10bit DAC(5bit +5bit2x2
5
=2
6
# of
Rs) instead of direct 10bit2
10
Considerations:
Main R-string loaded by the interpolation
string resistors
Large R values for interpolating string
less loading but lower speed
Can use buffers
V
out
V
ref
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 49
R-String DAC
Including Interpolation
Use buffers to prevent
loading of the main
ladder
Issues:
Buffer DC offset
Effect of buffer
bandwidth
limitations on
overall speed
V
ref
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 50
Charge Based: Serial Charge Redistribution DAC
Operation based on redistribution of charge associated with C1 &
C2 to perform precise division by factor of 2
Nominally C
1
=C
2
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 51
Charge Based: Serial Charge Redistribution DAC
Simplified Operation: Conversion Sequence
( )
( )
1 2 1 2
T1 T1 T2 T2
C C C C 1 2
REF 1 1 2
1
REF
1 2
REF
1 2
o
o
o
o
Q Q Q Q C C V
V C C C V
C
V V
C C
V
Si nce C C V
2
+ + = +
= +
=
+
= =
=
T1
T2
1 1
1 2
T1 T1
C REF 1 C
T1 T1
C C REF 1
Q V C & Q 0
Q Q V C

+ =
= =
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 52
Conversion sequence:
Next cycle
If S3 closed V
C1
=0 then when S1 closes V
C1
= V
C2
= V
REF
/4
If S2 closed V
C1
=V
REF
then when S1 closes V
C1
=V
C2
=V
REF
/2+V
REF
/4
Serial Charge Redistribution DAC
Simplified Operation (Contd)
T1
T2
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 53
Serial Charge Redistribution DAC
Conversion sequence:
Discharge C1 & C2S3& S4
closed
For each bit in succession
beginning with LSB, b
1
:
S1 open- if b
i
=1 C1
precharge to V
REF
if b
i
=0
discharged to GND
S2 & S3 & S4 open- S1
closed- Charge sharing
C1 & C2
of precharge on
C1 + of charge
previously stored on
C2C2
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 54
Serial Charge Redistribution DAC
Example: Input Code 101
b
3
b
2
b
1
LSB
MSB
Example input code 101output (4/8 +0/8 +1/8 )V
REF
=5/8 V
REF
Very small area
For an N-bit DAC, N redistribution cycles for one full analog output
generation quite slow
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 55
Parallel Charge Scaling DAC
Make Cx & Cy function of incoming DAC digital word
V
ref
V
out
C Cx Cy
out
ref
Cx
V V
Cx Cy C +
=
+
DAC operation based on capacitive voltage division
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 56
Parallel Charge Scaling DAC
E.g. Binary weighted
B+1 capacitors & B switches
(Cs built of unit elements
2
B
units of C)
C C 2C 4C 8C 2
(B-1)
C
Vref
Vout
reset
b
0
(lsb) b
1
b
2
b
3
b
B-1
(msb)
B 1
i
i
i 0
out
ref
B
b 2 C
V V
2 C

=
=

EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 57
Charge Scaling DAC
Example: 4Bit DAC- Input Code 1011
C C 2C 4C 8C
Vref
Vout
b
0
(lsb) b
1
b
2
b
3
C C 2C 4C 8C
Vref
Vout
reset
b
0
(lsb)
b
1
b
2
b
3
2- Charge phase
1- Reset phase
0 1 3
out ref ref
4
2 C 2 C 2 C 11
V V V
2 C 16
=
+ +
=
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 58
Charge Scaling DAC
Sensitive to parasitic capacitor @ output
If C
p
constant gain error
If C
p
voltage dependant DAC nonlinearity
Large area of caps for high DAC resolution (10bit DAC ratio
1:512)
Monotonicity depends on element matching (more later)
ref
P
B
B
i
i
i
out
V
C C
C b
V
+
=

=
2
2
1
0
C C 2C 4C 8C 2
(B-1)
C
Vref
Vout
reset
b
0
(lsb) b
1
b
2
b
3
b
B-1
(msb)
C
P
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 59
Parasitic Insensitive
Charge Scaling DAC
Opamp helps eliminate the parasitic capacitor effect by producing virtual
ground at the sensitive node since C
P
has zero volts at start & end
Issue: opamp offset & speed- also double capacitor area
C 2C 4C 8C 2
(B-1)
C
Vref
Vout
reset
b
0
(lsb) b
1
b
2
b
3
b
B-1
(msb)
C
P
C
I
-
+
C
I
B 1 B 1
i i
b 2 C b 2
i i
B i 0 i 0
V V , C 2 C V V
out ref I out ref
B
C 2
I


= =
= = =
EECS 247 Lecture 13: Data Converters- Testing & DAC Design 2010 Page 60
Charge Scaling DAC
Incorporating Offset Compensation
During reset phase:
Opamp disconnected from capacitor array via switch S3
Opamp connected in unity-gain configuration (S1)
C
I
Bottom plate connected to ground (S2)
V
out
~ - V
os
V
CI
= -V
os
This effectively compensates for offset during normal phase
C 2C 4C 8C 2
(B-1)
C
Vref
Vout
reset
b
0
(lsb) b
1
b
2
b
3
b
B-1
(msb)
C
P
-
+
C
I
os
V
reset
reset
S1
S2
S3
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 61
Charge Scaling DAC
Utilizing Split Array
Split arrayreduce the total area of the capacitors required for high
resolution DACs
E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64 unit Cs
Issue: Sensitive to series capacitance parasitic capacitor
seri es
al l LSB array C
C C
al l MSB array C
=

C
2C
4C
Vref
Vout
reset
b
5
b
4
b
3
b
2
+
-
8/7C
C 2C 4C
b
1
b
0
C
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 62
Charge Scaling DAC
Advantages:
Low power dissipation capacitor array does not dissipate DC power
Output is sample and held no need for additional S/H
INL function of capacitor ratio
Possible to trim or calibrate for improved INL
Offset cancellation almost for free
Disadvantages:
Process needs to include good capacitive material not compatible
with standard digital process
Requires large capacitor ratios
If binary-weighted Cs used then not inherently monotonic (more later)
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 63
Segmented DAC
Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
C C 2C 4C 8C 32 C
reset
b
1 b
2
b
3 b
5
16C
b
4
V
out
b
0
.
.
.
.
.
.
.
.
.
.
Switch
Network
6bit
resistor
ladder
6-bit
binary weighted
charge redistribution DAC
Example: 12bit
DAC
6-bit MSB DAC
R- string
6-bit LSB DAC
binary weighted
charge scaling
Component count
much lower
compared to full R-
string
Full R string
4096 resistors
Segmented 64
R + 7 Cs (64 unit
caps)
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 64
Current Based DACs
R-2R Ladder Type
R-2R DAC basics:
Simple R network
divides both voltage
& current by 2
R
V
V/2
2R 2R
I
I/2
I/2
Increase # of bits by replicating circuit
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 65
R-2R Ladder DAC
V
B
2R 2R
Emitter-follower added to convert to high output impedance current
sources
2R 2R 2R 2R
R R R R
V
EE
I
out
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 66
R-2R Ladder DAC
How Does it Work?
V
B
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2R
R R
V
EE
I
out
1xA
unit
1xA
unit
2xA
unit
4xA
unit
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 67
R-2R Ladder DAC
How Does it Work?
V
B
Simple 3bit DAC:
1- Consolidate first two stages:
2R 2R 2R 2R
R R
V
EE
I
T I
1
I
2
I
3
A
unit
A
unit 2A
unit
4A
unit
Q
T
Q
1
Q
2
Q
3
V
B
2R 2R R
R R
V
EE
I
1
+I
T I
2
I
3
2A
unit 2A
unit
4A
unit
Q
2
Q
3
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 68
R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC-
2- Consolidate next two stages:
V
B
2R 2R R
R R
V
EE
I
1
+I
T
I
2
I
3
2A
unit 2A
unit
4A
unit
Q
2
Q
3
V
B
2R R
R
V
EE
I
2
+I
1
+I
T
I
3
4A
unit
4A
unit
Q
2
Q
3
Tot al Tot al Tot al
3 2 1 3 2 1 T
I I I
I I I I I , I , I
2 4 8
= + + = = =
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 69
R-2R Ladder DAC
How Does it Work?
V
B
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2R
R R
V
EE
I
I 2I
4I
2I
4I
I
out
A
unit
A
unit
2A
unit
4A
unit
Ref: B. Razavi, Data Conversion System Design, IEEE Press, 1995, page 84-87
In most cases need to convert output current to voltage
Note that finite output resistance of the current sources causes gain error
only
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 70
R-2R Ladder DAC
V
B
2R 2R
Trans-resistance amplifier added to:
- Convert current to voltage
- Generate virtual ground @ current summing node so that output
impedance of current sources do not cause error
- Issue: error due to opamp offset
V
out
R
-
+
2R 2R 2R 2R
R R R R
V
EE
I
I 2I
4I
8I 16I
2I
4I
8I
16I
R
Total
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 71
R-2R Ladder DAC
Opamp Offset Issue
out i n
os os
Tot al
Tot al
out i n
os os
Tot al
out i n
os os
Tot al
Tot al
out
os
R
1
V V
R
If R l arge,
V V
If R not l arge
R
1
V V
R
Pr obl em:
Si nce R i s code dependant
V woul d be code dependant

Gi ves ri se t o INL & DNL
| |
+
=
|
\ .
=
~
=
| |
+
=
|
\ .

V
out
R
-
+
R
Total
os
V
Offset
Model
EECS 247 Lecture 14: Data Converters- DAC Design 2009 Page 72
R-2R Ladder
Summary
Advantages:
Resistor ratios only x2
Does not require precision capacitors
Disadvantages:
Total device emitter area A
E
unit
x 2
B
Not practical for high resolution DACs
INL/DNL error due to amplifier offset