Ch.

4 Design of Arithmetic Operations

1. 2. 3. Serial Adder Multiplier- signed, unsigned Divider- signed, unsigned

Serial Adder with Accumulator

X T0 0101 T1 0010 T2 0001 T3 1000 T4 1100

Y 0111 1011 1101 1110 0111

Ci 0 1 1 1 0

Sumi Ci+1 0 0 1 1 (1) 1 1 1 0 (0)

x<= x+y x=augend, y=addend,

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Control Circuit
input: N, Clock output: Sh

State Graphs for Control Networks

Notation of Mealy Machine
Input/Output XiXj/ZpZq : Xi=1, Xj=1, Zp=1, Zq=1 Ex) input (X1, X2, X3, X4), Output (Z1, Z2, Z3, Z4) X1X4/Z2Z3 : 10/0110

State Sk input label constraints

1. Sk input label Ii, Ij , IiIj=0 if i j 2. N-input label I1+I2+ +In = 1

Examples
Good!

Bad!

4.3 Unsigned Multiplication

4 x 4 multiplication

Product <= Mcand x Mplier Mcand: Mplier:

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Design of a Binary Multiplier

Multiplication
add and shift operation Product

Mcand Mplier

State Graph for Multiplier Control

input: M, St output: Load, Sh, Ad, Done

VHDL for 4x4 Multiplier

-- This is a behavioral model of a multiplier for unsigned binary numbers. It multiplies a -- 4-bit multiplicand by a 4-bit multiplier to give an 8-bit product. -- The maximum number of clock cycles needed for a multiply is 10. library BITLIB; use BITLIB.bit_pack.all; entity mult4X4 is port (Clk, St: in bit; Mplier,Mcand : in bit_vector(3 downto 0); Done: out bit); end mult4X4; architecture behave1 of mult4X4 is signal State: integer range 0 to 9; signal ACC: bit_vector(8 downto 0); -- accumulator alias M: bit is ACC(0); -- M is bit 0 of ACC begin
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process begin wait until Clk = '1'; -- executes on rising edge of clock case State is when 0=> -- initial State if St='1' then ACC(8 downto 4) <= "00000"; -- Begin cycle ACC(3 downto 0) <= Mplier; -- load the multiplier State <= 1; end if;
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when 1 | 3 | 5 | 7 => -- "add/shift" State if M = '1' then -- Add multiplicand ACC(8 downto 4) <=add4(ACC(7 downto 4),Mcand,'0'); State <= State + 1; else ACC <= '0' & ACC(8 downto 1); --Shift accumulator right State <= State + 2; end if; when 2 | 4 | 6 | 8 => -- "shift" State ACC <= '0' & ACC(8 downto 1); -- Right shift State <= State + 1; when 9 => -- End of cycle State <= 0; end case; end process; Done <= '1' when State = 9 else '0'; end behave1;
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General Case: NxN-bits Multiplier

Multiplier control with Counter input: M, St output: Load, Sh, Ad, Done

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Operation with Counter

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4-bit Multiplier Partial Products

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4 x 4 Array Multiplier

total delay->8tad+tg n2 AND, n(n-2) FA n HA are needed!

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4.4 Multiplication of Signed Binary Numbers

1. 2. 3. 4. Complement the multiplier if negative Complement the multiplicand if negative Multiply the two positive binary numbers Complement the product if it should be negative

Multiplication of the Signed fractional Binary numbers

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Signed Fractional Binary Numbers

2s Complement Signed binary fraction
(Sign bit + fraction) Ex) Sign bit + three fractional bits 0.101 b = 2^(-1)+2^(-3) = +5/8 1.011 b = -(0.100+0.001)=-(0.101) = -5/8 --2 Or 1.011 b = -2^0 +2^(-2) +2^(-3) = -1+3/8 = -5/8 1.000 b = -2^0 = -1 (smallest negative value) 0.111 b = 2^(-1)+2^(-2)+2^(-3) = +7/8 (largest positive value)

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Multiplication of Signed Binary Numbers

i) (+) x (+)

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ii) (-) x (+)

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iii) (+) x (-)

=1.g = -1 + 0.g

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iv) (-) x (-)

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Multiplication of Signed Binary Numbers

2s complement multiplier

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Control of 2s complement multiplier

inputs: St, M outputs: Load, Sh, Ad Done, Cm

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Faster Multiplier

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Control of Fast Multiplier

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2s complement
library BITLIB; use BITLIB.bit_pack.all; entity mult2C is port (CLK, St: in bit; Mplier,Mcand : in bit_vector(3 downto 0); Product: out bit_vector (6 downto 0); Done: out bit); end mult2C; architecture behave1 of mult2C is signal State : integer range 0 to 5; signal A, B: bit_vector(3 downto 0); alias M: bit is B(0); begin
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process variable addout: bit_vector(4 downto 0); begin wait until CLK = '1'; case State is when 0=> -- initial State if St='1' then A <= "0000"; -- Begin cycle B <= Mplier; -- load the multiplier State <= 1; end if;
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when 1 | 2 | 3 => -- "add/shift" State if M = '1' then addout := add4(A,Mcand,'0'); -- Add --multiplicand to A and shift A <= Mcand(3) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); else A <= A(3) & A(3 downto 1); -- Arithmetic --right shift B <= A(0) & B(3 downto 1); end if; State <= State + 1;
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when 4 => -- add complement if sign bit if M = '1' then -- of multiplier is 1 addout := add4(A, not Mcand,'1'); A <= not Mcand(3) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); else A <= A(3) & A(3 downto 1); -- Arithmetic right shift B <= A(0) & B(3 downto 1); end if; State <= 5; wait for 0 ns; Done <= '1'; Product <= A(2 downto 0) & B; when 5 => -- output product State <= 0; Done <= '0'; end case; end process; end behave1;
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Command File and Simulation Results for (+5/8 by -3/8)

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Test Bench for Signed Multiplier

library BITLIB; use BITLIB.bit_pack.all; entity testmult is end testmult; architecture test1 of testmult is component mult2C port(CLK, St: in bit; Mplier,Mcand : in bit_vector(3 downto 0); Product: out bit_vector (6 downto 0); Done: out bit); end component; constant N: integer := 11; type arr is array(1 to N) of bit_vector(3 downto 0); constant Mcandarr: arr := ("0111", "1101", "0101", "1101", "0111", "1000", "0111", "1000", "0000", "1111", "1011"); constant Mplierarr: arr := ("0101", "0101", "1101", "1101", "0111", "0111", "1000", "1000", "1101", "1111", "0000"); signal CLK, St, Done: bit; signal Mplier, Mcand: bit_vector(3 downto 0); signal Product: bit_vector(6 downto 0); 32

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begin CLK <= not CLK after 10 ns; process begin for i in 1 to N loop Mcand <= Mcandarr(i); Mplier <= Mplierarr(i); St <= '1'; wait until rising_edge(CLK); St <= '0'; wait until falling_edge(Done); end loop; end process; mult1: mult2c port map(Clk, St, Mplier, Mcand, Product, Done); end test1;

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Command File and Simulation of Signed Multiplier

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[revised] Model for 2s Complement Multiplier

library BITLIB; use BITLIB.bit_pack.all; entity mult2Cs is port (CLK, St: in bit; Mplier,Mcand : in bit_vector(3 downto 0); Product: out bit_vector (6 downto 0); Done: out bit); end mult2Cs; architecture behave2 of mult2Cs is signal State, Nextstate: integer range 0 to 5; signal A, B: bit_vector(3 downto 0); signal AdSh, Sh, Load, Cm: bit; signal addout: bit_vector(4 downto 0); alias M: bit is B(0); begin
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process (state, st, M) begin Load <= '0'; AdSh <= '0'; Sh <= '0'; Cm <= '0'; Done <= '0'; case State is when 0=> -- initial State if St='1' then Load <= '1'; Nextstate <= 1; end if; when 1 | 2 | 3 => -- "add/shift" State if M = '1' then AdSh <= '1'; else Sh <= '1'; end if; Nextstate <= State + 1; when 4 => -- add complement if sign if M = '1' then Cm <= '1'; AdSh <= '1';-- bit of multiplier is 1 else Sh <= '1'; end if; nextstate <= 5; when 5 => -- Output product done <= '1'; nextstate <= 0; 36 end case;

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end process; addout <= add4(A, Mcand, '0') when Cm = '0' else add4(A, not Mcand, '1'); process begin wait until CLK = '1'; -- executes on rising edge if Load = '1' then -- Load the multiplier A <= "0000"; B <= Mplier; end if; if AdSh = '1' then -- Add multiplicand to A and Shift A <= (Mcand(3) xor Cm) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); end if; if Sh = '1' then A <= A(3) & A(3 downto 1); B <= A(0) & B(3 downto 1); end if; State <= Nextstate; end process; Product <= A(2 downto 0) & B; end behave2;

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Model for 2s Complement Multiplier

-- This model of a 4-bit multiplier for 2's complement numbers -- implements the controller using a counter and logic equations. library BITLIB; use BITLIB.bit_pack.all; entity mult2CEQ is port(CLK, St: in bit; Mplier,Mcand: in bit_vector(3 downto 0); Product: out bit_vector(6 downto 0)); end mult2CEQ; architecture m2ceq of mult2CEQ is signal A, B, Q, Comp: bit_vector(3 downto 0); signal addout: bit_vector(4 downto 0); signal AdSh, Sh, Load, Cm, Done, Ld1, CLR1, P1: bit; Signal One: bit:='1'; Signal Din: bit_vector(3 downto 0) := "0100"; alias M: bit is B(0); begin
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Count1: C74163 port map (Ld1, CLR1, P1, One, CLK, Din, open, Q); P1 <= Q(2); CLR1 <= not Q(3); Done <= Q(3); Sh <= not M and Q(2); AdSh <= M and Q(2); Cm <= Q(1) and Q(0) and M; Load <= not Q(3) and not Q(2) and St; Ld1 <= not Load; Comp <= Mcand xor (Cm & Cm & Cm & Cm); -- complement Mcand if Cm='1' addout <= add4(A,Comp,Cm); -- add complementer output to A process begin wait until CLK = '1'; -- executes on rising edge if Load = '1' then -- load the multiplier A <= "0000"; B <= Mplier; end if;
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if AdSh = '1' then -- Add multiplicand to A and shift A <= (Mcand(3) xor Cm) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); end if; if Sh = '1' then -- Right shift with sign extend A <= A(3) & A(3 downto 1); B <= A(0) & B(3 downto 1); end if; if Done = '1' then Product <= A(2 downto 0) & B; end if; end process; end m2ceq;
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Binary Division
-- Division 8bits / 4bits

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Design of a Parallel Binary Divider

Fig. 4-19

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Overflow
quotient of greater than 15 inspect dividend and divisor
Ex) 135/7=19.2857....

can subtract but, quotient bit of 1 will destroy LSB of dividend overflow!

Overflow condition
X8X7X6X5X4Y3Y2Y1Y0

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Review
Fig. 4-19

Su=1: subtract signal, and set the quotient bit to 1 Su=0: can not subtract C=0: divisor is greater than the 4 leftmost dividend bits, thus, subtract can not occur
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Unsigned Divider Control

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Control Signals for Signed Divider

LdU Load upper half of dividend from bus LdL Load lower half of dividend from bus Lds Load sign of dividend into sign flip-flop S Sign of dividend Cm1 Complement dividend register (2's complement) Ldd Load divisor from bus Su Enable adder output onto bus (Ena) and load upper half of dividend from bus

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 Cm2 Enable complementer (Cm2 equals the complement of the sign bit of the divisor, so that a positive divisor is complemented and a negative divisor is not) Sh Shift the dividend register left one place and increment the counter C Carry output from adder (If C = 1, the divisor can be subtracted from the upper dividend.) St Start V Overflow Qneg Quotient will be negative (Qneg = 1 when sign of dividend and divisor are different)
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Signed Divider

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Signed Divider

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 Control

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VHDL Model of 32-bit Signed Divider

library BITLIB; use BITLIB.bit_pack.all; entity sdiv is port(Clk,St: in bit; Dbus: in bit_vector(15 downto 0); Quotient: out bit_vector(15 downto 0); V, Rdy: out bit); end sdiv; architecture Signdiv of Sdiv is constant zero_vector: bit_vector(31 downto 0):=(others=>'0'); signal State: integer range 0 to 6; signal Count : integer range 0 to 15; signal Sign,C,NC: bit; signal Divisor,Sum,Compout: bit_vector(15 downto 0); signal Dividend: bit_vector(31 downto 0); alias Q: bit_vector(15 downto 0) is Dividend(15 downto 0); alias Acc: bit_vector(15 downto 0) is Dividend(31 downto 16);54

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begin -- concurrent statements compout <= divisor when divisor(15) = '1' -- 1's complementer else not divisor; Addvec(Acc,compout,not divisor(15),Sum,C,16); -- 16-bit adder Quotient <= Q; Rdy <= '1' when State=0 else '0'; process begin wait until Clk = '1'; -- wait for rising edge of clock case State is when 0=> if St = '1' then Acc <= Dbus; -- load upper dividend Sign <= Dbus(15); State <= 1; V <= '0'; Count <= 0; -- initialize overflow// initialize counter end if; 55

when 1=> Q <= Dbus; State <= 2; -- load lower dividend when 2=> Divisor <= Dbus; if Sign ='1'then -- two's complement Dividend if necessary addvec(not Dividend,zero_vector,'1',Dividend,NC,32); end if; State <= 3; when 3=> Dividend <= Dividend(30 downto 0) & '0'; -- left shift Count <= Count+1; State <= 4; when 4 => if C ='1' then -- C v <= '1'; State <= 0; else -- C' Dividend <= Dividend(30 downto 0) & '0'; -- left shift Count <= Count+1; State <= 5; 56 end if;

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when 5 => if C = '1' then -- C ACC <= Sum; -- subtract Q(0)<= '1'; else Dividend <= Dividend(30 downto 0) & '0'; -- left shift if Count = 15 then -- KC' count<= 0; State <= 6; else Count <= Count+1; end if; end if; when 6=> if C = '1' then -- C Acc <= Sum; -- subtract Q(0) <= '1'; else if (Sign xor Divisor(15))='1' then -- C'Qneg addvec(not Dividend,zero_vector,'1',Dividend,NC,32); end if; -- 2's complement Dividend state <= 0; end if; end case; end process; end signdiv;

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Test Bench for Signed Divider

library BITLIB; use BITLIB.bit_pack.all; entity testsdiv is end testsdiv; architecture test1 of testsdiv is component sdiv port(Clk,St: in bit; Dbus: in bit_vector(15 downto 0); Quotient: out bit_vector(15 downto 0); V, Rdy: out bit); end component; constant N: integer := 12; -- test sdiv1 N times type arr1 is array(1 to N) of bit_vector(31 downto 0); type arr2 is array(1 to N) of bit_vector(15 downto 0);
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 constant dividendarr: arr1 := (X"0000006F",X"07FF00BB",X"FFFFFE08", X"FF80030A",X"3FFF8000",X"3FFF7FFF",X"C00 08000",X"C0008000", X"C0008001",X"00000000",X"FFFFFFFF",X"FFFF FFFF"); constant divisorarr: arr2 := (X"0007", X"E005", X"001E", X"EFFA", X"7FFF", X"7FFF", X"7FFF", X"8000", X"7FFF", X"0001", X"7FFF", X"0000"); signal CLK, St, V, Rdy: bit; signal Dbus, Quotient, divisor: bit_vector(15 downto 0); signal Dividend: bit_vector(31 downto 0); signal count: integer range 0 to N;
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begin CLK <= not CLK after 10 ns; process begin for i in 1 to N loop St <= '1'; Dbus <= dividendarr(i) (31 downto 16); wait until rising_edge(CLK); Dbus <= dividendarr(i) (15 downto 0); wait until rising_edge(CLK); Dbus <= divisorarr(i); St <= '0'; dividend <= dividendarr(i); -- save dividend for listing divisor <= divisorarr(i); -- save divisor for listing wait until (Rdy = '1'); count <= i; -- save index for triggering end loop; end process; sdiv1: sdiv port map(Clk, St, Dbus, Quotient, V, Rdy); end test1;

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Simulation Result of Signed Divider

-- Command file to test results of signed divider list -hex -Notrigger dividend divisor Quotient V -Trigger count run 5300 ns delta dividend divisor quotient v count 0 +0 00000000 0000 0000 0 0 470 +3 0000006F 0007 000F 0 1 910 +3 07FF00BB E005 BFFE 0 2 1330 +3 FFFFFE08 001E FFF0 0 3 1910 +3 FF80030A EFFA 07FC 0 4 2010 +3 3FFF8000 7FFF 0000 1 5 2710 +3 3FFF7FFF 7FFF 7FFF 0 6 2810 +3 C0008000 7FFF 0000 1 7 3510 +3 C0008000 8000 7FFF 0 8 4210 +3 C0008001 7FFF 8001 0 9 4610 +3 00000000 0001 0000 0 A 5010 +3 FFFFFFFF 7FFF 0000 0 B 5110 +3 FFFFFFFF 0000 0002 1 C
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