Verilog Tutorial 1
Verilog Tutorial 1
Conducted by:
Course Objective
Create and implement designs by using the ISE software design
environment and Basys-2 Spartan3E FPGA board. RTL Verilog code for synthesis
Verilog for Description Verilog for Synthesis
Verilog Modeling for Combinational Circuits Verilog Modeling for Sequential Circuits
Creating Finite State Machine (FSM) by using Verilog Verilog test fixtures for simulation Introduction to FPGA Project Work
PHASE-I
AGENDA:
Introduction to VLSI and its importance Getting Started with ISE 10.1 and Basys-2 Spartan 3E Kit Lab work
or Start All Programs Xilinx ISE Design Suite 10.1ISE Project Navigator