Kolokium dan Sanggar Kerja Institut Sel Fuel Langkawi, 21 - 23 November 2008 ms.

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FLOW FIELD FABRICATION USING WET ETCHING S.K. Kamarudin1, W.R.W. Daud1, B.Y. Majlis2, A.B. Mohamad1,3, A.A.H. Kadhum1,3, U.A. Hasran1, M.M. Ahmad1, N. Hashim1 , S. Basri1 Institut Sel Fuel Institut Kejuruteraan Mikro dan Nanoelektronik 3 Jabatan Kejuruteraan Kimia dan Proses, Fakulti Kejuruteraan Universiti Kebangsaan Malaysia 43600 UKM Bangi, Selangor, Malaysia
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ABSTRACT The flow fields of both cathode and anode of a micro fuel cell are fabricated on silicon wafer using wet etching with KOH + IPA solution. Through holes and channels for the anode are done using a double-etch technique that utilizes etching time to control the depth of the required pattern. It was observed that with constant monitoring of the conditions and parameters used during the whole microfabrication process, it is possible to successfully utilize the wet etching process to fabricate the flow fields required in the fuel cell design. Keywords: KOH; positive resist; flow field; silicon wafer; wet etching

INTRODUCTION Micro-fuel cells have a higher energy densities compared to batteries (Dyer 2002) and stand out as the most promising candidate due to factors such as instantaneous refuelling time, compact and lightweight system, and easy storage of liquid fuel. Miniaturization, however, is not a simple scaling down of the larger system. Rather, each component of the fuel cell must be redesigned with an eye towards miniaturization (Meyers & Maynard 2002). MEMS technology is able to make the bipolar plate smaller and with higher precision, coupled with the potential of mass production. The use of silicon wafer in micro-fuel cells has made it possible to use a range of materials available in the semiconductor IC industry (Maluf 2000). Most published literature shows a preference towards dry etching with DRIE system for the flow field fabrication as it produces high aspect ratio silicon micromachining (Yeom et al. 2005, Esquivel et al. 2008, Zhang et al. 2007, Lu et al. 2004). However, it is expensive due to the high expense of equipment and running cost. Wet chemical etching has low process cost, simple etch setup, higher etch rate, better surface smoothness, high degree of anisotropy and lower environmental pollution and KOH is the common etchant for silicon (Biswas and Kal 2006). This work aims to investigate the feasibility of etching through hole with channel structures on a silicon wafer for the fabrication of flow fields using the wet etching method with an etching mask of thermally grown silicon oxide layer.

METHODOLOGY The process flow to produce wafer structures suitable for use as flow fields in a micro direct methanol fuel cell is shown in Figure 1 (a) and the schematic of the fabrication process for the anode and cathode substrates are shown in Figure 1 (b) and (c),

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respectively. Silicon wafers of 100 p-type 100 mm diameter with a thickness of 500 20 m and resistivity of 0 20 ohm-cm were used. Silicon (Si) etching mask is the thermally grown silicon oxide (SiO2) layer.

i. Thermal oxidation

ii. Photolithography: 1 mask

st

iii. SiO2 etching with BOE

iv. Si etching with KOH i. Thermal oxidation v. Photolithography: 2 mask ii. Photolithography vi. SiO2 etching with BOE iii. SiO2 etching with BOE iv. Si etching with KOH (through holes)
nd

vii. Si etching with KOH (channels & through holes)

(a)

(b)

(c)

Figure 1 (a) Process Flow for the Fabrication of Wafer Structures, and the Main Steps of the Microfabrication Process for (b) Anode Substrate, (c) Cathode Substrate

Fresh bare wafers were cleaned and underwent a thermal oxidation process inside a Modu-Lab oxidation furnace module with an oxygen flow rate of 1 L/min at 1100 C. Placed in an oxidizing ambient, the time required to grow an oxide of thickness X0 at a constant temperature on a bare silicon surface, t, is obtained using the Deal-Grove model that works very well for single-crystal silicon under most conditions. is a corrective term to obtain the total time required to grow oxide under the same conditions on a wafer with a pre-existing oxide layer. Thickness was measured with the profilometer (XP-1 High Resolution Surface Profiler from Ambios Technology with 100X-fixed standard magnification and 2.0 m stylus tip radius) or a spectrophotometer (Filmetrics F20 version 3.4.3, Solver version 3.1.1). Constants A and B encapsulate the properties of the reaction and the oxide layer, respectively (refer to appendix): (1)

. (2) Following the oxidation process, the substrates underwent photolithography. The photolithography masks were designed using a computer-aided-design (CAD) software and produced on a high quality transparency paper. The photoresist and

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developer used for this experiment are positive resist PR1-4000A and RD6 (Futurrex, Inc.), respectively. The photoresist spinner used is the Laurell Spin Processor model WS-400A-6NPP/LITE/IND (Laurell Technologies Corporation). The wafer was loaded onto the wafer chuck. The photoresist was dropped onto the wafer surface and spin-coated to get the desired thickness. The wafer was unloaded and placed on the oven plate to be soft-baked and later removed from the oven plate to be cooled on the cooling slab. For the mask alignment process, Exposure and Mask Alignment System MDA-400M (Midas System), which can achieve a resolution and alignment accuracy of 1m, was used. The resist-coated wafer was loaded onto the wafer chuck and the mask was attached to the frame. The X, Y, Z positions of the aligner were adjusted to allow the mask to be satisfactorily aligned with the wafer and the photoresist was exposed to UV light of exposure wavelength 365nm. The wafer was then immersed into developer RD6 to develop the photoresist. This is a critical process in photolithography as the photoresist can be under- or overdeveloped depending on the development time. After a thorough rinse with DI water until water resistivity reached the prescribed limit, overlay inspection and pattern line-width measurement using a high-power microscope (Olympus BX51M with 5/10/50/100X magnification) were carried out to ensure the succesful transfer of the mask pattern. If it is unsuccessful, the photoresist is stripped with acetone and the photolithography process is repeated until the result is satisfactory before undergoing hard-baking. For the anode side, two masks designed are required in the etching process, the first is for patterning the through holes and the second is for etching the channels and the through holes (refer to Fig. 1(b) ii and v). Before silicon etching can be carried out, the oxide mask needs to be etched by immersing the patterned substrate in a 10:1 Buffered Oxide Etch (BOE) solution. The back side is coated with a thin layer of photoresist to protect the oxide layer from being etched along. Then, the wafer is diced and immersed in KOH. The KOH solution needs to be constantly diluted to prevent damage to the wafer. Due to the non-uniform nature of the etching process, the double-etch technique utilizes an oxide layer of thickness up to 4.8 m.

RESULTS AND DISCUSSION Six wafers were oxidized in the same batch for 41.27 hours with five pauses in between. The thickness measurement was taken during each pause to observe whether the oxidation follows the model prediction. Wafers are numbered from 1 to 6 depending on their position in the metal boat, i.e. #1 is the farthest from the process tube outlet where the oxygen source is.

Table 1 Comparison between the Calculated Values and the Real Values of t Wafer # Model (hr) t (%) SiO2 thickness () 1 38.30 7.18% 41741 2 38.15 7.56% 41655 3 38.42 6.90% 41804 4 37.96 8.01% 41552 5 37.67 8.72% 41388 6 36.90 10.59% 40959

Table 1 shows that the position of the wafers in the boat influences the oxidation rate, therefore the closer the wafer to the oxygen source, the slower the rate due to the lower temperature of the oxygen gas. The difference between the

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calculated and real values of oxidation time, t, is relatively small in the range of 7 11%. Time to grow up to 4 m thick oxide layer is ~40 hours, i.e. the rate of oxidation is about 0.1 m/hr. Graph of oxide layer thickness against time from experiment is as shown in Figure 2. The relationship between the growth of oxide thickness and time is almost linear, which shows that the delay or pause between each process does not influence the thickness of the oxide layer formed.

Figure 2 Thermal Oxidation Rate of (100) Silicon at T = 1100C

For the photolithography process, trial and error methods were conducted. Some techniques were deemed unsuitable for the process, e.g. using negative resist type and double-coating of positive photoresist during spinning. Development parameters are quite difficult to confirm from visual inspection because the results vary from one run to the next even though all the parameters and settings are the same and the development time is similar. Finally, parameters that give a good performance for this experiment are obtained as given in Table 2.

Table 2 Parameters used in the Photolithography Process PR Type PR1 4000A Clean & Dry T (C) 120 t (min) 5 Spinner rpm 3000 t (s) 45 Soft-bake T (C) 120 t (s) 90 Aligner t (s) 16 Hard-bake T (C) 120 t (s) 90 RD6 t (min) 2-3

Etching with a higher KOH concentration (40 50%) was found to take too much time and the fast evaporation of water in the KOH solution resulted in very high KOH concentration, causing severe damage to the wafer before the process could be completed. After several trial and error methods, the KOH concentration of 30 wt% at

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80 90C was used in the experiment and the times taken for mask #1 and #2 are 210 and 150 minutes, respectively. IPA is added to the KOH solution in order to smoothen the (100) wafer surface (Zubel 2000) and stirring is regularly employed to increase the etch rate during KOH dilution (Mihalcea et al. 2001). For repeated etching under similar conditions and with the same KOH concentration, patterns #1 and #2 in Table 3 show faster oxide etching rate that results in the rapid erosion of oxide mask on the front and back sides of the wafer, while patterns #3 and #4 can be etched until the through hole structure is completed without much erosion to the wafer. The double-etch technique benefits from the etch rate obtained during cathode through hole structure formation, as shown by patterns #5 and #6 in Table 3. However, the patterns are typically over-etched and the channel depth varies as it is very difficult to control the etching time. The remaining oxide layer after silicon etching process completes is removed with BOE.

Table 3 Comparison between Pattern Design and Etched Wafer

Cathode 1

Cathode 2

Cathode 3

Cathode 4

Anode 5
Mask 1 Mask 2

Anode 6
Mask 1 Mask 2

CONCLUSIONS Several designs have been utilized to pattern the wafer and it was found that not all of them are suitable to be etched for through holes using KOH solution. The double-etch technique results in a predictable over-etched pattern due to the anisotropic nature of KOH wet etching process and also because it is very difficult to control the process through etching time to obtain the etch depth and pattern desired. However, it was found that it is possible to etch both the channels and through holes for simple mask designs using only the more affordable wet etching method with KOH solution of quite low concentration.

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APPENDIX In literature (Insitute of Microelectronics, Vienna), the parameters B and B/A were plotted over the temperature range 800 1000 C for (111) oriented silicon at one atmosphere for wet and dry oxidation. In order to get the corresponding values for (100) oriented silicon, only the C2 values must be divided by the factor 1.68, while all the E1,2 and C1 values are the same as given in Table A1. Table A1 Arrhenius parameters for B and B/A in (111) oriented silicon Ambient Dry O2 Wet O2 B C1 = 7.72 x 102 m2/hr E1 = 1.23 eV C1 = 3.86 x 102 m2/hr E1 = 0.78 eV A1 A2 B/A C2 = 6.23 x 106 m/hr E2 = 2.00 eV C2 = 1.63 x 108 m2/hr E2 = 2.05 eV

REFERENCES Dyer, C.K. 2002. Fuel cells for portable applications, J. Power Sources, 106: 3134. Meyers, J.P., Maynard, H.L.J. 2002. Design considerations for miniaturized PEM fuel cells, J. Power Sources, 109: 7688. Maluf, N.I. 2000. An Introduction to Micro-Electromechanical Systems Engineering, Artech House, London. Yeom, J., Mozsgai, G.Z., Flachsbart, B.R., Choban, E.R., Asthana, A., Shannon, M.A., Kenis, P.J.A. Microfabrication and characterization of a silicon-based millimeter scale, PEM fuel cell operating with hydrogen, methanol, or formic acid. 2005. Sensors and Actuators B 107: 882891 Esquivel, J. P., Sabate, N., Santander, J., Torres, N., Cane, C. 2008. Fabrication and characterization of a passive silicon-based direct methanol fuel cell, Microsyst Technol 14:535541 Zhang, Y., Lu, J., Shimano, S., Zhou, H., Maeda, R. 2007. Development of MEMS-based direct methanol fuel cell with high power density using nanoimprint technology, Electrochemistry Communications 9: 13651368 Lu, G.Q., Wang, C.Y., Yen, T.J., Zhang, X. 2004. Development and characterization of a silicon-based micro direct methanol fuel cell, Electrochimica Acta 49: 821828 Biswas, K., Kal, S. 2006. Etch characteristics of KOH, TMAH and dual doped TMAH for bulk micromachining of silicon, Microelectronics Journal 37: 519525 Zubel, I. 2000. Silicon anisotropic etching in alkaline solutions III: On the possibility of spatial structures forming in the course of Si(100) anisotropic etching in KOH and KOH + IPA solutions, Sensors and Actuators 84: 116 125 Mihalcea, C., Holz, A., Kuwahara, M., Tominaga, J., Oesterschulze, E., Atoda, N. 2001. Improved anisotropic deep etching in KOH-solutions to fabricate highly specular surfaces, Microelectronic Engineering 5758: 781786 Institute for Microelectronics, Vienna. http://www.iue.tuwien.ac.at/phd/hollauer/node16.html