Chapter 5 Combinational ATPG

Outline
Introduction to ATPG ATPG for Combinational Circuits Advanced ATPG Techniques

Input and Output of an ATPG

ATPG (Automatic Test Pattern Generation)
Generate a set of vectors for a set of target faults
Netlist Fault list

ATPG Program

Test vectors

Backtrack statistics

Aborted faults Undetected faults

Redundant faults

Components of An ATPG System

To detect easily detectable faults

Random pattern generator if faults remaining

Simulation-based test generator

Fault simulator if faults remaining

Find all faults captured by current vectors

new vector generated

Algorithmic pattern generator (ATPG)

Generate vectors for undetected faults or prove them to be undetectable

4

Revisiting Fault Coverage

Fault efficiency (ATPG efficiency)
Percentage faults have been successfully processed by a ATPG Proving a fault undetectable testing the fault

Undetectable faults can cause performance, power, reliability problems, etc. Faults may be masked by undetectable faults.

# of detected faults Fault coverage= Total # of faults # of detected faults Fault efficiency= Total # of faults- # of undetectable faults
5

Fully V.S. Partially Specified Patterns

A fully specified test pattern (every PI is either 0 or 1) A partially specified test pattern (certain PIs could be unknown)

0 0 1 1

0/1 stuck-at 1 0/1 1

1 x 1 x

1/0 stuck-at 0 1/0 1

Applications of partially specified test patterns

Test compaction Finding pattern of best test power, delay, etc.

Test Compaction
To reduce the number of test vectors as long as we keep the same detectable fault coverage. Test compaction is important for randomly generated patterns.
Even for vectors generated by an ATPG, since the order of processing faults will decide which vectors are discovered first.

An Example of Different Vectors Detecting the Same Faults

Assume we know the vectors and their detectable faults
If we start from f1, we find v1 to detect (f1, f3, f5). And then continue with f2. We find v2 to detect it. And for the remaining f4, we find v3 for detection. In total, we need 3 vectors.

v1 v2 v3 v4

f1 x x x

f2 x x

f3 x x x

f4

f5 x x x
8

An Example of Different Vectors Detecting the Same Faults (cont.)

With the same assumption
If we order the faults as f4, f2, f5, f3, f1. For f4, we find v3 to cover (f3, f4, f5) And for f2, we find v2 or v4 to cover (f1, f2) In total, we only need 2 vectors. f1 x x x f2 x x f3 x x x f4 f5 x x x
9

v1 v2 v3 v4

Test Compaction Methods

Use fault dictionary
Find essential vectors
No other vector can test faults covered only by essential vectors.

Find minimum vectors to cover all rest faults

A NP-complete problem.

Try different orders of input vectors in a fault simulator.

10

Other Test Compaction Methods

Static compaction
After a set of vectors has been generated Use D-intersection For example, t1=01X t2=0X1 t3=0X0 t4=X01 after compaction: t13=010 t24=001

Dynamic compaction
Process generated vectors on-the-fly After generate a test for a fault, choose a secondary target fault to be tested and try to test the second fault by dont cares (X) not assigned by the first fault.

11

Combinational ATPG
Test Generation (TG) Methods
Exhaustive methods Boolean Equation Structural Analysis Implication Graph

Milestone Structural ATPG Algorithms

D-algorithm [Roth 1967] 9-Valued D-algorithm [Cha 1978] PODEM [Goel 1981] FAN [Fujiwara 1983] Other advanced techniques

12

Exhaustive Test Generation

Explore all possible input combinations to find input patterns detecting faults Complexity ~ O(n2 no_pi)

Generate tests for the stuck-at 0 fault, .

Inputs 000 001 010 011

f 0 0 0 0 0 1 1 1

f 0 0 0 0 0 1 0 1

a b

stuck-at 0

f c

100 101 110 111

Boolean Equation Method

f = ab+ac, f = ac T = the set of all tests for fault = {(a,b,c) | ff=1} = {(a,b,c) | f*f+f*f=1} = {(a,b,c) | (ab+ac)(ac)' + (ab+ac)'(ac) = 1 } = {(a,b,c) | abc'=1} = { (110) }.
c a b stuck-at 0 f

The complexity is high with the computation of faulty function.

Boolean Difference Method

ff=1 == (=0) (f(=0)f(=1)) for stuck-at 1, or (=1) (f(=0)f(=1)) for stuck-at 0 Define Boolean difference df/d=f(=0)f(=1)
Meaning any change at can be observed at the outputs of f().

15

Example of Boolean Difference with Fault at PIs

a b
a stuck-at 0 X

f= ab + ac c
df/da = f(a=0) f(a=1) = 0 (b+c) = (b+c) Test-set for a s-a-0 = {(a,b,c) | a (b+c)=1} = {(11x), (1x1)}.
Fault activation requirement Fault sensitization requirement

Boolean Difference for Internal Signals

Calculation
Step 1: convert the function F into a new one G that takes the signal w as an extra primary input Step 2: dF(x1, , xn)/dw = dG (x1, , xn, w)/dw
w x1 . . . xn x1 . . . xn

Free w F

17

Example of Boolean Difference with Internal Fault

a b
h stuck-at 0 X

f= ab + ac c
G(i.e., F with h floating ) = h + ac dG/dh = G(h=0) G(h=1) = (ac 1) = (a+c) Test-set for h s-a-1 is { (a,b,c)| h (a'+c')=1 } = { (a,b,c)| (a'+b') (a'+c')=1 } = { (0xx), (x00) }. Test-set for h s-a-0 is {(a,b,c)| h (a'+c')=1} = {(110)}.
For fault activation For fault sensitization
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Chain Rule
A B C D

f G(f(A, B), C, D) {A,B} and {C,D} have no variables in common

f = AB and G = f + CD dG/df = (C + D) and df/dA = B dG/dA = (dG/df) (df/dA) = (C+D) B

An Input vector v sensitizes a fault effect from A to G iff v sensitizes the effect from A to f and from f to G

19

Test Generation Based on Structural Analysis

Important algorithms
D-algorithm [Roth 1967] 9-Valued D-algorithm [Cha 1978] PODEM [Goel 1981] FAN [Fujiwara 1983]

Key techniques
Find inputs to (1) activate, and (2) propagate the fault through sensitized paths to POs Branch and bounds
20

Structural Test Generation

ATPG traverse circuit structures by the following process:
Select targets Which path to propagate fault? Which line to assign value? How to activate fault? How to propagate fault?

More targets

Make decisions No Yes Pattern found? Yes End Correct results? No Delete previous decisions If no more decision to be deleted, select new targets.
21

More decisions

Common Concepts for Structural Test Generation

Fault activation
Set the faulty signal to either 0 or 1 A line justification problem

Fault propagation
Select propagation paths to POs Inputs to the gates on the propagation paths are set to non-controlling values if the inputs are not on the path.
Side inputs are set to non-controlling values.

Multiple line justification problems

Line justification
Find inputs that force certain signals to be 0 or 1.
22

Examples of Fault Activation and Propagation for Stuck-at Faults

Fault activated by inverting the signal value: d=1. Fault propagation
Fault propagated to f by e=0.

Line justification
To assign d=1, we need (a b)=(1 1). To assign e=0, we need c=0.

a b

d stuck-at 0 X d=1 for fault activation f

e=0 for fault propagation

23

What are the Decision Points?

On fault propagation
We select propagation paths to POs. Involve decisions on which paths to choose.

On line justification
Given a signal to justify, we need to make a decision on which inputs to set. For example, to set the output of an OR gate to 1, we need to choose which input to set to 1.

Backtrack
If we make a wrong decision (guess), we return and erase the decision (, and make another one). All decisions are recorded.
24

Branch-and-Bound Search
Test Generation is a branch-and-bound search
Every decision point is a branching point If a set of decisions lead to a conflict (or bound), a backtrack is taken to explore other decisions

A test is found when

(1) fault effect is propagated to a PO (2) all internal lines are justified
Since the search is exhaustive, it will find a test if one exists No test is found after all possible decisions are tried
Target fault is undetectable

25

An Illustration of Branch and Bounds

Assume a, b, and c are internal signals
a
0 1

b
0 1

c
0 1

Solution space with a=0, b=0

Solution space with a=0, b=1, c=0

Solution space with a=0, b=1, c=1

Solution space with a=1

26

Decision on Fault Propagation Path

d a b c G1 G6 e G3 G4
G5 or G6

G5

f1

f2

Decision tree before we start: Fault activation

G1=0 {a=1, b=1, c=1} G3=0

G5

G6

Fault propagation through G5 or G6 Decision through G5:

d=1 G4=1 The resulting test is (1111X) e=0 The resulting test is (111x0)

Decision through G6:

27

Decisions On Line Justification

a b c d k q l m n o e f h p r s

q=1 k=1
backtrack a=1, b=1 c=1, d=1 m=0, n=0 r=0

l=1

Fault activation set h to 0 Fault propagation e=1, f=1 o=0 m=1 n=1 Fault propagation q=1, r=1 To justify q=1 l=1 or k=1 Decision point c=0 (Success) Decision: l =1 c=1, d=1 m=0, n=0 r=0 inconsistency at r backtrack ! Decision: k=1 a=1, b=1 To justify r=1 m=1 or n=1 ( c=0 or d=0) Done !

r=1

28

Implications
Implications
Computation of the values that can be uniquely determined
Local implication: propagation of values from one line to its immediate successors or predecessors Global implication: the propagation involving a larger area of the circuit and re-convergent fanout

Maximum Implication Principle

Perform as many implications as possible It helps to either reduce the number of problems that need decisions or to reach an inconsistency sooner

29

An Example of Implication to Influence Decisions

d a b c G2 G1 G6 e G3 G4 f2 G5 f1

Fault activation
G1=0 {a=1, b=1, c=1} {G3=0, G2=0} G5=0

Fault propagation through G6 only Decision through G6:

G4=1 e=0 test pattern is (111x0)

30

Milestone Structural Test Generation Methods

D-algorithm [Roth 1967] 9-Valued D-algorithm [Cha 1978] PODEM [Goel 1981] FAN [Fujiwara 1983] Other advanced techniques

31

The D-Algebra
Allow the representation of the good and faulty behavior at the same time. Formally define/generate decision points in fault activation and propagation Introduce the symbol D in addition to 0, 1, x D = 1/0 (D 0/1) represents a signal which has value 1 in fault-free circuit and 0 in the faulty circuit.
D D D D D D D D D 0 D D 0 D D D D D D D D 1
32

Forward implication conditions for NOT, AND, OR in D-algebra

A Quick Overview of DAlgorithm

A structural algorithm Use 5-value logic (0, 1, X, D, D) Try to activate and propagate fault to outputs first with internal justification.
Then apply branch and bounds on line justification problems.

33

Fault Activation
Specify the minimal input conditions which must be applied to a logic element to produce an error signal at its output.
Stuck-at faults at an AND output: Stuck-at-0 fault: 11D Stuck-at-1 fault: 0xD and x0D More complex fault model, e.g., bridging faults, gate type errors, can also be modeled.

34

Fault Activation of Complex Fault Models

Apply the concept of Boolean equation method
List the set of input patterns for function F. F is the (local) representation function of the fault site. (1) fault-free output=0 {F=0} (2) fault-free output=1 {F=1} (3) faulty output=0 {Ff=0} (4) faulty output=1 {Ff=1}

{F=0} {Ff=1} or {F=1} {Ff=0} Example: 2-input AND gate output stuck-at 1
{F=0}={00, 01, 10}, {Ff=1}={00, 01, 10, 11}, {F=1}={11}, {Ff=0}={} {F=0} {Ff=1} = {00, 01, 10} {F=1} {Ff=0} = {}
35

Example of Complex Fault Models

Assume the fault is to change a AND gate to an OR gate
{F=0}={00, 01, 10}, {Ff=1}={01, 10, 11}, {F=1}={11}, {Ff=0}={00} {F=0} {Ff=1} = {01, 10} {F=1} {Ff=0} = {}

Apply 01, we produce a 0/1 (D) at the output Apply 10, we also produce a (D) 0/1.

36

D-frontiers and J-fontiers

Two most important data structures in the Dalgorithm.
Both store a list of gates.

D-frontiers
Where to choose the propagation paths. D-frontiers should not be empty during the search of test patterns.

J-frontiers
Where to perform line justifications. J-frontiers will be empty after a test pattern is found.
37

D-frontiers
D-frontiers are the gates whose output value is X, while one or more inputs are D or D.
d
1 a 1 b c 1

G5 G1
D

f1 G6 X

f2

G3

G4

Fault activation G1=0 { a=1, b=1, c=1 } { G3=0 } Fault propagation can be done through either G5 or G6
D-frontiers={G5, G6}
38

J-frontiers
J-frontier: is the set of gates whose output value is known (i.e., 0 or 1), but is not implied by its input values.
a b c d k q l m n o e f h p r s

Fault activation set h to 0 Fault propagation e=1, f=1 o=0 Fault propagation q=1, r=1 We need to justify both q=1 and r=1: J-frontiers={q, r}.

39

D-drive Function
The D-drive selects a gate in the D-frontier and attempts to propagate the D and/or Dfrom its input(s) to its output by setting side-inputs to non-controlling values.
D X To drive D to the output, we need to set the side-input to 1. D 1 D

For more complex functions, we can use the truth table of 5-value logics.
40

Implication in D-Algorithm
Involve D and D in the implication. Basic principles are guided by the truth table of each logic gate (complex cell). Examples are given in the following pages.

41

Local Implications considering D/D (Forward)

Before 0 1 1 1 D' D x x x x 0 a x a 0 x 1 1
J-frontier={ ...,a }

After 0 1 0 a 0 a

1 0 D' D

J-frontier={ ... }

D-frontier={ ...,a }

D-frontier={ ... }

42

Local Implications considering D/D (Backward)

Before x x x 1 x x 1 0 0 a x 1 1 0 1
J-frontier={ ... }

After 1 0 0 a 1 1 1

x x

J-frontier={ ...,a }

1 x

43

Backward local Implication by Prime Cubes

Prime Cubes
A simplified form of truth table. Circle groups of 0 or 1 in the Karnaugh map.
a b
a 0 b 0 0 0 1

f Prime cubes of AND

a 1 0 x

b 1 x 0

f 1 0 0
44

Backward Implication for Complex Cells

Find the prime cubes of the function f(a,b,c) = ac + b
b 1 0 1 1

0 c

a 0 x 1 x

b x 1 0 0

c 0 x x 1

f 1 1 0 0

In this example, if we want to justify f=0 and we know c=1, then we also obtain the backward implication of ab=X0
45

Checking Consistency
Consistency check for 5-V logic

We might assign different requirements from different decisions. We have to make sure every signal have compatible assignment in the circuit.

0 0 1 X D D 0 0

1 1 1

X 0 1 X D D

D D D

D D D
46

Terminating Conditions for DAlgorithm

Success:
(1) Fault effect at an output (D-frontier may not be empty) (2) J-frontier is empty

Failure:
(1) D-frontier is empty and fault is not at POs (2) No decision left but J-frontier is not empty

47

Propagation Phase of the DAlgorithm Choose signals to

activate fault Perform implication, and check consistency no

No D-frontier left

Backtrack

Consistent? yes

(remove implied signals)

(D-drive) Select a D-frontier and Propagate the fault Backtrack

(remove implied signals)

no

Is there a D or D at PO? yes

Fail

Line justification
(next page)
48

Line Justification Phase

Test generated no Any un-justified line? J-frontier not empty yes Select an un-justified line, and choose inputs for the gate (record decisions) Perform implication, and check consistency update J-frontier Consistent?
No decision left, but J-frontier not empty Line justification failed No alternative decisions

yes

Backtrack
(remove last decisions and implied signals recover J-frontiers)

no

49

D-Algorithm Example
I2
1

I1 1 I4 I3
0 1

G1

G4 G5 G6 G7

1 D 1 1

G2 D

sa1

G9

G3 0

Fault activation set G2 to 0 I2=1, I3=1, D-Frontier={G5, G6}, JFrontier={} Fault propagation select G5 I1=1 G1=0 G4=1, D-Frontier={G6, G9}, J-Frontier={} Fault propagation select G9 G6=1, G7=1 I4=0, G3=0 I4=1 (Contradictory) propagation fails, backtrack to select another Dfrontier from {G6}.

50

D-Algorithm Example (Cont.)

I2
1

I1 1 I4 I3
1 1

G1

G4 G5 G6 G7

1 D D 1

G2 D G3

sa1
0

G9

Fault propagation

select G6

I4=1, G3=0, G7=1

51

9-Value D-Algorithm
Logic values (fault-free / faulty)
{0/0, 0/1, 0/u, 1/0, 1/1, 1/u, u/0, u/1, u/u}, where 0/u={0,D'}, 1/u={D,1}, u/0={0,D}, u/1={D',1}, u/u={0,1,D,D'}.

Advantage:
Automatically considers multiple-path sensitization, thus reducing the amount of search in D-algorithm The speed-up is NOT very significant in practice because most faults are detected through single-path sensitization

Example: 9-Value D-Algorithm

d'
1/u 0/u

h i j
u/1

1/u D

1/1

0/u

e' a b c
0/1 u/1 u/1

u/1 D

u/0

n
D

k
u/1

f'
u/1

l
u/1

u/0

m
u/1

Fault activation set a to 0/u h=1/u, DFrontier={g} Fault propagation select g b=u/1, c=u/1 D-frontier={i, k, m} Fault propagation select i d=1/u Dfrontier={k, m, n} Fault propagation select n h=1; j, k, l, m=u/1 J-frontier={j, k, l, m, h} Justify j e=u/1 e=u/0 (consistent) Similarly f=u/1

Selecting Inputs for 9-Value DAlgorithm

To derive the input test vector, we choose the values consistent with both fault-free and faulty circuits.
A = (0/u)={0, D} B = (1/u)={1, D} C = (1/u)={1, D} D = (u/1)={1, D} E = (u/1)={1, D} F = (u/1)={1, D} 0 1 1 1 1 1

The final vector

(A,B,C,D,E,F) = (0, 1, 1, 1, 1, 1)

54

Problems with the D-Algorithm

Assignment of values is allowed for internal signals
Large search space Backtracking could occur at each gate
TG is done through indirect signal assignment for FA, FP, and LJ, that eventually maps into assignments at PIs The decision points are at internal lines The worst-case number of backtracks is exponential in terms of the number of decision points (e.g., at least 2k for k decision nodes) D-algorithm will continue even when D-frontier is empty

Inefficient for large circuits and some special classes of circuits

Example: ECAT (error-correction-and-translation) circuits.
55

ECAT Circuits
A B C E F G H sa0 J K L M Q R N P

Primitive D-cube: A = B = 1, H = D To propagate through P to output R

One possible choice is N = Q = 1, but this is impossible.

D-algorithm will exhaustively enumerate all internal signals to confirm that N = Q = 1 is impossible.
56

The Decision Tree

A B C E F G H sa0 J K L M
J=1,K=0 Q=1 N=1 J=0,K=1 L=0,M=0 C=0,E=0 F=0,G=1 Justification impossible L=1,M=1

C=1,E=1 F=1,G=0

57

PODEM: Path-Oriented DEcision Making

The test generation is done through a sequence of direct assignments at PIs Decision points are at PIs, thus the number of backtracking might be fewer Also a structural algorithm Also use 5-value logic and D-frontiers. Also a branch and bounds algorithm. In PODEM, to activate and propagate faults, a series of objective line justifications are selected (similar to Dalgorithm), but then each objective is backtraced to PIs and a forward simulation is used to perform implications and confirm consistency .
58

Search Space of PODEM

Complete Search Space
A binary tree with 2n leaf nodes, where n is the number of PIs For example, {a, b, c, d} are PIs in the following binary tree
a 0 b 1 b

0 c 0 d F 1 d F

1 c 0 d F 1 d S d F 0 c 1

1 c 0 1 d F
59

d S

d F

PODEM: Recursive Algorithm

PODEM () begin If(error at PO) return(SUCCESS); If(D-Frontier is empty) return(FAILURE); /* terminating conditions*/ (k, vk) = Objective(); (j, vj) = Backtrace(k, vk); Imply (j, vj); Imply (j, vj); Imply (j, x); return (FAILURE); end
60

/* choose a line, k, to be justified */ /* choose the PI, j, to be assigned */ /* make a decision */

If ( PODEM() == SUCCESS ) return (SUCCESS); /* reverse vj */

If ( PODEM() == SUCCESS ) return(SUCCESS); /* we have wrong objectives */

An Example PI Assignments in PODEM

Assume we have four PIs: a, b, c, d. Decision: a=0 Decision: b=0 fails a Reverse decision: b=1 1 0 Decision: c=0 fails b b Reverse decision: c=1 0 1 Decision: d=0 fails Failure c Decision: d=1 fails 1 0 Backtrack: d=x Failure d Backtrack: c=x 1 0 Backtrack: b=x Failure Failure Reverse decision: a=1
61

Objective() and Backtrace()

Objective()
Guide decisions to activate and propagate faults. Lead to sets of line justification problems. A signal-value pair (w, vw)

Backtrace()
Guide decisions to line justification. Backtrace maps a objective into a PI assignment that is likely to contribute to the achievement of the objective Traverses the circuit back from the objective signal to PIs Involves finding an all-x path from objective site to a PI, i.e., every signal in this path has value x A PI signal-value pair (j, vj) No signal value is actually assigned during backtrace !
62

Objective() Routine
Objective() { /* The target fault is w s-a-v */ if (the value of w is x) obj = (w, v ); else { select a gate (G) from the D-frontier; select an input (j) of G with value x; c = controlling value of G; obj = (j, c); } return (obj); }
63

fault activation fault propagation

Backtrace() Routine
Backtrace(w, vw) { /* Maps objective into a PI assignment */ G = w; v = vw; while (G is a gate output) { /* not reached PI yet */ inv = inversion of G; /* inv=1 for INV, NAND, NOR*/ select an input (j) of G with value x; G = j; /* new objective node */ v = vinv; /* new objective value */ } return (G, v); /* G is a PI */ }
64

Backtrace Example
Objective to achieved: (F, 1)
X a b X X X X F=1

Backtrace find a=0; Forward simulate a=0

1 a b 0 1 X X F=1

F is still x after we set a=0

65

Backtrace Example (Cont.)

Objective to achieved: (F, 1)
1 a b 0 1 X X F=1

Backtrace find b=1; Forward simulate b=1

1 a b 0 1 1 0 F=1

F=1
66

Terminating Conditions
Success:
Fault effect seen at an output.

Failure:
D-frontier is empty and fault is not at any POs.

67

Example: PODEM
d'
1 0

h i j
0

1 D

e' a b c
0/1 1 1

0 D

n
X

k
1

f'
X

l
X

m
X

Fault activation set a to 0 h=1, D-Frontier={g} Fault propagation select g b=1, c=1 Dfrontier={i, k, m} Fault propagation select i d=1 D-frontier={k, m, n} Fault propagation select n objective =(k, 1) Backtrace e=0 e=1 j=0 Empty D-frontier and fault not at PO Backtrack to e=1 e=0 j=1, k=D

Example: PODEM (Cont.)

d'
X 0

h i j
1

1 D D-frontier={m, n} Fault propagation select n objective =(m, 1) Backtrace f=0 f=1 l=0 Empty D-frontier and fault not at PO Backtrack to f=1 f=0 l=1, m=D

e' a b c
0/1 1 1

1 D

n
D

k
D

n=D, success!!

f'
1

l
1

m
D

Another PODEM Example: ECAT

A B C E F G H J K L M Q N
Fault activation set H to 1 A=1, B=1, DFrontier={P} Fault propagation select P objective =(N, 1) Backtrace C=1 Backtrace E=1 J=0, L=1 Backtrace F=1 Backtrace G=1 K=0, M=1 N=0, R Q=1 P=D R=D

sa0

Note that there is no backtracking in this example.

70

Characteristics of PODEM
A complete algorithm like D-algorithm Will find the test pattern if it exists Use of backtrace() and forward simulation No J-frontier, since there are no values that require justification No consistency check, as conflicts can never occur No backward implication Backtracking is implicitly done by simulation rather than by an explicit and time-consuming save/restore process Experimental results show that PODEM is generally faster than the D-algorithm
71

The Selection Strategy in PODEM

In Objective() and Backtrace()
Selections are done arbitrarily in original PODEM The algorithm will be more efficient if certain guidance used in the selection of objectives and backtrace paths

Selection Principle
Principle 1: among several unsolved problems, attack the hardest one Ex: to justify a 1 at an AND-gate output Principle 2: among several solutions for solving a problem, try the easiest one Ex: to justify a 1 at OR-gate output

The key is to quantitatively define hard and easy.

Controllability As Guidance of Backtrace

We usually use controllability to guide the selection.
More details will be provided in Ch 6. Testability Analysis.

Objective (g, 1)

choose path g f for backtracing

Two unsolved problems e=1 and f=1 Choose the harder one: f=1 (lower probability of being 1).

Objective (g, 0)

choose path g f for backtracing

Two possible solutions: e=0 or f=0 Choose the easier one: f=0 (higher probability of being 0).

a=1/2 b=1/2 c=1/2 d=1/2

e=3/4 g f=1/4

Probability of being 1

FAN Fanout-Oriented Test Generation

Techniques to accelerate the test generation process
Immediate Implications Unique sensitization Headlines Multiple backtrace

74

Immediate Implications
A B C PODEM Initial objective L = 0 Backtrace to PI: B = 0 Implication: H = 1, K = 1, J = 0, L = 1 Fail backtrack.
75

H K E

J sa1 L

FAN Initial objective L = 0 Set J = K = E = 1 J=1 H=0 A=B=1 K=1 C=0

Unique Sensitization
A 1 0 B G1 1 G2 CD E D G3 1 D G4

F 1

Only one path to propagate D on signal C to output H. Set all the off-path inputs to non-controlling values. G1 = 1, E = 1, F = 1, A = 1 B=0

PODEM
Initial objective: set G1 to 1 Backtrace to PI: A = 0 assigning A = 0 will later block the propagation of D
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Head lines
Output of fanout-free regions with PIs as inputs.
Backtrace in FAN stop at headlines. Reduce search space.

bound lines Head lines

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Breadth-First Multiple Backtrace

All must be set to 1.

11 1

Both must be set to 1.

1 0

11 1

0
Set to 0 the input w/ easiest-to-control to 0 input.

PODEMs depth-first search is sometimes inefficient. Breadth-first multiple backtrace identifies possible signal conflicts earlier. Attempts to satisfy a set of objectives simultaneously
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Why Multiple Backtrace ?

Drawback of Single Backtrace
A PI assignment satisfying one objective may preclude achieving another one, and this leads to backtracking

Multiple Backtrace
Starts from a set of objectives (Current_objectives) Maps these multiple objectives into head-line assignments that is likely to

Contribute to the set of objectives Or show that objectives cannot be simultaneously achieved
0 Multiple objectives may have conflicting requirements at a stem 0 1 1
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Example: Multiple Backtrace

conflicting stem

A1 1 A B A2 0 E E1 1 E2 G 0 H 1

I=1

1
Consistent stem C

1 1

J=0 Stem_objectives Head_objectives

Current_objectives

Processed entry

(I,1), (J,0) (J,0), (G,0) (G,0), (H,1) (H,1), (A1,1), (E1,1) (A1,1), (E1,1), (E2,1), (C,1) (E1,1), (E2,1), (C,1) (E2,1), (C,1) (C,1) Empty restart from (E,1) (E,1) (A2,0) empty

(I,1) (J,0) (G,0) (H,1) (A1,1) (E1,1) (E2,1) (C,1) (E,1) (A2,0)

A A,E A,E A,E A A A A

C C C C C
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Multiple Backtrace Algorithm

Mbacktrace (Current_objectives) { while (Current_objectives ) { remove one entry (k, vk) from Current_objectives; switch (type of entry) { 1. HEAD_LINE: add (k, vk) to Head_objectives; 2. FANOUT_BRANCH: j = stem(k); increment no. of requests at j for vk; /* count 0s and 1s */ add j to Stem_objectives; 3. OTHERS: inv = inversion of k; c = controlling value of k; select an input (j) of k with value x; if ((vk inv) == c) add(j, c) to Current_objectives; else { } } (to next page) for every input (j) of k with value x add(j, c) to Current_objectives; }

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Multiple Backtrace (cont)

if(Stem_objectives ) { remove the highest-level stem (k) from Stem_Objectives; vk = most requested value of k; if (k has contradictory requirements and k is not reachable from target faults) return (k, vk) /* recursive call here */ add (k, vk) to Current_objectives; return (Mbacktrace(Current_objectives); } else { remove one objective (k, vk) from Head_objectives; return (k, vk); } }
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FAN Algorithm
FAN() begin if Imply_and_check() = FAILURE then return FAILURE if (error at PO and all bound lines are justified) then begin justify all unjustified head lines return SUCCESS end if (error not at PO and D_frontier = ) then return FAILURE /* initialize objectives */ add every unjustified bound line to Current_objectives select one gate (G) from the D-frontier c = controlling value of G (to next page)
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FAN algorithm (cont)

for every input (j) of G with value x add (j,c) to Current_objectives /* multiple backtrace */ (i,vi) = Mbacktrace(Current_objectives) Assign(i,vi) if FAN() = SUCCESS then return SUCCESS Assign(i,vi) /* reverse decision */ if FAN() = SUCCESS then return SUCCESS Assign(i,x) return FAILURE end

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Advanced Concepts of ATPG

Dominator ATPG Learning algorithms State hashing Satisfiability-based methods and Implication graphs

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Dominators for Fault Propagation

Before
X D X X X X X

After unique D-drive analysis

X D X X

Unique D-Drive Implication

If every gates in D-frontier pass through a dominator (unique D-drive), we can set noncontrolling values at other side-inputs, and propagate D/D further.
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Learning Methods for ATPG

Learning process systematically sets all signals to 0 and 1 and discover what other signal values are implied.
Used extensively in implication. Ex. a=1 b=0, even a and b are not implied immediately by gate relationship.

Static learning
Start the learning process before ATPG

Dynamic learning
Start the learning process in between ATPG steps when some signal values are known Costly process
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Modus Tollens for Learning

Given

P Q is true
We can derive

~Q ~P is true

Example:
A B C D 1 F A B C

P and Q are Boolean statements ~Q means that Q is not true 1 D 0 F

E (B=1)

E (B=0)
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(B=0) (F=0) => ~(F=0) ~(B=0) => (F=1)

When A=1 (B=1) (F=1) => (F=0)

(Static Learning)

(Dynamic Learning)

Constructive Dilemma for Learning

Given

(1) P=>Q and R=>S, and (2) Either P or R is true

We can derive

Either Q or S is true.

Example:
Both [(a=0) => (i=0)] and [(a=1) => (i=0)] are true. Either (a=0) or (a=1) holds => (i=0)
1 1 1 0 0 1 i=0 1 1 0 a=1 1 1 1 0 i=0
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a=0

Modus Ponens for Learning

Given

F and F=>G are true

We can derive

G is true.

Example:
[a=0] and [(a=0) => (f=0)] => (f=0)

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Recursive Learning
From known signal values, try all possible decisions (recursively). If a certain signals have the same values among all decisions, they are implied values.

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Example of Recursive Learning

a b c d e1 g1 f1 e2 f2 i=0 For i, try g1=0 e1=0, f1=0 e1=0 g2 h l k i=0

j=1

For e1, try a1=0 a2=0, e2=0 For e1, try b1=0 b2=0, e2=0 e2=0 g2=0 l=0 k=1 f2=0

f1=0 For i, try h1=0 l=0 k=1

For f1, try c1=0 c2=0, f2=0 For f1, try d1=0 d2=0, f2=0

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State Hashing (EST)

Records and compare E-frontiers
E-frontiers are the cut between known signals and unknown parts.

Given identical E-frontiers

Previous implications can be used Or inconsistency can be deduced from the previous run.

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State Hashing Example

C=1 E=0 F=0 g k B=0 h Z F A=1 m n C=0 E=0 g k B=1 h A m Z n

Step
1 2 3 4 5

Input Choice B=0 C=1 E=0 A=1 F=0

E-frontier {B=D} {C=1, B=D} {g=1, m=D} {g=1, n=D} {Z=D}

Step 1 2 3

Input Choice C=0 B=1 E=0

E-frontier {h=D} {m=D} {g=1, m=D}

Match found at step 3

Process for detecting B s-a-1 Test pattern = (CEFBA)=(10001)

Process for detecting h s-a-1 Test pattern = (CEFBA)=(00011)

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Implication Graph ATPG

Translate circuits into implication graphs Use transitive closure graph algorithm to perform ATPG
Some decisions and implications are better assigned with graph algorithms. But experiences show that circuit structure is a very important information for ATPG.

Satisfiability-based algorithms are currently the fastest implementation for justification and commonly applied to verification problems.
We have a separate set of slides about SAT.

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Translating Gate to its Equivalent Implication Graph

Use NAND as an example A two-input NAND can be described completely by the following 3 equations. a c b c c ab Note that they cover all cubes. Implication graph Each node represents a signal variable. If there is a directed edge from one node (v1) to another (v2), v1 imply v2.
a b a b Equivalent implication graph for NAND.
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a b

c
c c

Perform Implication on the Graph

Assume we have c=0, we add an edge for c c
c c == c+c == c

Extra implication are found by tracing linked nodes. In this example, a a and b b, hence a=1, b=1. a 0 0 1 1 b 0 1 0 1

1 1 0 1
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Truth table for implication a b ==a+b

Implication Graph Examples

a b c e d F
d e c d e c a b F a b F

Equivalent Circuit Implication Graph

Implication Graph d=0 New paths: a-d-d-a, F-d-d-F, b-d-d-b New conditions: a a, F F, b b Implied logic values: a=1, F=1, b=1

Implication Graph F=1 (i.e., de=0) New paths: b-d-e-b, b-e-d-b New conditions: b b Implied logic values: b=1
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