On-Chip Implementation of High Speed and High resolution Pipeline Radix 2 FFT Algorithm

N. Mahdavi, R. Teymourzadeh, IEEE Student Member, Masuri Bin Othman

Arak university, Iran, VLSI Design Center, Institute of Microengineering and Nanoelectronics (IMEN) Universiti Kebengsaan Malaysia, 43600 Bangi, Selangor, Malaysia [email protected] , [email protected] , [email protected]
Abstract- A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of N 2 log 2 N 11 . Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

The proposed method shows high performance of the FFT algorithm. The principle architecture is based on using a memory to keep input and output data. Thus, it reduces hard ware complexity. All the blocks are designed to operate with the same clock frequency. These stages implement as pipeline and parallel to reduce FFT calculations time. III. FFT BLOCK DIAGRAM DESCRIPTION Fig. 1, shows the main block diagram of the FFT algorithm. Each block will be investigated separately. A. Radix-2 Butterfly Algorithm First, the RAM is initialized by external microprocessor and the data are loaded to the RAM by bit reserve address pin. The Radix 2 Butterfly block is the primary prefatory step taken in DIT FFT [8,9]. This block calculates the complex number in (1) and (2), as follow.

I.

INTRODUCTION

Fast Fourier transform is a faster version of DFT which was invented by Cooley & Tuky in 1965 [1]. There are several types of FFT algorithms. Radix-2 is a practical algorithm to calculate FFT by using decimation in time (DIT) method. The main idea of decimation in time is to sunder the input string of hn with length of N 2 v into two substrings with odd and even indexes. The N-point DFT of hn can be achieved by suitable combining to N 2 -point DFT of each substring. Each one of them can be reduced to N 4 -point DFTs. This procedure will continue till only 2-point DFTs remains [2]. The final result is the formation of FFT algorithm. In 2006 petrovsky [3] implemented Radix 2-4 based on parallel-pipeline FFT-processors at structural level. He achieved 0.00201 MSE on his FFT algorithm. This paper shows the implementation of high speed and high resolution FFT based on parallel pipeline and floating point Radix-2 with the minimum MSE of 0.0001. The next section describes the principle of the FFT structure. The mathematical formulation and block diagram of pipeline FFT algorithm is described in section III. Section IV shows implementation and design result in brief. Finally, conclusion is expressed in section V. II. PRINCIPLE OF THE FFT STRUCTURE The computation of N-point FFT via decimation-in-time algorithm requires ON log 2 N complex multiplication time [7] and it will be increased if basic butterfly computation is used for adder and multiplication in decimation-in-time FFT algorithm. Additionally a complicated controller is also required. Furthermore, implementing fixed point FFT algorithm, results the output differs significantly in comparison to the expected output. To obtain the high speed and high resolution FFT algorithm, implementation of the floating point pipeline FFT is applied.

output1 input1 W k input 2

(1) (2)

output 2 input1 W input 2

k

Figure 1. The FFT block diagram

Hence, one complex multiplication and two complex additions are required in this calculation. If output1 X 01 iYo1 , output 2 X o 2 iYo 2 and

W k X wk iYW k we have:

X o1 iYo1 X i1 X W k X i 2 YW k Yi 2

X o 2 iYo 2 X i1 X W k X i 2 YW k Yi 2

iYi1 X W k Yi 2 YW k X i 2

(3) (4)

iYi1 X W k Yi 2 YW k X i 2

Thus, each butterfly requires four real multiplications and six real additions. If the above equations are implemented using fixed point calculations, the error possibility of the result will increase. These errors [4] consist of round-off, overflow and coefficient quantization errors. To reduce the errors and provide high resolution, floating point adder/subtractor is replaced. This adder/subtractor operates in 3 stages including mantis alignment, mantis addition/ subtraction and normalization. Thus, each of the above phases can be used as stages for pipeline implementation. We convert the first phase into two stages in order to achieve higher clock frequency [5], [6]. Fig. 2, and Fig. 3, show the block diagram of the pipeline adder/subtractor and multiplier. It is not necessary to adjust the exponents in multiplier. Since the normalized inputs are loaded to the multiplier, the mantises are multiplied and the exponents are added and amended. The result may be shifted one bit leftward. Thus the exponent will be decremented one unit.

Fig. 4, shows the internal schematic of the pipeline butterfly algorithm. To improve speed calculations in the Radix-2 butterfly algorithm, the pipeline registers are located after each addition, subtraction and multiplication blocks. Hence, the pipeline butterfly algorithm keeps the final result in the register to transfer it to the RAM by the next clock cycle. This FFT algorithm is exactly executed after N 2 Log 2 N 11 clock pulses. The 11 clock pulses delay is created by 11 pipeline registers in adder, subtractor and multiplier in a serial butterfly block. Additionally, parallel design of the FFT algorithm decreases the calculation time significantly. B. ROM and RAM Blocks The ROM in Radix-2 FFT algorithm has two look-up k tables to save W coefficients. These coefficients are inherently complex numbers so the real & imaginary parts are separately kept on that. Since the amplitude of the sine and cosine are the same in the four quarters, (they only k differ in the signs) W are calculated just for k 0 to k N 4 and related sign are saved for k 0 to N into the ROM. Thus, it avoids using a large number of gates in the FPGA board. There is a RAM in the FFT block diagram. According to the system workflow, two complex data must be read from the RAM simultaneously and loaded to the butterfly block. Meanwhile, the two outputs of the butterfly block have to be written in the RAM at the same time. Fig. 5, shows the internal structure of the RAM with the capability of reading and writing the two complex data simultaneously.

Figure 2. Pipeline floating point adder/ subtractor

Figure 3. Pipeline floating point multiplier

Figure 5. Internal structure of the RAM

Figure 4. Internal schematic of the pipeline butterfly algorithm

IV. IMPLEMENTATION RESULT The new architecture of the Radix-2 FFT algorithm Verilog code was written and simulated by Matlab software. The design code is downloaded to the Virtax-2 FPGA board. From Xilinx ISE synthesize report, it was shown minimum clock period is 9.94 ns (Maximum Frequency is 100.6 MHz). The chip layout on Virtex 2 FPGA board is shown in Fig. 6. Fig. 7, shows the output digital signal of the new Radix-2 FFT algorithm which simulated by Modelsim software. Fig. 8, shows the measured signal spectrum achieved by Radix-2 FFT algorithm for 1024 floating point complex data.

The output result appeared after 5131 clock pulses which proved the complex calculation of N 2 log 2 N 11 in the system. The System MSE was measured by Matlab software. It shows the mean squared error (MSE) of 0.0001.

V.

CONCLUSION

The new architecture of the high speed and high resolution of the parallel, pipeline and floating point Radix2 FFT algorithm was designed and investigated. High Speed FFT architecture was obtained by two methods. The pipeline structure and parallel design lead us to have high speed FFT algorithm. Additionally, using a internal RAM makes the design compatible with different type of FPGA board. The implementation result shows the maximum throughput of the 100.6 MHz in Virtex 2 FPGA board. Meanwhile, the resolution was increased by floating point calculation during the FFT process. The proposed FFT algorithm proves the latency of N 2 Log 2 N 11 , 5131 clock pulses for N 1024 with the mean squared error (MSE) of 0.0001. ACKNOWLEDGMENT We wish to thank our friend, Dr. Mohamad Amir Amini who has assisted us for completion of this dissertation. REFERENCES
[1] J. W. Cooley, J. W. Tukey, An Algorithm for the Machine Calculation of Complex Fourier series," Math of comp Vol. 19, pp. 297-301, 1965. A. Saidi, Decimation-in-time frequency FFT algorithm. Acoustics, Speech, and Signal Processing , ICASS-94, IEEE International Conference. Vol. 3, pp. 453-456, 1994 A.A. Petrovsky, S. L. Shkredov, Automatic Generation of SplitRadix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimization, Proceeding of the international symposium on parallel computing in Electrical engineering (PARELEC06), pp.181-186, 2006. E. C. Ifeachor, B. V. Jervis, Digital Signal Processing: A Practical Approch. Second Editiond. Prantice Hall, 2002. M. Morris Mano, Computer System Architectur. Third Edition. Prantice Hall. 1992. D. A. Patterson & J. L. Hennssy. Computer Organization & Design: the Hardware/ Software Interface. Second Edition. Morgan Kaufman Publishere Inc. 1998. Lo sing Cheng, A. Miri, Tet Hinb Yeap, Efficient FPGA Implementation of FFT based Multipliers, IEEE Conference Electrical and Computer Engineering, pp. 1300-1303, 2005. K. S. Hemmert, K. D. Underwood, An Analysis of The DoublePrecision Floating-point FFT on FPGAs, 13th IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 171-180, April 2005. Shiqun Zheng, Dunshan Yu, Design and implementation of a parallel real-time FFT processor, 7th IEEE conference on Solid-State and Integrated Circuits Technology, Vol. 3, pp. 165-168, Oct 2004.

Figure 6. The core layout on FPGA board

[2] [3]

[4] [5] [6] [7] Figure 7. The output digital signal of the system [8]

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Figure 8. Signal spectrum of high speed radix-2 FFT algorithm