INTEGRATED CIRCUITS

DATA SHEET

TDA8703 8-bit high-speed analog-to-digital converter

Product specication Supersedes data of April 1993 File under Integrated Circuits, IC02 1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

FEATURES 8-bit resolution Sampling rate up to 40 MHz High signal-to-noise ratio over a large analog input frequency range (7.1 effective bits at 4.43 MHz full-scale input) Binary or two's complement 3-state TTL outputs Overflow/underflow 3-state TTL output TTL compatible digital inputs Low-level AC clock input signal allowed Internal reference voltage generator Power dissipation only 290 mW (typical) Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required. ORDERING INFORMATION TYPE NUMBER TDA8703 TDA8703T PACKAGE NAME DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm APPLICATIONS

TDA8703

General purpose high-speed analog-to-digital conversion Digital TV, IDTV Subscriber TV decoder Satellite TV decoders Digital VCR. GENERAL DESCRIPTION The TDA8703 is an 8-bit high-speed Analog-to-Digital Converter (ADC) for video and other applications. It converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level AC clock input signal is allowed.

VERSION SOT101-1 SOT137-1

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ILE DLE AILE B fCLK/fCLK Ptot Notes 1. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz). PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stages supply current DC integral linearity error DC differential linearity error AC integral linearity error 3 dB bandwidth maximum conversion rate total power dissipation note 1 note 2; fCLK = 40 MHz note 3 CONDITIONS MIN. 4.5 4.5 4.2 40 TYP. 5.0 5.0 5.0 28 19 11 19.5 290

TDA8703

MAX. 5.5 5.5 5.5 36 25 14 1 1/2 2 415

UNIT V V V mA mA mA LSB LSB LSB MHz MHz mW

2. The 3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input). 3. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clock signal. b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor.

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

BLOCK DIAGRAM

TDA8703

clock inputs
handbook, full pagewidth

V CCA 7

CLK 16

CLK 17

VCCD 18

TC 21

CE 22

STABILIZER

CLOCK DRIVER

DEC 5

VRT 9

TDA8703 TDA8703T

12 D7 13 D6 14 D5 15 D4 analog voltage input VI 8 ANALOG - TO - DIGITAL CONVERTER LATCHES TTL OUTPUTS 23 D3 24 D2 1 D1 2 D0 VRB 4 LSB data outputs MSB

19

VCCO overflow / underflow output

OVERFLOW / UNDERFLOW LATCH 3 AGND analog ground 20 DGND digital ground

TTL OUTPUT

11

MGA015

Fig.1 Block diagram.

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

PINNING SYMBOL PIN D1 D0 AGND VRB DEC n.c. VCCA VI VRT n.c. O/UF D7 D6 D5 D4 CLK CLK VCCD VCCO DGND TC CE D3 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION data output; bit 1 data output; bit 0 (LSB) analog ground reference voltage bottom (decoupling) decoupling input (internal stabilization loop decoupling) not connected positive supply voltage for analog circuits (+5 V) analog voltage input reference voltage top (decoupling) not connected overow/underow data output data output; bit 7 (MSB) data output; bit 6 data output; bit 5 data output; bit 4 clock input complementary clock input positive supply voltage for digital circuits (+5 V) positive supply voltage for output stages (+5 V) digital ground input for two's complement output (TTL level input, active LOW) chip enable input (TTL level input, active LOW) data output; bit 3 data output; bit 2 Fig.2 Pin configuration.
V CCA VI V RT n.c. O/UF D7
handbook, halfpage

TDA8703

D1 D0 AGND V RB DEC n.c.

1 2 3 4 5 6 7 8 9 10 11 12
MLB034

24 23

D2 D3

22 CE 21 20 19 TC DGND V CCO

TDA8703/ TDA8703T 18 V CCD

17 16 15 14 13 CLK CLK D4 D5 D6

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCCA VCCD VCCO VCCD VCCA VCCO VVI VCLK/VCLK IO Tstg Tamb Tj Notes 1. The circuit has two clock inputs CLK and CLK. There are four modes of operation: PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage differences supply voltage differences supply voltage differences input voltage range AC input voltage for switching (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND note 1; referenced to DGND CONDITIONS MIN. 0.3 0.3 0.3 1.0 1.0 1.0 0.3 55 0

TDA8703

MAX. +7.0 +7.0 +7.0 +1.0 +1.0 +1.0 +7.0 2.0 +10 +150 +70 +125

UNIT V V V V V V V V mA C C C

a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clock signal. b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL RESISTANCE SYMBOL Rth j-a SOT101-1 SOT137-1 PARAMETER from junction to ambient in free air 55 75 K/W K/W VALUE UNIT

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

TDA8703

CHARACTERISTICS VCCA = V7 V3 = 4.5 V to 5.5 V; VCCD = V18 V20 = 4.5 V to 5.5 V; VCCO = V19 V20 = 4.5 V to 5.5 V; AGND and DGND shorted together; VCCA VCCD = 0.5 V to +0.5 V; VCCO VCCD = 0.5 V to +0.5 V; VCCA VCCD = 0.5 V to +0.5 V; Tamb = 0 C to +70 C; unless otherwise specied (typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 C). SYMBOL Supply VCCA VCCD VCCO ICCA ICCD ICCO Inputs CLOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input impedance input capacitance VCLK/VCLK = 0.4 V VCLK/VCLK = 0.4 V VCLK/VCLK = VCCD fCLK/fCLK = 10 MHz fCLK/fCLK = 10 MHz note 1; DC level = 1.5 V 0 2.0 400 0.5 4 4.5 0.8 VCCD 100 300 2.0 V V A A A k pF V analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stage supply current all outputs LOW 4.5 4.5 4.2 5.0 5.0 5.0 28 19 11 5.5 5.5 5.5 36 25 14 V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCLK VCLK AC input voltage for switching (peak-to-peak value) TC AND CE (REFERENCED TO DGND) VIL VIH IIL IIH VVI(B) VVI(0) VOS(B) VVI(T) VVI(255) VOS(T) VVI(p-p) IIL IIH Zi Ci 1996 Aug 26 LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current

0 2.0 VIL = 0.4 V VIH = 2.7 V 400 1.33 output code = 0 VVI(0) VVI(B) output code = 255 VVI(T) VVI(255) VVI = 1.4 V VVI = 3.6 V fi = 1 MHz fi = 1 MHz 7

1.41

0.8 VCCD 20

V V A A V

VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) input voltage (bottom) input voltage offset voltage (bottom) input voltage (top) input voltage offset voltage (top) input voltage amplitude (peak-to-peak value) LOW level input current HIGH level input current input impedance input capacitance 1.48 1.455 1.55 0.125 3.2 3.115 1.66 60 3.36 3.26 1.71 0 120 10 14 1.635 V 0.155 V 3.5 0.115 1.75 180 V V V A A k pF 3.385 V

0.085

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

TDA8703

SYMBOL Reference resistance Rref Outputs

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

reference resistance

VRT to VRB

220

DIGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND) VOL VOH IOZ fCLK/fCLK LOW level output voltage HIGH level output voltage output current in 3-state mode IO = 1 mA IO = 0.4 mA 0.4 V < VO < VCCD 0 2.7 20 0.4 VCCD +20 0 25 2.5 1 1/2 2 V V A

Switching characteristics (note 2; see Fig.3) maximum clock frequency 3 dB bandwidth differential gain differential phase fundamental harmonics (full-scale) harmonics (full-scale), all components supply voltage ripple rejection supply voltage ripple rejection 40 note 6 fi = 4.43 MHz 6 LOW-to-HIGH transition HIGH-to-LOW transition enable-to-HIGH enable-to-LOW disable-to-HIGH disable-to-LOW MHz

Analog signal processing (fCLK = 40 MHz) B Gd d f1 fall SVRR1 SVRR2 note 3 note 4 note 4 fi = 4.43 MHz fi = 4.43 MHz note 5 note 5 19.5 0.6 0.8 55 28 1 7.1 8 16 19 16 14 9 MHz % deg dB dB dB %/V

Transfer function ILE DLE AILE EB DC integral linearity error DC differential linearity error AC integral linearity error effective bits LSB LSB LSB bits

Timing (note 7; see Figs 3 to 6; fCLK = 40 MHz) tdS tHD tdLH tdHL tdZH tdZL tdHZ tdLZ sampling delay output hold time output delay time output delay time 3-state output delay times 3-state output delay times 3-state output delay times 3-state output delay times 2 10 20 25 20 20 12 ns ns ns ns ns ns ns ns

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

Notes 1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:

TDA8703

a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clock signal. b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor. 2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 2 ns. 3. The 3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input). 4. Low frequency ramp signal (VVI(p-p) = 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VVI(p-p) = 0.5 V, fi = 4.43 MHz) at the input. 5. Supply voltage ripple rejection: a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V: SVRR1 = 20 log (VVI(127) / VCCA) b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V: SVR2 = {(VVI(0) VVI(255)) / (VVI(0) VVI(255))} VCCA. 6. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz). 7. Output data acquisition: a) Output data is available after the maximum delay of tdHL and tdLH.

1996 Aug 26

Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

Table 1 Output coding and input voltage (referenced to AGND; typical values) BINARY OUTPUT BITS STEP 0 1 . . 254 255 Overow Table 2 VVI(p-p) 1.55 . . . 3.26 >3.26 O/UF D7 1 0 0 . . 0 0 1 0 0 0 . . 1 1 1 D6 0 0 0 . . 1 1 1 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1 Underow <1.55 1 1 1 . . 0 0 0

TDA8703

TWO'S COMPLEMENT OUTPUT BITS D7 D6 0 0 0 . . 1 1 1 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1

Mode selection TC X(1) 0 1 CE 1 0 0 D7-D0 high impedance active; twos complement active; binary active active O/UF high impedance

Note 1. X = dont care.

handbook, full pagewidth

CLK

1.3 V

sample N

sample N + 1 sample N + 2

VI t HD t dS 2.4 V D0 - D7 data N 1 1.3 V data N data N + 1 0.4 V t dLH t dHL

MEA105

Fig.3 Timing diagram.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

TDA8703

handbook, full pagewidth

CE input

reference level (1.4 V) 2.4 V

data outputs 0.4 V t dHZ t dLZ t dZH t dZL

MLB035 - 1

Fig.4 3-state delay timing diagram.

V CCO
handbook, halfpage

2 k VCCO
handbook, halfpage

S1 D0 to D7 C 5 k IN916 or IN3064

2 k D0 to D7 15 pF IN916 or IN3064

DGND
MGD691 MBB955

S2

DGND

Fig.6 Fig.5 Load circuit for timing measurement; data outputs (CE = LOW).

Load circuit for timing measurement; 3-state outputs (CE: fi = 1 MHz; VVI = 3 V); see Table 3.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

Table 3 Mode selection SWITCH S1 open closed closed closed SWITCH S2 closed open closed closed

TDA8703

TIMING MEASUREMENT tdZH tdZL tdHZ tdLZ INTERNAL PIN CONFIGURATIONS

CAPACITOR 15 pF 15 pF 5 pF 5 pF

handbook, halfpage

VCCO

handbook, halfpage

V CCA

D7 to D0 O/U

(x 90) VI

DGND
MGD692

AGND
MLB037

Fig.7 TTL data and overflow/underflow outputs.

Fig.8 Analog inputs.

handbook, halfpage

VCCO

handbook, halfpage

V CCD

CE TC DGND
MLB039

DGND
MGD693

Fig.9 CE (3-state) input.

Fig.10 TC (twos complement) input.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

TDA8703

handbook, full pagewidth

V CCA

VRT

VRB DEC

AGND
MCD188

Fig.11 VRB, VRT and DEC.

handbook, full pagewidth

VCCD

CLK 30 k 30 k

V ref

DGND

MCD189 - 1

Fig.12 CLK and CLK inputs.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number FTV/8901).

TDA8703

handbook, full pagewidth

D1

24

D2

D0

23

D3

AGND V RB

22

CE

21

TC DGND VCCO VCCD 22 nF 5V 22 (1)

DEC

20

n.c. 47 pF V CCA 4.7 F

6 TDA8703 TDA8703T

19

18

22 nF VI V RT 8 17 CLK 100 pF

16

CLK

4.7 F

22 nF n.c. 10 15 D4 DGND

O / UF AGND D7

11

14

D5

12

13
MGA014 - 1

D6

CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter Characteristics, note 1). CLK and CLK can be used in a differential mode (see Chapter Characteristics, note 1). VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity. If it is required to use the TDA8703 in a parallel system configuration, the references (VRB and VRT) of each TDA8703 can be connected together. Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703. Analog and digital supplies should be separated and decoupled. Pins 6 and 10 should be connected to AGND in order to prevent noise influence. (1) It is recommended to decouple VCCO through a 22 resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS load device.

Fig.13 Application diagram.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

PACKAGE OUTLINES DIP24: plastic dual in-line package; 24 leads (600 mil)

TDA8703

SOT101-1

seating plane

ME

A2

A1 c Z e b1 b 24 13 MH w M (e 1)

pin 1 index E

12

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015AD EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-01-23

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

TDA8703

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

A X

c y HE v M A

Z 24 13

Q A2 A1 pin 1 index Lp L 1 e bp 12 w M detail X (A 3) A

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)

0.9 0.4 0.035 0.016

0.012 0.096 0.004 0.089

0.019 0.013 0.014 0.009

8 0o

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-01-24

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

TDA8703

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.

1996 Aug 26

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Philips Semiconductors

Product specication

8-bit high-speed analog-to-digital converter

DEFINITIONS Data sheet status Objective specication Preliminary specication Product specication Limiting values

TDA8703

This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1996 Aug 26

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