MC146818A

I
I

Advance

Information

CMOS

REAL-TIME CLOCK PLUS RAM (RTC)

The MC146818A Real-Time Clock plus RAM is a peripheral device which includes the unique MOTEL concept for use with various microprocessors, microcomputers, and larger computers. This part combines three unique features: a complete time-of-day clock with alarm and one hundred year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low-power static RAM. The MC146818A uses high-speed CMOS technology to interface with 1 MHz processor buses, while consuming very little power. The Real-Time Clock plus RAM has two distinct uses. First, it is designed as a battery powered CMOS part (in an otherwise NMOS/TTL system) including all the common battery backed-up functions such as RAM, time, and calendar. Secondly, the MC146818A maybe used with a CMOS microprocessor to relieve the software of the timekeeping ,~~ workload and to extend the available RAM of an MPU such as the ., ~:$ ,!!:\; .\,i,... , MC146805E2. ...\}t .. ,.,.>*t!F\+ {k ~ q Low-Power, High-Speed CMOS ,1, $s,,.. ~;, ~p )>.~$$~. q Internal Time Base and Oscillator ,& Q.%~!* *>sq,.,,\ ,$4:*, $+.~:;;, . ..~. O Counts Seconds, Minutes, and Hours of the Day t:>?,. q Counts Days of the Week, Date, Month, and Year ,$: ;<4 , ..!*:,: . q 3 V to 6 V Operation ~t.k ,$,., q Time Base Input Options: 4.194304 MHz, 1.048ti ,)$ ~~z, or 32.7W ,,,,,M,f, , ...*<.*$, ,$\<..%.kHz ,,:,, .\., ..i,;t~ q Time Base Oscillator for Parallel Resonan~$$~{S]s .~;\l.. .
q 40 to 200 pW Typical Operating Power{,~L:~#~ Frequency Time Base q 4.0 to 20 mW Typical Operating Po.~%j~*$?gh q Binary or BCD Representation q 12- or 24-Hour Clock with ,$$,> ..?.l A~$oQ$PM :,., ,{+<, .$k, q Daylight

Frequency Time Base ,~$.~,,, ~fTW~ Calendar, and Alarm in 12-Hour Mode

CASE 623

Savings Time OplWn $ *;* $*,,$$ q Automatic End of Mo~:~~$e6gnition q Automatic Leap Y~r ~&&~ensation ~ *$ .$$ q Selectable Ba$W&nWotorola and Competitor Bus Timing , -~.,y, }$~* q Multiplex@:~@ fbr Pin Efficiency ~.,-,, q lnterfq&$&%@% Software as 64 RAM Locations
q 14 B~es:$~CIOck ,,*J q Microprocessor#$@t@mpatible

PIN ASSIGNMENT

oT
Oscl
0SC2

~vDD [
2 [ 3

23 ] SQW 22 ] Ps 21 JCKOUT 20 ] CKFS lg ] l~Q 18 ] RESET 17 ] DS 16 ] STBY 15 ] Rl~ 14 ] AS 13 ]=

and Control Registers

q ~~~~~$iof General Purpose RAM .. ~. . @x;.$J&%ws indicates Data Integrity Bit

ADO [ 4 AD1 [ 5 AD2 [ 6 AD3 [ 7 AD4 [ 8 AD5 c g

?{&us Compatible Interrupt Signals (~Q) .. q Three Interrupts are Separately Software Maskable and Testable Time-of-Day Alarm, Once-per-Second to Once-per-Day Periodic Rates from 30.5 ps to 500 ms End-of-Clock Update Cycle Square-Wave Output Signal q Clock Output May Be Used as Microprocessor At Time Base Frequency -1 or +4
q 24-Pin Dual-In-Line q Quad Pack Also q Programmable

Clock Input

AD6 [ 10 AD7 [ 11 Vss [ 12

Package

Available

. hls document contains !ntormatlon on a new product. Specltlcatlons and tntormatlon here!n are subject to change without notice

)MOTOROLAINC,,

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ADI-1026

FIGURE

BLOCK

DIAGRAM

+ Clock output ~ ~ CKOUT CKFS

sow

~Q
RESET Ps

User RAM (50 Bytes)

,i,>,~ . ~><., ~:*.,*.*$:, \ h .

. .. ?+ $.;).,,<,:?

,<;}.: -

MAXIMUM

RATINQ~~(@oJjages R~$n& ~:?

referenced

to VSS) Value 0.3 to +8.0 Unit

Symbol VDD

Supply

Volta~J**

$?

v
v mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS =(Vin or Voutl s VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e. g., either VSS or VDD).

All Input V:$~&.~xcept

OSC1

Vin I

V5S O.5 to VDD+O.5 10 TL to TH 0 to 70 40 to 85 55to +150

Current ~rai~~r Pin Excluding Vmi,a%q,.vs s Op&~~~&Temperature ~%$~6818A <@c146818AC Storage Temperature Range Range

TA Tstg

Oc

Oc

THERMAL

CHARACTERISTICS Characteristic Symbol I Value Unit

Thermal Resistance Plastic Cerdlp Ceramic

I
9JA

I 120I
65 50

c/w

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)C ELECTRICAL CHARACTERISTICS
Frequency of Operation Output Voltage lLoad< lOpA

(vD D = 3 Vdc, vs s = O Vdc, TA = Tl to TH unless otherwise noted)

I Symbol I fosc vOL vOH V; CL (OSC2)= 10 pF IDD3 IDD4 50 Min 32.768 VDD O.1 I Max 32.768 0.1 I Unit kHz v I

Characteristics

IDD Bus Idle CKOUT=fosc, CL= 15 pF; SOW Disabled, STBY=O.2 fosc=32.76B kHz IDD Quiescent fosc= DC; OSC1 = DC; All Other lnpUtS=vDD0.2 NO Clock

.\, A&fi%$k ~ {?. 50 $:#$, !, :,.: ~~.+ i: ,.~ ,,~ ~+ ,.... , . .:s. i,,.. .. ..,t>.$. :.*$ \k;~# ~, \ . ..,. )$ it *.,+ ..% ~-.>,,->, ,.,/, t +?+~t;;k~ v <t \k*t ?J ~tl,

V;

Output High Voltege (l Load= 0.25 mA, All Outputs) Output Low Voltage (i Load= 0.25 mA, All Input High Voltage
OUtpUtS)

vOH
VOL

2.7

Input Low Voltage Input Current Three-State Leakage

~,

, %&$$y vlH STBY, ADO-AD7, DS, AS, R/W, CS .,$,@,q., RESET, CKFS, PS, OSC1 $:?y$: ~ ~?:, ,,. k$,w.~D MOT vlL ?$yvss ADO-AD7, DS, AS, R/W, CS, CKFS, PS, RESET, OSCI Vss MOT .#vj AS, DS, R/~F ~~:$~ MOT, OSCI, CE, STBY, RESET, CKFS, ,P# $ IRQ, AD@@fl~lTsL

,,} $i.,,,, -$.*;,,:,: ~

0.3
VDD VDD VDD

v
v

0.5
Vss * 10 *I * 10

v
PA WA

Input Current Three-State Leakage

.::.

AS, DS, R/~ MOT, OSCI, CE, STBY, RESET, CKFS, PS

1

Iin ITSL

I
1

I
,

+10 *1
I

AA PA

I
1

IRQ, ADO-AD7

*IO

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BUS TIMING VDD=5.O V *lo% 1 TTL and 130 pF Load Min 953 300 325

Ident. Number 1 2 3 4 8 13 14 15 18 21 24
25 26 27 28

Vnn=3.O V ti;F Load Characteristi~ Cycle Time Pulse Width, Pulse Width, DS/E Low or ~D/WR High DS/E High or RD/WR Low Symbol tcvc PWEL PWEH
tr, tf

Min 5000 lm 15m

Max
100

Max dc 30

Unit ns ns
ns ns ns ~$

Input Rise and Fall Time

R/~

Hold Time Setup Time Before DS/E or ~D

tRWH tRWS tcs tCH tDHR

tnu\A/ Fall I tASL tAHL Rise tASD pwAs Rise tASED H

10 2m 200 10 10
100 2~ 100 m 6~ 500 I

Im

10 80 25 o 10 o

R/~

Chip Select Setup Time Before DS, ~R, Chip Select Hold Time Read Data Hold Time Write Data Hold Time
Muxed I Muxed Address Address Valid Time to AS/ALE Hold Time to AS/ALE High to DS/E

,:,,, *.#*..,...,:{ ~s %+.< .$.. ,,. ~: m ~~ ~;~e.: ,,~r$

50 ,~p+:;a
w ~*.~y>>, .. ..s.. t .

n: SI ns ns ns ns ns

DelaV Time DS/E Pulse Width, DelaV Time,

AS/ALE AS/ALE

, * *,i$ ;~J$$95 * %:.\tf.,:/?@ ax.. ,.!>.

30 31 32 33
NOTE:

Peripheral Output Data Delay Time from DS/ E or ~ Peripheral Data Setup Time S~ S~ Setup Time before AS/ALE Hold Time after AS/ALE
E, ALE, ~, NOTICES and ~R appearing

tDDR tDSW tSBS tSBH

1300

., .,.,.? ~ ~... ,!..~, ~ .?.?~i~,. ~, :,

20 2m TBD TBD

240

Rise

1q$.ii ~. ~ ~Q:@:J~$+3 $~B~~ ~

.,...... Mp;cessor ~+.k .

ns

Fall

_
signals.

Designations

refer to signals from alternative on page 20 of this data :~~t, .,

* Refer to IMPORTANT

-.

Note:

VHIGH=VDD2.O

VHIGH=2.O

V, VLOW=O.8 V, for VDD=5.O V +IOYO for outputs only. V for outputs onlv. V, VLOW=O.5 V, for VDD=3.O

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FIGURE 3 BUS READ TIMING

COMPETITOR

MULTIPLEXED

BUS

LE(AddressLatch
~ (Read Output Enable)
(DS Pin)

I
C= (Chip Select)

IL

STBY

ADO-AD7 (Address/ Data Bus)

FIGURE 4 BUS WRITE TIMINti?@PETITOR

MULTIPLEXED

BUS

ADO-AD7 (Address/ Data Bus)

@-

*W
Address

25 J

31
Write Data

<;
Note: VHIGH=VDD-2.O VHIGH=2.O V, VLOW=O.8 V, for VDD=5.O

Valid only.

Valld

V A 10% for outputs only.

V, VLOW=O.5

V, for VDD=3.O

V for outputs

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TABLE 1 SWITCHING

CHARACTERISTICS

(VSS=O

Vdc, TA= TL to TH)

-.
VDD=3.O I
I Oscillator Startu~

Vdc I Unit I

VDD = 5.0 Vdc & 10A Min 51 51 C I I Max I Unit

Description

I Symbol I
ltRrl

Min TBD TBD TDn

Max

1Reset Pulse Width

Reset Delay Time D, ,1-DA,.,-. C---!AI; A+L

I tRWL tRLH I +-, .,,

[ I

lTBDlms] I I I I I

ll~lmsl KS ps ..I I

I
I

ps
&s i\!

DS

RESET

.
ITQ

VDD

2k

(KQ OnIV)

L MM D7000 or Equivalent

130pF

.
All Outputs Except OSC2 (See Figure 10)

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FIGURE 7 POWER-UP

VDD Pin ~~

Ov

RESET Pin

CKOUT Pin

VDD Pin

Ov

PS Pin .

The VRT bit is set to a ,1, by reading Register d. The VRT bit mn only be cleared by pulling the PS pin low (see REGISTER D ($OD)).

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SIGNAL DESCRIPTIONS
The block diagram in Figure 1, shows the pin connection with the major internal functions of the MC146818A RealTime Clock plus RAM. The following paragraphs describe the function of each pin. VDD, VSS DC power is provided to the part on these two pins, VDD being the more positive voltage. The minimum and maximum voltages are listed in the Electrical Characteristics tables. MOTMOTEL The MOT pin offers flexibility when choosing bus type, When tied to VDD, Motorola timing is used. When tied to VSS, competitor timing is used. The MOT pin must be hardwired to the VDD or VSS supply and cannot be switched during operation of the MC146818A.

ADO-AD7 MULTIPLEXED ADDRESSIDATA BUS

BIDIRECTIONAL

Multiplexed bus processors save pins by presenting the address during the first portion of the bus cycle and using the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time of the MC146818A since the bus reversal from address to data is \\;~,;. occurring during the internal RAM access time. >.t,, ,..,$) .... . The address must be valid just prior to the fall ,@#~$~~LE at which time the M C146818A latches the addr.e~ ??@ ADO to AD5, Valid write data must be presente@t~~~~fi8?d stable during the latter portion of the DS or ~~~~?~~. In a read cycle, the M C146818A outputs eight ~[~bf~~ta during the latter portion of the DS or ~ pulse~$~$~mases driving the bus (returns the output drivers to t~,h,$h-impedance state) when DS falls in the Motorola&cJ&e o~~OTEL or R~ rises in the other case.

..,~t;~,
.?)?

OSC1, OSC2 TIME BASE, INPUTS

The time base for the time functions may be an external signal or the crystal oscillator. External square waves at 4.184304 MHz, 1.M576 MHz, or 32.768 kHz may be connected to OSCI as shown in Figure 9. The internal time-base frequency to be used is chosen in Register A. The on-chip oscillator is designed for a parallel resonant AT cut crystal at4.1 M04 MHz, 1.048576 MHz or32.768 kHz frequencies. The crystal connections are shown in Figure 10 and the crystal characteristics in Figure 11. CKOUT CLOCK OUT, OUTPUT The CKOUT pin is an output at the time-base freque~~ divided by 1 or 4. A major use for CKOUT is as the t~u~:t, clock to the microprocessor; thereby saving the c,@$:&::@ second crystal. The frequency of CKOUT depends%~okt$he

AS MULTIPLEX~:~@#~SS STROBE, INPUT +,tp:=,y,t\> A positive goin~+ mu~~[pjexed address strobe pulse serves to demultiplex t~~x,~~s. The falling edge of AS or ALE causes the address+~:$~~atched within the MC146818A.
,!:!~ ,$$v<,,:hi:.

.,

DS ~ #&$AsTROBE

OR READ, INPUT

+ ..j:..k~
CKFS CLOCK OUT FREQUENCY #%&<$: INPUT When the CKFS pin is tied to VD~$~$:jcai~es CKOUT to be the same frequency as the time b~e ~~fie OSCI pin. When CKFS is tied to Vss, CKOUJ:~~l~@~OSCl time-base frequency divided by four. T~le~~ summarizes the effect

~~,DS pin has two interpretations via the MOTEL circuit, ,:&$$n@manating from a Motorola type processor, DS is a .,,,%~o$$lve pulse during the latter portion of the bus cycle, and !,,, *~~&$ariously called DS (data strobe), E (enable), and 42 (42 . ..-,:::.J+>,<T, ,. *a:J clock). During read cycles, DS signifies the time that the ~\33, RTC is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the Real-Time Clock plus RAM to latch the written data, The second MOTEL interpretation of DS is that of ~, MEM R, or ~ emanating from the competitor type processor. In this case, DS identifies the time period when the real-time clock plus RAM drives the bus with read data. This interpretation of DS is also the same as an output-enable signal on a typical memory.

R/~

READ/WRITE,

INPUT

, ,,: ., ,
~me Base,,~~~ ~=~k Frequency (oscl~, ;$t~,; + Select Hn Freq~ ~,,,,, (CKFS)
4.W: 4.ly3~,,Myz ,.,..r M HZ MHZ M HZ High Low High Low High Low

Clock Frequency Output Hn (CKOUT) 4.1943W MHz

1.W576 1.W576 MHz MHz

~$+&6 :\:~576

262.144 kHz 32.768 kHz 8.192 kHz

The MOTEL circuit treats the R/~ pin in one of two ways. When a Motorola type processor is connected, R/~ is a level which indicates whether the current cycle is a read or write. A read cycle is indicated with a high level on R/~ while DS is high, whereas a write cycle is a Iowon R/~ during DS. The second interpretation of R/~ is as a negative write pulse, ~R, MEMW, and l/OW from competitor tv~e ~rocessors, The MOTEL circuit in t~s mode gives R/~pin the same meaning as the write (W) pulse on many generic RAMs. ~S CHIP SELECT, INPUT The chip-select (C~) signal must be asserted (low) for a bus cycle in which the MC146818A is to be accessed. C= is not latched and must be stable during DS and AS (Motorola case of MOTEL) and during ~D and ~R. Bus cycles which take place without asserting C= cause no actions to take place within the MC146818A. When C% is not used, it should be grounded. (See Figure 20).

32.768 kHz 32.7& kHz

SQW SQUARE WAVE, OUTPUT The SQW Din can output a signal from one of the 15 taps provided by ihe 22 internal-divid~r stages. The frequency of the SQW may be altered by programming Register A, as shown in Table 5. The SQW signal may be turned on and off using the SQWE bit in Register B.

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FIGURE 9 EXTERNAL TIME-BASE

CONNECTION

4.1%304 MHz or 1.W576 MHz 32.7:; kHz

$
I I

VDD

Optional VI 2

(VDD1.O

Oscl
3 (Open)< OSC2

L
OSC2 MC146818A

MC146818A

,.. ,!~.-

fow RS (Maximum) CO (Maximum) cl Q Cin/Cout R Rf

4.175 Q 7 pF

MHz

1.046576 MHz 700 n 5 pF 0.~8 pF 35 k 15-40 pF 10 M

32.7@ kHz Wk 1.7 pF 0.~3 pF 30 k 10-22 pF 300-470 k 22 M

0.012 pF 50 k 15-30 pF 10 M

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~Q

INTERRUPT REQUEST, OUTPUT

The IRQ pin is an active low output of the MC14W18A that may be used as an interrupt input to a processor, The ~Q output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the 1~ pin, the processor program normally reads Register C. The RESET pin also clears pending interrupts. When no interrupt in the high-impedance may thus be connected processor. conditions are present, the ~Q level is state. Multiple interrupting devices to an ~Q bus with one pullup at the

FIGURE 12TYPICAL POWERUP DELAY CIRCUIT FOR RESET

DI

D2

RESET RESET, INPUT

The RESET pin does not affect the clock, calendar, or RAM functions. On powerup, the RESET pin must be held low for the specified time, tRLH, in order to allow the power supply to stabilize. Figure 12 shows a typical representation of the RESET pin circuit. When RESET is low the following occurs: a) Periodic Interrupt Enable (PIE) bit is cleared zero, b) Alarm c) Alarm Interrupt Interrupt Enable Enable (AIE) (AIE) bit is cleared bit is cleared to zero, to zero,
.. .,~!,:~,,+

to

d) Update ended Interrupt Flag (UF) bit is cleared to zero, e) Interrupt Request status Flag (IRQF) bit is cleared to zero, f) Periodic Interrupt Flag ( PF) bit is cleared to zero,

Not~~${,the ,~J,,,t dwe ~y 1~~

RTC is isolated from the MPU or M CU power by a drop, care must be taken to meet Vin requirements.

g) The part is not accessible. h) Alarm Interrupt Flag (AF) bit is cleared to zero, i) IRQ pin is in high-impedance state, and j) Square zero, Wave output Enable (SQWE) bit is cleared JQ

,,f:~
FIGURE 13 TYPICAL POWERUP DELAY CIRCUIT FOR POWER SENSE

STBY STAND
The STBY pin, MC146818A making Stand-by operation

BY

~l~\ tFi>\t:;*g*\\$ .,. ~+! ,,,:*.LF, ,, .,,,.$

...

when active, prevents ac~s~$~ it ideal for battery back-~~~~l~ations. incorporates (TD a transpa~~$$~~$tch,

the DI After D2

data strobe (DS) goes low recognized as a valid signal. The STBY signal is totally latch is opened by the falling

or .:>.$,:< _j:rn@), STBY is J*! N $$3, asyR*L@6s. Its transpare~t e~~~.of .@S (rising edge of RD ~.$,*,% 2$\$-

I
VDD 2.0 k

or ~R) and clocked by the r$@n@~dge of AS (ALE). Therefore, for STBY to be reco$oize@t@S and AS should occur in pairs. When STBY gop@~l,W,,before the falling edge of DS at (rising edge of ~R ?r ~~k$~re current cycle is completed that edge and thq \ $h<,~ycle will not be executsd. ~.. .!,...
S*, \~*~>

Ps MC146818

+
Vss

PS POW,~:J~~$E,

INPUT

0.005 ~F

The pQ,v&-s~$se pin is used in the control of the valid RAM @~~~$ (VRT) bit in Register D. When the PS pin is low ~@q,w~~T bit is cleared to zero. W~@Using the VRT feature during powerup, the PS pin must % externally held low for the specified tpLH time. As power is applied, the VRT bit remains low indicating that the contents of the RAM, time registers, and calendar are not guaranteed. PS must go high after powerup to allow the VRT bit to be set by a read of register D,

DI = M BD701 (Schottky) or Equivalent D2 = 1N4148 or Equivalent

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POWER-DOWN

CONSIDERATIONS
Before Register updates initializing the internal registers, the SET bit in B should be set to a 1 to prevent time/calendar from occurring. The program initializes the 10 loca-

In most systems, the MC146818A must continue to keep time when system power is removed. In such systems, a conversion from system power to an alternate power supply, usually a battery, must be made. During the transition from system to battery power, the designer of a battery backed-up RTC system must protect data integrity, minimize power consumption, and ensure hardware reliability. The stand-by (STBY) pin controls all bus inputs (R/~, DS, AS, ADO-AD7) ST BY, when negated, disallows any unintended also reduces modification power of the RTC data by the bus. by reducing reduced STBY of consumption the number

tions in the selected format (binary or BCD), then indicates the format in the data mode (DM) bit of Register B. All 10 time, calendar, and alarm bytes must use the same data mode, either binary or BCD. The SET bit may now be c~red to allow updates. Once initialized the real-time clocRMkes all updates in the selected data mode. The data ~~~a,~%nnot be changed without reinitializing the 10 data ,&~<~~~$t* Table 3 shows the binary and BCD form~&Q{t~e 10 time, calendar, and alarm locations. The 24/:~9 ~~~,1~ Register B establishes whether the hour locatio+n$f#p[&sent l-to-12 or O-to-23. The 24/12 bit cannot be c~;fi~&~r%ithout reinitializing the hour locations. When th+ l~~~~r format is selected the high-order a l. The time, bit of the hoursh~& ..l,>.<., represents PM when it is J~. .:i\\y+. :\\ .;. ..<,), .,+*,. calendar, ~@ ~~~rm bytes are not always Once per second the logic to be advanced by

transitions seen internally. Power consumption may be further resistive and capacitive loads from pin and the squarewave During and after the maximum specification (SQW) pin. power source must never

by removing out (CKOUT) the VIN Failure to

the clock

conversion,

be exceeded.

meet the VIN maximum specification can cause a virtual SCR to appear which may result in excessive current drain and destruction of the part.

accessible by the proce~?i:,@;ogram. ,.::, \., ...., , 10 bytes are switched ~,~b update

ADDRESS
Figure 14 shows the address

MAP
The

map of the MC146818A,

one second and te<~ec~for an alarm condition. If any of the 10 bytes are,~&#@$?This time, the data outputs are undefined. The u~~a~ ~~ckout time is 248ys at the 4.19W04 MHz and 1.O@fiMMz time Qas&fl~he time bases and 1948 ps for the 32.768 kHz Update Cycle section shows how to accomcycle bytes in the processor program. may be used in two ways. First,

memory consists of 50 general purpose RAM bytes, 10 RAM bytes which normally contain the time, calendar, and alarm data, and four control and status bytes, All 64 bytes directly readable and writable by the processor program are ex-

mo,&e the update ,,$~t~~e%~hree alarm

cept for the following: 1) Registers C and D are read only, 2) bit 7 of Register A is read only, and 3) the high-order bit of the seconds and status byte is read only. The contents of four control registers (A, B, C, and D) are described in .Fi.. ,~.. ,.,., REGISTERS. ~ ~:, .:$.., %<. ,+ ....t)\..).$<l>\b TIME, CALENDAR, AND ALARM LOCATIONS >..!l;:!,,t, .,..... The processor program obtains mation by reading the appropriate may initialize the time, calendar, these and decimal RAM alarm locations. bytes The contents be either may time and calw~~~r ~tiYorlocations. ~~f~~gram >.*. J. and ala~,$~p$i~rltlng to of th.$,~@&~~, calendar, ~ bi.~r~.,~~ binarv-coded

,%,~p~$ the Program inserts an alarm time in the appropriate ,~$~$~pbrs, minutes, and seconds alarm locations, the alarm in:,$~fbrrupt is initiated at the specified time each day if the alarm enable bit is high. The second usage is to insert a dont *J~ care care state code in one or more of three alarm bytes. The dont is any hexadecimal byte from CO to FF. That is,

the two most-significant bits of each byte, when set to l, create a dont care situation. An alarm interrupt each hour is created with a dont care code in the hours alarm location. Similarly, an alarm is generated every minute with dont care codes in the hours and minutes alarm bytes. The dont care codes in all three alarm bytes create an interrupt every second. MAP

(BCD).

FIGURE 14 ADDRESS o

00

01
1

Seconds
Seconds Alarm

100) 01 I

13

OD

Binary or BCC Contents

50
Bvtes
1 I 4 I

User
RAM

10

Register

I OA

63

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TABLE 3 TIME, CALENDAR,

Address Location Decimal Range o-59

AND

ALARM

DATA

MODES

.Function Seconds Range Binary Data Mode $W-S3B BCD Data Mode $W-$59 Example Bina~ Data Mode 15 BCD Data Mode 21

o
1

Seconds Alarm Minutes Minutes Alarm Hours (12 Hour Mode)

o-59 o-59 o-59 1-12 O-23 1-12 O-23

$00-$3B $W-$3B $W-$3B $01-$OC (AM) and $81-$8C ( PM) $CO-$17 $01-$OC (AM) and $81-$8C (PM) $W-$17

$W-$59 $W-$59 $m-$59 $01-$12 (AM) and

15 3A 3A

21 56 56 .!,. A),,),, l.~:~ ,,.l.,.,$.. :.*L~\,\. t,., ,1. ~ ., ~ *:~\ ,:::~ ,<$,+ ,,,:s ~

2 3

$81-$92 (PM)
$W-$23 $01-$12 (AMI and $81-$92 (PM) $~-23

05 05
05

Hours (24 Hour Mode) Hours Alarm (12 Hour Mode) Hours Alarm (24 Hour Mode)

.,,1,,,t,,,8t:i.,.. IS,. ~ .y ~,z ~,~m,., ~ .),,.: ,,, ~...V , %$ ,?@:$, . .. ,>., ! 05

,:ft<+;:t~ ,.\\. %,...!:

05 ~$+j >,, 05
,. $~?.. <i,)

6 7 8 9

Dav of the Week

Sunday= 1 Date of the Month Month Year

1-7 1-31 1-12 o-99

$01-$07 $01-$1F $01-$oc $00-$63

!t. t$:i;~:;,, $01-$07 <f@ ~\..+:t .,jh ,.*, ., $01-$31 $ :&*$@$ $01-$12,<P,$ t 02 $m-$~+:$~Q )$; J* *
Y*<

05 15 02 79

4F

STATIC CMOS RAM The % general purpose RAM bytes are not dedicated within the MC140818A. They can be used by the processor program, and are fully available during the update cycle. When time and calendar information must use battery back-up, very frequently there is other non-volatile data that must be retained when main power is removed. The W u~~,,: RAM bytes serve the need for low-power CMOS bat~y-<~ backed storage, and extend the RAM available $&&@

M C148818AS may be included in th~$~~~~~. The time/calendar functions may be disabl~~ ~:b~lding the DvO-DV2 dividers, in Register A, in th~~~es$.~hte by settin9 the SET bit in Register B or by re~ovag the oscillator. Holding the dividers in reset preve.~&~~&#~upts or SQW output from operating while set~&~}~&rS ET bit allows these functions to occur. With the &~id~s clear, the available user RAM is extended to 59+b~teS~he high-order bit of the seconds byte, bit 7 of @~~fS~~ A, and all bits of Registers C and D cannot effecl~~~~ be used as general purpose RAM. e. ~..h ., t.$.:. .!,;it, ,,, ;&:~JN~ERRUPTS The RTC @wsJ%,@~ includes three separate fully automatic sources of {~te~pts to the processor. The alarm interrupt may be@r~r%timed to occur at rates from once-per-second to q~~~@aY The periodic interrupt may be selected for rate~;<(~~ half-a-second to 30.517 ps. The update-ended interru@f may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt conditions are described in greater detail in other sections. The processor program selects which interrupts, if any, it wishes to receive. Three bits in Register B enable the three
interrupts. Writing a 1 to a interrupt-enable bit permits that interrupt to be initiated when the event occurs. A U in

the interrupt-enable bit prohibits the IRQ pin from being asserted due to the interrupt cause.

If ~~ intertupt flag is already set when the interrupt be&%:j.enabled, the ~ pin is immediately activated, ,,tq~u$ the interrupt initiating the event may have occurred .<,x,,~w{ earlier. Thus, there are cases where the program a,f~~uld clear such earlier initiated interrupts before first ,i~y bnabling new interrupts. When an interrupt event occurs, a flag bit is set to a l in Register C. Each of the three interrupt sources have separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bit may be used with or without enabling the corresponding enable bits. In the software scanned case, the program does not enable the interrupt. The interrupt flag bit becomes a status bit, which the software interrogates, when it wishes. When the software detects that the flag is set, it is an indication to software that the interruptevent occurred since the bit was last read. However, there is one precaution. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included with Register C so the bits which are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts (on any bits) are held after the read cycle. One, two or three flag bits may be found to be set when Register C is used. The program should inspect ail utilized flag bits every time Register C is read to insure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt-flag bit is set and the corresponding interrupt-enable bit is also set, the ~Q pin is asserted low. ~Q is asserted as long as at least one of the three interrupt sources has its flag and enables bits both set. The IRQF bit in Register C is a l whenever the ~Q pin is being driven low. The processor program can determine that the RTC initiated the interrupt by reading Register C. A l in bit 7

...

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(IRQF bit) indicates that one or more interrupts have been initiated by the part. The act of reading Register C clears all the then-active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual flag bits in the same byte which have the corresponding interrupt-mask bits set and service each interrupt which is set. Again, more than one interrupt-flag bit may be set. DIVIDER STAGES

operating time base, the first update cycle is one-half second later. The divider-control bits are also used to facilitate testing the MC146818A. SQUARE-WAVE OUTPUT SELECTION

The MC146818A has 22 binary-divider stages following the time base as shown in Figure 1. The output of the dividers is a 1 Hz signal to the update-cycle logic. The divers are controlled by three divider bus (DV2, DVI, and DVO) in Register A. DIVIDER CONTROL The divider-control bits have three uses, as shown in Table 4. Three usable operating time bases may be selected (4.184304 MHz, 1.048576 MHz, or 32.768 kHz). The divider
chain may be held at reset, which allows precision setting of

Fifteen of the 22 divider taps are made available to a 1-of-1 5 selector as shown in Figure 1. The first purpose of selecting a divider tap is to generate a square-wave output signal at the SQW pin. The RSO-RS3 bits in Register A establish the square-wave frequency as listed in Table 5. The SQW frequency selection shares the 1-of-15 selector,$~ith ,~) ~~..,....... periodic interrupts. ~~... :/, ~,?. ,:?,,, ,,,,,, Once the frequency is selected, the output of th:~~~~ pin may be turned on and off under program coq:g~{,~tih the square-wave output selection bits, or the&~,~~~outputenable bit may generate an asymmetric m~~form at the time of execution. The square-wave out~@~J~has a number ,../& i,;...<** > of potential uses. For example, it ~~ ~+m as a frequency standard for external use, a freqyen~$~?nthesizer, or could be used to generate one or m%,&~,dlo tones under Pro9ram

!,

,\.

TABLE

PE~~Q&~,)~TERRUPT $s<., l: ,,r.\\e: ,$h,y,:~~...4.1=

RATE AND

SQUARE MHz

WAVE

OUTPUT 32.768 Time

FREQUENCY kHz Base

or 1.046676 Tme Base SQW

,$~$~~~jits
$~ #~iater ,,8s3 ,.,. \*... ,> ~j$ *% 2 : A RS1 ; RSO ;

Periodic Interrupt Rate tpl 3;;,s

Periodic

outputInterrupt Rate
tpl

SQW

Output

Frequency None 32.768 kHz

Frequency None

None
3.90625

<..:., ..JX:{$:, .Ji+t,.,,> * .-.~,s;.:, !,.:. ,,.,. ..~.\\\, :.*

,:ti ~ $8, ~

J:{.*.., :\:\,. !\)>

ms

256

HZ

o o

0 0

1 1

0 1

61.035 PS

16.384 kHz 8.192 kHz 4.096 kHz 2.048 kHz 1.024 kHz 512 HZ 256 Hz 128 HZ
R4

7.8125 ms 122.070 ~S 244.141 flS W.281

128 HZ 8.192 kHz 4.@6 kHz 2.048 kHz

122.070 ~S
244.141 #S =.281

o
o

1
1
1

0
0
1 1

0
1
0

\, ,\. .... .. .
..$>,.. .

PS 976.562 US

PS

976.562 BS

1.024 kHz
512 HZ 256 HZ 128 HZ
64 Hz

0
1 1
1 1

1
0 0 0 0 1 1 1
1

1
0 1 0 1 0 1 0
1

1.953125 ms 3.90625 ms I 7.8125 m 1s I 1s 15.625 m 31,25 ms 62.5 ms

I 1.953125 ms
3.90625 ms 7,8125 ms

1 1 1
1

0 0 1 1 0 0 1
1

H7

15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms

32 HZ 16 HZ 8 Hz 4 Hz
1

32 HZ 16 HZ 8 HZ 4 Hz
1

125 ms
250 ms 500 ms

2 Hz

L&

2 Hz

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PERIODIC INTERRUPT SELECTION The periodic interrupt allows the ~ pin to be triggered from once every 5W ms to once every 30.517 ps. The periodic interrupt is separate from the alarm interrupt which may be output from once per second to once per day. Table 5 shows that the periodic interrupt rate is selected with the same Register A bits which select the square-wave frequency. Changing one also changes the other. But each function may be separately enabled so that a program could switch between the two features or use both. The SQW pin is enabled by the SQWE bit in Register B. Similarly the periodic interrupt is enabled by the PIE bit in Register B. Periodic interrupt is usable by practically all real-time systems. It can be used to scan for all forms of inputs from contact closures to serial recieve bits or bytes. It can be used in multiplexing displays or with software counters to measure inputs, create output intervals, or await the next needed software function.

complete, the output will be undefined. The update in progress (UIP) status bit is set during the interval. A program which randomly accesses the time and date information finds data unavailable statistically once every 4032 attempts. Three methods of accommodating nonavailability during update are usable by the program. In discussing the three methods, it is assumed that at random points user programs are able to call a subroutine to obtain the time o$$gay. The first method of avoiding the update cycle, ~~,~$%e update-ended interrupt. If enabled, an interrupt @~@kS*after every update cycle which indicates that oveb;~w,;.&s are available to read valid time and date inforrn~~&$Buring this time a display could be updated or the i~fqw$$bn could be transferred to continuously availablq,t.&~~$,*Before leaving the interrupt service routine, the ~~~~$ bit in Register C ,4 .$,.? ~,>$;: \.. should be cleared. The second method uses t$~wate-in-progress bit (U IP) in Register A to determin~;ti~~~%~update cycle is in progress or not. The UI P bit will ,~j%,,$hce per second. Statistically, the UIP bit will indiq$~;~~~t time and date information is $+ unavailable once ~,~ery~~~ attempts. After the UIP bit goes high, the updat~$~~~,begins 244 ps later. Therefore, if a low is read on th~~l~$it, the user has at least 2~ ws before the time/cale@& d~ta will be changed. If a l is read in the UIP bit, {~~@$fie/calendar data may not be valid. The user shou~,d avb$~ interrupt service routines that would cause the ti~)~tieded to read valid time/calendar data to exceed ,p%;>

UPDATE CYCLE

The MC14~18A executes an update cycle once per second, assuming one of the proper time bases is in place, the DVO-DV2 divider is not clear, and the SET bit in Register B is clear. The SET bit in the l state permits the program to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring. The primary function of the update cycle is to increment the seconds byte, check for overflow, increment the minutes byte when appropriate and so forth through to the year of <<,j~%$~#e third method uses a periodic interrupt to determine if the century byte. The update cycle also compares each %$s-J%update cycle is in progress. The UIP bit in Register A is set alarm byte with the corresponding time byte and issues an $high between the setting of the PF bit in Register C (see alarm if a match or if a dont care code (1IXXXXXX) is ,..:, ,. .! Figure 15), Periodic interrupts that occur at a rate of greater present in all three positions. ~:)::. than tBUC+tUC allow valid time and date information to be With a 4.19~ MHz or 1.048576 MHz time base thq$~~~+~$ read at each occurrence of the periodic interrupt. The reads date cycle takes 248 ps while a 32.708 kHz time base~,&*& ~~~ should be completed within (Tpl + 2) + tBUC to ensure that cycle takes 1984 ps. During the update cycle, the t~~~~endata is not read during the update cycle. dar, and alarm bytes are not accessible by the p~$~s~~ program. The MCI%818A protects the progra~>~~% reading transitional data. This protection is provid~>~~switch ing the time, calendar, and alarm portion,~~*~~# RAM off the microprocessor bus during the entir~ up~ate cycle. If the processor reads these RAM loca,@%&W~ore the update is (,.:, To properly setup the internal counters for daylight savings time operation, the user must set the time at least two seconds before the rollover will occur. Likewise, the time must be set at least two seconds before the end of the 29th or 30th day of the month.

tpl = Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62,5 ms, etc. per Table 5)
tuc = Update Cycle Time (2W ps or lW ps) tBUC = Delay Time Before Update Cycle (2M KS)

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REGISTERS
The M C146818A has four registers which are accessible to the processor program. The four registers arealsofullyaccessible during the update cycle. REGISTER A ($OA)
MSB b7 UIP b6 DV2 b5 DV1 b4 DVO b3 RS3 b2 RS2 bl RS1 LS B bO RSO Read/ Write Register except UIP

progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. SET is a read/write bit which is not modified by RESET or internal functions of the MC146818A. PIE The periodic interrupt enable (PIE) bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the l~pin to be driven low. A program writes a 1 to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3, RS2, RSI, and RSO bits in Register A, A zero in PIE blocks l~Q from being initiated by a periodic interrupt, but the periodic flag (P~) bit is still set at the periodic rate. PIE is not modified b~,a~&$~o-

UIP The update in progress (UIP) bit is a status flag that may be monitored by the program. When UIP is a l, the update cycle is in progress or will soon begin. When UIP is a U, the update cycle is not in progress and will not be for at least 244 ps (for all time bases). This is detailed in Table 6. The time, calendar, and alarm information in RAM is fully available to the program when the UIP bit is zero it is not in transition. The UIP bit is a read-only bit, and is not affected by Reset. Writing the SET bit in Register B to a l inhibits any update cycle and then clears the UIP status bit.
TABLE 6 UPDATE CYCLE TIMES UIP Bit

UIE The UIE (q~~~~~%%ded interrupt enable) bit is a read/write bit which e, ~7~s the updat%end flag (U F) bit in Register C to a@~,,lf % The RESET pin going low or the 4.lWW MHz Z@ ps 1 SET bit goin~~~~~c~ears the UIE bit. 1 1.046576 MHz Z& fls .4, :$, . 1 32.766 kHz lw~s SQW~;~~&&n the square-wave enable (SQWE) bit is set to a lk~~ the program, a square-wave signal at the freo 4.194304 MHz 244 fis qu~~y spefified in the rate selection bits (RS3 to RSO) apo 1.M576 MHz 244 ps W$S @ the SQW pin. When the SQWE bit is set to a zero 244 fis o 32.766 kHz ,,,,, @e~QW pin is held low. The state of SQWE is cleared by ~ ,,~,;~~~~k ESET pin. SQWE is a read/write bit. DV2, DVI, DVO Three bits are used to permit the Dro*$:=: ,.,:. +:,8 DM The data mode (DM ) bit indicates whether time gram to select various conditions of the 22-stage divider .1, ..,} and calendar updates are to use binary or BCD formats. The ? chain. The divider selection bits identify which of the thre:~ DM bit is written by the processor program and maybe read time-base frequencies is in use. Table 4 shows that tJ,ti&j2, by the program, but is not modified by any internal functions bases of 4.194304 MHz, 1.046576 MHz, and 32.7~ k~~)~~, or RESET. A l in DM signifies binary data, while a U in be used. The divider selection bits are also used to$,~j&~,J~& DM specifies binary-coded-decimal (BCD) data. divider chain. When the time/calendar is first ini~~t~~:~~the program may start the divider at the precise,~~$~&red in 24/12 The 24/12 control bit establishes the format of the RAM, When the divider reset is removed;~~~:~wt update the hours bytes as either the 24hour mode (a l) or the cycle begins one-half second later. Thes%.th~e read/write 12-hour mode (a U), This is a read/write bit, which is afbits are not affected by RESET. ~d: >~fected on Iy by software. ..

Time Base

Update Cycle ~me

(Oscl)

(tuc)

Minimum Time Before Update

Cycle (tBuC)

AIE The alarm interrupt enable (Al E) ~T$f&j&i$&ad/write bit which when set to a 1 permits the @~rfl~~& (AF) bit in Register C to assert IRQ. An alarm inte~~@\$occurs for each second that the three time bytes e~~~~~~&i?hree alarm bytes (including a dont care alarm &od&tQ~ binary 1IXXXXX). When the AIE bit is a U, the ~~~jt does not initiate an ~Q signal. The RESET pin cle~f~~s~~% V. The internal functions do not affect the ,~~,t~t~

;.i ,{.,!$.~..$.. .,.>*,,, * ~ ..:.,\~,

RS3, RS2, RS1, RSO The fo$~ ray selection bits select one of 15 tapes on the 22-sta~.~W~~&@P, disable the divider or output. The tap selected may ~.~hed to generate an output square wave (SQW pin) ~i~or &periodic interrupt. The program may do one of ~~~~wing: 1) enable the interrupt with. the PIE bit, ~~~~~le the SQW output pin with the SQWE bit, 3) en@~th at the same time at the same rate, or 4) enable n,g~w~~~able 5 lists the periodic interrupt rates and the sqq~re-.g%ve frequencies that may be chosen with the RS ~j~%h@e four bits are readlwrite bits which are not affecte,~Q~%ES ET. ,.,1, $,,,, ~ .)e~,{., REGl~Ei B ($OB)
MSB b71b61b51b41 SET b31b21bl LSB bO Read/ Write Register

DSE The daylight savings enable (DSE) bit is a readlwrite bit which allows the program to enable two special updates (when DSE is a 1). On the last Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a JO. DSE is not changed by any internal operations or reset. REGISTER C ($OC)
MSB b7/b61b51b4 IRQFIPFIAFIUFIOIO b3 b bl jOIO I LSB bO Read-Only Register

PIE I AIE ] UIEI SQWEI DM ] 24/12 I DSE

SET When the SET bit is a O, the update cycle functions normally by advancing the counts once-per-second. When the SET bit is written to a 1, any update cycle in

IRQF The interrupt request flag (IRQF) is set to a l when one or more of the following are true: PF=PIE=I AF=AIE=I UF=UIE=I i.e., IRQF= PF*PIE+ AF*AIE+UF*UIE

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Any time the IRQF bit is a l, All flag gram bits are cleared after or when

the 1~

pin is driven

low.

Register

C is read by the pro-

b6 TO bO The remaining bits of Register D are unused. They cannot be written, but are always read as OS. TYPICAL The MC146818A INTERFACING for use with microprocesmultiplexed bus. to bus-compatible that the if address standard

the RESET pin is low.

PF The periodic interrupt flag (PF) is a read-only bit which is set to a l when a particular edge is detected on the selected tap of the divider chain. The RS3 to RSO bits establish the periodic rate. PF is set to a l independent of the state of the PIE bit. PF being a l initiates an ~ signal and sets the IRQF bit when PIE is also a l. The PF bit is cleared by a RESET or a software read of Register C. AF A l in the AF (alarm interrupt flag) bit indicates

is best suited

sors which generate an address-then-data Figures 16 and 17 show typical interfaces processors. decoding metalgate violated. These can be interfaces done assume quickly.

However,

CMOS gates are used, the CS setup time may be Figure 18 illustrates an alternative method o?s:$hip

that the current time has matched the alarm time. A l in the AF causes the ~ pin to go low, and a l to appear in the IRQF bit, when the AIE bit also is a 1 . A RESET or a read of Register C clears AF. UF The update-ended interrupt flag (UF) bit is set after each update cycle. when the UIE bit is a l, the l in UF causes the IRQF bit to be a l, by a Register C read or a RESET. bits of Status Register 1 are read asserting 1~. UF is cleared

selection which will accommodate such slower dq~~~&! The MC146818A can be interfaced to single#[email protected] (MCU) by using eleven port lineS@~~,@Ubwn in Figure 19. Non-multiplexed bus micropro@~*&~an be in.*.$ {*({F terfaced with additional support. ,<,,:.@$s There is one method of usin~.+~~~~@ultiplexed bus MC146818A with non-multiplexed face uses available bus control *S ~pcessors. The inter~ign&#to multiplex the adM CWOO, MC6802, is shown in Figure 20.

b3 TO bO The unused as Os. REGISTER MSB b7 VRT VRT b6 b5 b4 They

dress and data bus togetherik~:~~~ An example using eitha~t~b:~~otorola MCW08, or MC6809 ~~a&$r,~essor

can not be written.

D ($OD) LSB b3 b2 bl bO Read Only Register the

When the MC14681~/&~,~mapped as shown in Figures 19 and 20, the AS and D\%,~inputs should be left in a low state when the part iqjf~}lbeing accessed. Refer to the _ description J@~l\~ conditions which must be met STBY ca~, ~~ r,~ognized, Figur~~:? fl!~ftrates entered with the subroutines the registers which system. containing maybe dat~jtrans%rs :h~u~.be ;&8f&; t: in a non-multiplexed pin before used for

0
The valid

0
RAM

0
(VRT)

and time

bit indicates

The subroutines the following

condition of the contents of the RAM, provided the power sense (PS) pin is satisfactorily connected. A O appears in the VRT bit when the power-sense program can set the VRT bit when pin is low. The processor the time and calendar are

initialized to indicate that the RAM and time are valid. The VRT is a read only bit which is not modified by the RES~T pin. The VRT bit can only be set by reading Register

$Q,f$:?@~&cumulator A: The address of the RTC to be accessed. ~~~~> Accumulator B: Write: The data to be written. ~~..~t Read: The data read from the RTC. .:!A l,The RTC is mapped to two consecutive memory locations RTC and RTC+ 1 as shown in Figure 20.

Q:~?~,, .,\, ~~:;,>,, .,

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FIGURE ~@~~:*l&18A INTERFACED WITH COM,,@~~J@& MULTIPLEXED BUS MICROPROCESSORS

*
H MC6801 MC146B05E2 w > Other Peripherals and Memorv

Address Decode* i CT I I I I RESET~ RESET ~Q

\ R/~ DS AS AD@AD7

q High-Speed

VDD CKOUT + 1

MC146818A CKFS STBY SQW

I
I L

SiliconGate CMOS or TTL Address Decoding _ __ ,

H @
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FIGURE 17 MC148818A INTERFACED WITH COMPETITOR COMPATIBLE MULTIPL~ED BUS MICROPROCESSORS

I
8085 8M 8049 4 8/4

8 Address/Data Address Latch Enable (ALE~ Read ~) Wri?e (=) Interrupt Request ~ e

8 / + + Other Periph~@ls andw~y

Address

Address Decode I m l~Q R/~ DS AS ~m~>

:(,,,

FIGURE 18 MC ~~8A INTERFACE WITH MC148805W CMOS MULTIPLEXED MICROP~@~,SOR WITH SLOW ADDRESSING

DECODING

M C14@05E2

@ti$~~?exed

Address/Data

Oscl I I
AS RESET MC146818A RIW IRQ ADO-AD7

VDD

I I
I
I

MOT CKOUT CKFS A STBY 4 SQW I

4. IW304 MHz (Typ)

This illustrates the use of CMOS gating for address decoding.

EI ~_______-----___2l I
v ~D

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FIGURE 19 MCl~18A INTERFACED WITH THE PORTS OF A TYPICAL SINGLE CHIP MICROCOMPUTER 4. 193W MHz (Tvp)

M C3870 M C6805 MC 146805 S2000 8021

I I I
L
* NOTE: C= can be controlled by a port pin (ifJav}#able). *. <$

AS

STBY

fl_
Power Failure Circuit

(See STBY Description)

DO-D7

~ADo-AD7
Vss

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FIGURE 21 SUBROUTINE FOR READING AND WRITING THE MCl@18A WITH A NON-MULTIPLIED BUS

READ

STA LDAB RTS STA STAB RTS

RTC RTC+ 1

WRITE

RTC RTC+ 1

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PACKAGE

DIMENSIONS

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to make of others.

changes Motorola

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to any products or circuit trademarks

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to improve herein;

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or design.

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or use of any product registered

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