PIC16F8X

9.0 INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the number of the file in which the bit is located. For literal and control operations, k represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: Byte-oriented operations Bit-oriented operations Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 9-2 lists the instructions recognized by the MPASM assembler. Figure 9-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.

PIC16F8X
TABLE 9-2
Mnemonic, Operands

PIC16FXX INSTRUCTION SET

Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS 14-Bit Opcode LSb Status Affected Notes

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f

1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z Z Z Z Z Z Z Z Z

1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

C C C,DC,Z Z

1,2 1,2 1,2 1,2 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3

TABLE 9-1
Field
f W b k x

OPCODE FIELD DESCRIPTIONS

Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label

All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.

LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z

FIGURE 9-1:

GENERAL FORMAT FOR INSTRUCTIONS

0

Dont care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Label name Top of Stack Program Counter Program Counter High Latch Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)

Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)

label TOS PC
PCLATH

TO,PD C,DC,Z Z

GIE WDT TO PD dest [ ]

When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

( ) <>

italics

k = 11-bit immediate value

1998 Microchip Technology Inc.

DS30430C-page 55 DS30430C-page 56 1998 Microchip Technology Inc.

PIC16F8X
9.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:

PIC16F8X
BCF Syntax: Operands: Operation: Status Affected: Bit Clear f [label] BCF 0 f 127 0b7 0 (f<b>) None
01 00bb bfff ffff Bit b in register f is cleared.

Instruction Descriptions
Add Literal and W [label] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk The contents of the W register are added to the eight bit literal k and the result is placed in the W register.

ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:

AND Literal with W [label] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk The contents of W register are ANDed with the eight bit literal 'k'. The result is placed in the W register.

BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:

Bit Test, Skip if Clear [label] BTFSC f,b 0 f 127 0b7 skip if (f<b>) = 0 None
01 10bb bfff ffff If bit b in register f is 1 then the next instruction is executed. If bit b, in register f, is 0 then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.

Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Cycles: Q2
Read literal k

1 1 Q1
Decode

Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write register f

Q3
Process data

Q4
Write to W

Q Cycle Activity:

Q2
Read literal "k"

Q3
Process data

Q4
Write to W

Words: Cycles: Q Cycle Activity:

1 1(2) Q1
Decode

Example:

ADDLW

0x15 W W = = 0x10 0x25

Example

ANDLW W W

0x5F = = 0xA3 0x03

Example

BCF

FLAG_REG, 7 FLAG_REG = 0xC7

Q2
Read register f

Q3
Process data

Q4
No-Operat ion

Before Instruction After Instruction

Before Instruction After Instruction

Before Instruction After Instruction

FLAG_REG = 0x47

If Skip:

(2nd Cycle) Q1 Q2
No-Operat ion

Q3

Q4

No-Operati No-Opera No-Operat on tion ion

ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:

Add W and f [label] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z
00 0111 dfff ffff Add the contents of the W register with register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f.

ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:

AND W with f [label] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z
00 0101 dfff ffff

f,d

Example

HERE FALSE TRUE

BTFSC GOTO PC =

FLAG,1 PROCESS_CODE

Before Instruction
address HERE

After Instruction BSF Syntax: Operands: Operation: Status Affected: Bit Set f [label] BSF 0 f 127 0b7 1 (f<b>) None
01 01bb bfff ffff Bit b in register f is set.

AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.

f,b

if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Cycles: Q2
Read register f

1 1 Q1
Decode

Q3
Process data

Q4
Write to destination

Q Cycle Activity:

Q2
Read register f

Q3
Process data

Q4
Write to destination

Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1

Example

ADDWF

FSR, 0 W = FSR = 0x17 0xC2 0xD9 0xC2

Example

ANDWF

FSR, 1 W = FSR = 0x17 0xC2 0x17 0x02

Before Instruction

Before Instruction

Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write register f

After Instruction
W = FSR =

After Instruction
W = FSR =

Example

BSF

FLAG_REG,

Before Instruction
FLAG_REG = 0x0A

After Instruction
FLAG_REG = 0x8A

1998 Microchip Technology Inc.

DS30430C-page 57

DS30430C-page 58

1998 Microchip Technology Inc.

PIC16F8X
BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [label] BTFSS f,b 0 f 127 0b<7 skip if (f<b>) = 1 None
01 11bb bfff ffff

PIC16F8X
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Clear f [label] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff The contents of register f are cleared and the Z bit is set.

CALL Syntax: Operands: Operation:

Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.

CLRW f Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles:

Clear W [ label ] CLRW None 00h (W) 1Z Z

00 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set.

Status Affected: Encoding: Description:

If bit b in register f is 0 then the next instruction is executed. If bit b is 1, then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.

1 1 Q1
Decode

1 1 Q1
Decode

Words: Cycles: Q Cycle Activity:

1 1(2) Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write register f

Q Cycle Activity:

Q2
No-Opera tion

Q3
Process data

Q4
Write to W

Words: Q2
Read register f

1 2 Q1
Decode

Q3
Process data

Q4
No-Operat ion

Cycles: Q Cycle Activity: 1st Cycle

Q2
Read literal k, Push PC to Stack

Q3
Process data

Q4
Write to PC

Example

CLRF

FLAG_REG FLAG_REG = = = 0x5A 0x00 1

Example

CLRW

If Skip:

(2nd Cycle) Q1 Q2

Q3

Q4 2nd Cycle

Before Instruction After Instruction

FLAG_REG Z

Before Instruction
W W Z = = = 0x5A 0x00 1

No-Operati No-Opera No-Operat No-Operat on tion ion ion

After Instruction

No-Opera No-Opera No-Operat tion tion ion No-Opera tion

Example

HERE FALSE TRUE

BTFSC GOTO PC =

FLAG,1 PROCESS_CODE

Example

HERE

CALL

THERE

CLRWDT Syntax: Operands: Operation:

Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.

Before Instruction
PC = Address HERE

After Instruction
address HERE PC = Address THERE TOS = Address HERE+1

Before Instruction After Instruction

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE

Status Affected: Encoding: Description:

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Q2
No-Opera tion

Q3
Process data

Q4
Clear WDT Counter

Example

CLRWDT

Before Instruction
WDT counter = ? 0x00 0 1 1

After Instruction
WDT counter = WDT prescaler= = TO = PD

1998 Microchip Technology Inc.

DS30430C-page 59

DS30430C-page 60

1998 Microchip Technology Inc.

PIC16F8X
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z
00 1001 dfff ffff

PIC16F8X
GOTO Syntax: Operands: Operation: Status Affected: Encoding: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.

DECFSZ f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:

Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None
00 1011 dfff ffff
The contents of register f are decremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.

INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:

Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z

00 1010 dfff ffff The contents of register f are incremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f.

The contents of register f are complemented. If d is 0 the result is stored in W. If d is 1 the result is stored back in register f.

Description:

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Cycles: Q Cycle Activity: 1st Cycle

1 2 Q1
Decode

Words: Cycles: Q2
Read literal k

1 1 Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write to destination

Words: Cycles: Q Cycle Activity:

1 1(2) Q1
Decode

Q3
Process data

Q4
Write to PC

Q Cycle Activity:

Q2
Read register f

Q3
Process data

Q4
Write to destination

Q2
Read register f

Q3
Process data

Q4
Write to destination

2nd Cycle

Example

COMF

REG1,0 REG1 = = = 0x13 0x13 0xEC

No-Operat ion

No-Operat No-Opera No-Operat ion tion ion

Example

INCF

CNT, 1 CNT Z = = = = 0xFF 0 0x00 1

Before Instruction After Instruction

REG1 W

If Skip:

(2nd Cycle) Q1 Q2
No-Operat ion

Before Instruction Example Q3 Q4

GOTO THERE

After Instruction
PC = Address THERE

No-Opera No-Operat No-Operati tion ion on

After Instruction
CNT Z

DECF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:

Decrement f [label] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z

00 0011 dfff ffff Decrement register f. If d is 0 the result is stored in the W register. If d is 1 the result is stored back in register f.

Example

HERE

DECFSZ GOTO CONTINUE

CNT, 1 LOOP

Before Instruction
PC =

address HERE CNT - 1 0, address CONTINUE 0, address HERE+1

After Instruction
CNT if CNT PC if CNT PC = = = =

1 1 Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write to destination

Example

DECF

CNT, 1 CNT Z = = = = 0x01 0 0x00 1

Before Instruction

After Instruction
CNT Z

1998 Microchip Technology Inc.

DS30430C-page 61

DS30430C-page 62

1998 Microchip Technology Inc.

PIC16F8X
INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None
00 1111 dfff ffff The contents of register f are incremented. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.

PIC16F8X
IORWF Syntax: Operands: Operation: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z
00 0100 dfff ffff Inclusive OR the W register with register f. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f.

IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:

Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z

11 1000 kkkk kkkk The contents of the W register is ORed with the eight bit literal 'k'. The result is placed in the W register.

MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:

Move Literal to W [ label ] k (W) None

11 00xx kkkk kkkk The eight bit literal k is loaded into W register. The dont cares will assemble as 0s.

MOVLW k

0 k 255

Status Affected: Encoding: Description:

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Q2
Read literal k

Q3
Process data

Q4
Write to W

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Q2
Read literal k

Q3
Process data

Q4
Write to W

Words: Cycles: Q Cycle Activity:

1 1(2) Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write to destination

Q2
Read register f

Q3
Process data

Q4
Write to destination

Example

IORLW W W Z

0x35 = = = 0x9A 0xBF 1

Before Instruction After Instruction Example

IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1

Example

MOVLW W

0x5A = 0x5A

After Instruction

If Skip:

(2nd Cycle) Q1 Q2

Before Instruction

Q3

Q4

No-Opera No-Opera No-Operati tion tion on No-Operat ion

After Instruction
RESULT = W = Z =

Example

HERE

INCFSZ GOTO CONTINUE

CNT, 1 LOOP

MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description:

Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z

00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.

MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity:

Move W to f [ label ] (W) (f) None

00 0000 1fff ffff Move data from W register to register 'f'.

Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1

MOVWF

0 f 127

After Instruction
CNT = if CNT= PC = if CNT PC =

1 1 Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write register f

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Q2
Read register f

Q3
Process data

Q4
Write to destination

Example

MOVWF

OPTION_REG OPTION = W = 0xFF 0x4F 0x4F 0x4F

Before Instruction

After Instruction Example

MOVF FSR, 0 W = value in FSR register Z =1

After Instruction

OPTION = W =

1998 Microchip Technology Inc.

DS30430C-page 63

DS30430C-page 64

1998 Microchip Technology Inc.

PIC16F8X
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: 1 1 Q1
Decode

PIC16F8X
RETLW Syntax: Operands: Operation: Status Affected: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None
11 01xx kkkk kkkk The W register is loaded with the eight bit literal k. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.

No Operation [ label ] None No operation None

00 0000 0xx0 0000

RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description:

Return from Interrupt [ label ] None TOS PC, 1 GIE None

00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction.

RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description:

Return from Subroutine [ label ] None TOS PC None

00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.

NOP

RETFIE

RETURN

No operation.

Encoding: Description:

Q2

Q3

Q4 Words:

Words: Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle

1 2 Q1
Decode

No-Opera No-Opera No-Operat tion tion ion

Words: Cycles: Q Cycle Activity:

1 2 Q1
Decode

1 2 Q1
Decode

Q2

Q3

Q4

Example

NOP

Cycles: Q Cycle Activity: 1st Cycle 2nd Cycle

Q2
Read literal k

Q3
No-Opera tion

Q4
Write to W, Pop from the Stack

No-Opera No-Opera Pop from tion tion the Stack No-Opera No-Opera No-Opera tion tion tion

Q2
No-Opera tion

Q3
Set the GIE bit

Q4
Pop from the Stack

1st Cycle

No-Operat ion

No-Operat ion

No-Opera No-Opera No-Operat tion tion ion

2nd Cycle

No-Operat ion

No-Opera No-Opera No-Operat tion tion ion

Example

RETURN

After Interrupt
PC = TOS
;W contains table ;offset value ;W now has table value

Example

RETFIE

After Interrupt
PC = GIE = TOS 1

Example

CALL TABLE

TABLE ADDWF PC RETLW k1 RETLW k2

OPTION Syntax: Operands: Operation: Encoding: Description:

Load Option Register [ label ] None (W) OPTION

00 0000 0110 0010

OPTION

;W = offset ;Begin table ;

RETLW kn ; End of table

Status Affected: None

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.

Before Instruction
W W = = 0x07 value of k8

After Instruction

Words: Cycles: Example

1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

1998 Microchip Technology Inc.

DS30430C-page 65

DS30430C-page 66

1998 Microchip Technology Inc.

PIC16F8X
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C
00 1101 dfff ffff The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is stored back in register f. C Register f

PIC16F8X
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011 The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.8 for more details.

RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:

Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0 the result is placed in the W register. If d is 1 the result is placed back in register f. C Register f

RLF

f,d

SUBLW SLEEP Syntax: Operands: Operation: Status Affected: Encoding: Description:

Subtract W from Literal [ label ] 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk
The W register is subtracted (2s complement method) from the eight bit literal 'k'. The result is placed in the W register.

SUBLW k

Status Affected: Encoding: Description:

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Q2
Read literal k

Q3
Process data

Q4
Write to W

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Cycles: Q2
Read register f

1 1 Q1
Decode

Q3
Process data

Q4
Write to destination

Q Cycle Activity:

Q2
Read register f

Q3
Process data

Q4
Write to destination

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Example 1: Q2 Q3 Q4
Go to Sleep

SUBLW Before Instruction

W C Z = = = 1 ? ?

0x02

Example

RLF

REG1,0 REG1 C

Example
1110 0110 0 1110 0110 1100 1100 1

RRF REG1 C

REG1,0

No-Opera No-Opera tion tion

Before Instruction
= = = = =

Before Instruction
= = = = = 1110 0110 0 1110 0110 0111 0011 0

After Instruction Example: SLEEP

W C Z = = = 1 1; result is positive 0

After Instruction
REG1 W C

After Instruction
REG1 W C

Example 2:

Before Instruction
W C Z = = = 2 ? ?

After Instruction
W C Z = = = 0 1; result is zero 1

Example 3:

Before Instruction
W C Z = = = 3 ? ?

After Instruction
W C Z = = = 0xFF 0; result is negative 0

1998 Microchip Technology Inc.

DS30430C-page 67

DS30430C-page 68

1998 Microchip Technology Inc.

PIC16F8X
SUBWF Syntax: Operands: Operation: Encoding: Description: Subtract W from f [ label ] 0 f 127 d [0,1] (f) - (W) (destination) 00 0010 dfff ffff SUBWF f,d SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None
00

PIC16F8X
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk
The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register.

XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:

Exclusive OR W with f [label] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z
00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.

Status Affected: C, DC, Z

Subtract (2s complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.

1110

dfff

ffff

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.

Words: Cycles: Q Cycle Activity:

1 1 Q1
Decode

Words: Q2
Read literal k

1 1 Q1
Decode

Words: Q2
Read register f

1 1 Q1
Decode

Q3
Process data

Q4
Write to destination

Cycles: Q Cycle Activity:

Q3
Process data

Q4
Write to W

Cycles: Q Cycle Activity:

Q2
Read register f

Q3
Process data

Q4
Write to destination

Q2
Read register f

Q3
Process data

Q4
Write to destination

Example 1:

Example:

XORLW Before Instruction

W =

0xAF Example
0xB5

SUBWF Before Instruction

REG1 W C Z = = = =

REG1,1 Example
3 2 ? ? SWAPF REG, 0

XORWF

REG

Before Instruction
REG1 = 0xA5

Before Instruction
REG W = = 0xAF 0xB5

After Instruction
W = 0x1A

After Instruction
REG1 W = = 0xA5 0x5A

After Instruction
REG W = = 0x1A 0xB5

After Instruction
REG1 W C Z = = = = 1 2 1; result is positive 0

Example 2:

Before Instruction
REG1 W C Z = = = = 2 2 ? ?

TRIS Syntax: Operands: Operation: Encoding: Description:

Load TRIS Register [label] 5f7 (W) TRIS register f;

00

TRIS

After Instruction
REG1 W C Z = = = = 0 2 1; result is zero 1

Status Affected: None 0000 0110 0fff

The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.

Example 3:

Before Instruction
REG1 W C Z = = = = 1 2 ? ?

Words: Cycles: Example

1 1
To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

After Instruction
REG1 W C Z = = = = 0xFF 2 0; result is negative 0

1998 Microchip Technology Inc.

DS30430C-page 69

DS30430C-page 70

1998 Microchip Technology Inc.