Scribd Logo
Upload

Welcome to Scribd!

  • 249 views

    VHDL Code Hamming PDF

    Uploaded by

    soodeh_aslani
    This document describes the TC3000 family of IP cores for implementing turbo product codes. The TC3000 cores can implement Hamming and double-error correcting BCH product codes with customizable bitrates from 7 to 25 Mbits/s. Using these turbo product codes provides an additional gain of 2 to 3 decibels over classical FEC solutions. The cores offer flexibility in configurable parameters and high FEC performance for various block sizes and coding rates.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    VHDL Code Hamming PDF

    Uploaded by

    soodeh_aslani
    249 views2 pages
    This document describes the TC3000 family of IP cores for implementing turbo product codes. The TC3000 cores can implement Hamming and double-error correcting BCH product codes with customizable bitrates from 7 to 25 Mbits/s. Using these turbo product codes provides an additional gain of 2 to 3 decibels over classical FEC solutions. The cores offer flexibility in configurable parameters and high FEC performance for various block sizes and coding rates.

    Original Title

    vhdl code hamming.pdf

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes the TC3000 family of IP cores for implementing turbo product codes. The TC3000 cores can implement Hamming and double-error correcting BCH product codes with customizable bitrates from 7 to 25 Mbits/s. Using these turbo product codes provides an additional gain of 2 to 3 decibels over classical FEC solutions. The cores offer flexibility in configurable parameters and high FEC performance for various block sizes and coding rates.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    249 views2 pages

    VHDL Code Hamming PDF

    Uploaded by

    soodeh_aslani
    This document describes the TC3000 family of IP cores for implementing turbo product codes. The TC3000 cores can implement Hamming and double-error correcting BCH product codes with customizable bitrates from 7 to 25 Mbits/s. Using these turbo product codes provides an additional gain of 2 to 3 decibels over classical FEC solutions. The cores offer flexibility in configurable parameters and high FEC performance for various block sizes and coding rates.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 2

    TurboConcept 1, av. du Technople 29280 PLOUZANE FRANCE phone : +33 2 29 00 19 88 fax : +33 2 29 00 18 03 www.turboconcept.

    com

    TC3000 Turbo Product Code decoders


    Introducing turbo product codes with BCH t=2 codes Customisable bitrate : 7 to 25 Mbits/s
    Turbo codes improves a transmission link by an additional gain of 2 to 3 decibels, compared to classical FEC solutions. TC3000 is a family of IP Cores offering powerful and flexible turbo product codes. TC3000 is the first IP Core implementing Hamming and double-error-correcting BCH product codes. A highly generic approach allows TC3000 to be precisely optimised for a target application.

    Features
    Very High FEC performance : Hamming and "BCH-t=2" codes Bitrate customisable : 7 to 25 Mbits/s typical @ 5 iterations Large block sizes : up to 65 kbits On-the-fly change of the code Shortening facilities to adjust packet size and coding rate Single-chip PLD IP Core : Altera APEX, no external memory required Latency reduction by bank-swapping Two selectable configuration interface

    Bitrate/Complexity trade-off
    bitrate @ 5iter. 25 Mbit/s

    TC3014

    TC3024

    14 Mbit/s

    TC3012

    TC3022

    7 Mbit/s TC3011TC3021 2k 5k 10k

    parity and hamming product codes parity, hamming and BCH t=2 product codes

    20k Logic Elements

    This document contains preliminary information. Information is subject to change without notice. TC3000 is covered by several patents.

    Flexibility
    TC3000 family offers 3 levels of flexibility : TC3000 family member VHDL generic parameters before synthesis On-the fly parameters from block to block

    9 9 9 9 9 9 9 9 9 9 9

    BCH t=2 code support (YES/NO) Choice on bitrate Maximum row code length Maximum column code length Input Quantization width 1 or 2 input buffers Row code Column code Shortening values Max. number of iterations Stopping feature enabled

    FEC performance
    Very high FEC performance are obtained for various block sizes and coding rates. The FEC behaviour of the BCH t=2 codes makes them particularly attractive for quasi-error free applications.

    Gaussian channel and QPSK modulation. Results given with 5 -5 iterations.


    Product Code (32,26) x (32,26) (32,21) x (32,21) (64,57) x (64,57) (64,51) x (64,51) (128,120) x (128,120) (128,113) x (128,113) (256,247) x (256,247) (256,239) x (256,239) Rate Eb/N0 @BER=10 0.660 2.9 dB 0.431 2.4 dB 0.793 3.2 dB 0.635 2.6 dB 0.879 3.8 dB 0.779 3.3 dB 0.931 4.5 dB 0.872 4.0 dB

    Eb/N0 @BER=10-8 3.6 dB N.A. 3.6 dB 2.9 dB 4.2 dB 3.4 dB 4.8 dB N.A.

    Block Diagram
    Input Interface
    DCK DBLK DEN D[D_WIDTH-1:0] DRDY

    Input Buffer #1 Input module Input Buffer #0 Decoder module

    Output Buffer

    Output module

    QCK QBLK QEN Q QRDY

    Output Interface

    Global Signals

    CK RSTB MSELECT

    Configuration module

    TC3000 Dedicated Configuration I/Os


    MDATA[7:0] MADDR[3:0] MCSn T_C[1:0] ITMAX[3:0] ITSTOP M_R[3:0] T_R[1:0] M_C[3:0]

    Implementation results
    Product Codes supported
    Hamming BCH t=2 Row max. length

    TC3011 TC3014 TC3022

    9 9 9

    Generic parameter setting Column Data bank max. length width swap 64 64 4 NO 64 64 4 NO 128 128 4 NO 64 64 4 NO

    MRDn MWRn

    Microcontroller Interface

    LE 2025 6926 8115 8932

    ESB 22 36 88 24

    Implementation results APEX20K Fmax Typical Bitrate device MHz @(64,57), 5 iterations 200 C7 82 8 Mbits/s 200 C7 72 25 Mbits/s 400 C7 67 23.5 Mbits/s 400 C7 79 14 Mbits/s

    This document contains preliminary information. Information is subject to change without notice. TC3000 is covered by several patents.

    You might also like