Fundamentals of Computer Systems

A Single Cycle MIPS Processor

Stephen A. Edwards and Martha A. Kim

Columbia University

Spring 2012
Illustrations Copyright 2007 Elsevier

Lets Build a Simple Processor

Supported instructions: R-type: and, or, addu, subu, slt Memory instructions: lw, sw Branch instructions: beq Version 2.0: I-type: addiu J-type: j

MIPS State Elements

This is the programmer-visible state in the ISA

CLK PC'
32

CLK PC
32 32

CLK WE3 RD1 RD2 WE

32 32 32

RD

5 32 5

A1 A2 A3 WD3

Instruction Memory

5 32

Register File

32

RD Data Memory WD

32

ALU Interface and Implementation

A N B N 3F
A
N

B
N

ALU
N Y

F2

F2 0 0 0 0 1 1 1 1

F1 0 0 1 1 0 0 1 1

F0 0 1 0 1 0 1 0 1

Func. A&B A|B A+B A&B A|B AB A < B (slt)

Cout
Zero Extend N N N N

[N-1]

+ S

2
N

F1:0

Datapath Elements for the lw Instruction

Fetch instruction from instruction memory: Send the PC to the instruction memorys address

CLK PC' PC A RD Instruction Memory Instr

CLK A1 A2 A3 WD3 WE3 RD1

CLK WE A RD2 Register File RD Data Memory WD

lw rt, offset(base) LW 100011 base rt offset

Datapath Elements for the lw Instruction

Read the base register

CLK
25:21

CLK PC A RD Instr A1 A2 A3 WD3 WE3 RD1

CLK WE A RD2 Register File RD Data Memory WD

PC'

Instruction Memory

lw rt, offset(base) LW 100011 base rt offset

Datapath Elements for the lw Instruction

Sign-extend the immediate

CLK PC' PC A RD Instr

25:21

CLK A1 WE3 RD1

CLK WE A RD Data Memory WD

Instruction Memory

A2 RD2 A3 Register WD3 File

15:0

SignImm Sign Extend

lw rt, offset(base) LW 100011 base rt offset

Datapath Elements for the lw Instruction

Add the base register and the sign-extended immediate to compute the data memory address
ALUControl2:0 CLK PC' PC A RD Instr
25:21

CLK A1 WE3 RD1 SrcA

010 Zero

CLK WE A RD Data Memory WD

ALU

ALUResult

Instruction Memory

A2 RD2 A3 Register WD3 File

SrcB

SignImm
15:0

Sign Extend

lw rt, offset(base) LW 100011 base rt offset

Datapath Elements for the lw Instruction

Read data from memory and write it back to rt in the register le
RegWrite CLK PC' PC A RD Instr
25:21

ALUControl2:0 010 SrcA Zero CLK WE A RD Data Memory WD ReadData

CLK A1 A2 A3 WD3

1 WE3

ALU

RD1 RD2

ALUResult

Instruction Memory

20:16

SrcB

Register File

SignImm
15:0

Sign Extend

lw rt, offset(base) LW 100011 base rt offset

Datapath Elements for the lw Instruction

Add four to the program counter to determine address of the the next instruction to execute
RegWrite CLK PC' PC A RD Instr
25:21

ALUControl2:0 010 SrcA Zero CLK WE A RD Data Memory WD ReadData

CLK A1 A2
20:16

1 WE3

ALU

RD1 RD2

ALUResult

Instruction Memory

SrcB

A3 WD3

Register File

PCPlus4 SignImm
15:0

Sign Extend

Result

lw rt, offset(base) LW 100011 base rt offset

Additional Elements for sw

Read rt from the register le and write it to data memory

RegWrite CLK PC' PC A RD Instr

25:21

ALUControl2:0 010 SrcA Zero

MemWrite CLK 1 WE A RD Data Memory WD ReadData

CLK A1 A2 A3 WD3

0 WE3

ALU

RD1 RD2

ALUResult

Instruction Memory

20:16 20:16

SrcB

Register File

WriteData

PCPlus4 SignImm
15:0

Sign Extend

Result

sw rt, offset(base) SW 101011 base rt offset

Additional Elements for R-Type Instructions

Read from rs and rt Write ALUResult to rd (instead of rt)

RegWrite CLK PC' PC A RD Instr

25:21

RegDst 1

ALUSrc ALUControl2:0 0 SrcA varies Zero

MemWrite CLK 0 WE A RD Data Memory WD

MemtoReg 0

CLK A1 A2

1 WE3

ALU

RD1 RD2

ALUResult

ReadData

0 1

Instruction Memory

20:16

0 SrcB 1

A3 Register WD3 File

20:16 15:11

WriteData

PCPlus4
15:0

WriteReg4:0 Sign Extend

0 1

SignImm

Result

addu rd, rs, rt SPECIAL 000000 rs rt rd ADDU 00000100001

Additional Elements for beq

Determine whether rs and rt are equal Calculate branch target address
PCSrc RegWrite 0 CLK PC A RD Instr
25:21

RegDst x

ALUSrc ALUControl2:0 Branch 0 110 1 SrcA Zero

MemWrite CLK 0 WE A RD Data Memory WD

MemtoReg x

CLK 0 1 PC'

ALU

A1

WE3

RD1

ALUResult

ReadData

Instruction Memory

20:16

0 1

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

beq rs, rt, offset BEQ rs rt 000100

offset

Add a controller to complete it

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite CLK 0 1 PC' PC A RD Instr
25:21

PCSrc

31:26 5:0

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

Op

rs

Funct

R-Type Instruction Encoding

addu rd, rs, rt SPECIAL 000000 SPECIAL 000000 SPECIAL 000000 SPECIAL 000000 SPECIAL 000000 rs rt rd ADDU 00000100001 SUBU 00000100011 AND 00000100100 OR 00000100101 SLT 00000101010

subu rd, rs, rt rs rt rd

and rd, rs, rt rs rt rd

or rd, rs, rt rs rt rd

slt rd, rs, rt rs rt rd

The ALU Decoder

Control Unit

MemtoReg MemWrite Branch ALUSrc RegDst RegWrite

Opcode5:0

Main Decoder

Part of the control unit responsible for implementing the opcode Funct eld.
ALU Op 00 -1 11111Funct 100001 100011 100100 100101 101010 ALU Ctrl. 010 110 010 110 000 001 111 ALU Function Add Subtract Add Subtract AND OR Slt

ALUOp1:0 ALU Decoder

Funct5:0

ALUControl 2:0

The Main Decoder

Inst. R-type lw sw beq OP 000000 100011 101011 000100 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp

31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite

PCSrc

CLK 0 1 PC' PC A RD Instr

25:21

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq OP 000000 100011 101011 000100 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 0 0 0 0 1-

31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op Funct ALUSrc RegDst RegWrite

0 PCSrc

0 0 1 PC'

CLK PC A RD Instr
25:21

CLK A1 A2

1 WE3 RD1 RD2 SrcA 0 0 SrcB 1 1 0 WriteReg4:0 1

CLK 001 Zero ALUResult A

0 WE 0 ReadData 0 1

ALU

Instruction Memory

20:16

A3 Register WD3 File

20:16 15:11

WriteData

RD Data Memory WD

PCPlus4
15:0

SignImm Sign Extend

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq OP 000000 100011 101011 000100 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 1 0 0 1 0 0 0 0 0 1 100

31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite

PCSrc

CLK 0 1 PC' PC A RD Instr

25:21

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq OP 000000 100011 101011 000100 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 100 00

31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite

PCSrc

CLK 0 1 PC' PC A RD Instr

25:21

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq OP 000000 100011 101011 000100 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 0 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 1 100 00 01

31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite

PCSrc

CLK 0 1 PC' PC A RD Instr

25:21

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq addiu OP 000000 100011 101011 000100 001001 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 0 0 1 0 1 0 0 1 0 0 0 1 Can we do this with our datapath?
MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite CLK 0 1 PC' PC A RD Instr
25:21

0 0 1 0

0 1 -

100 00 01

PCSrc

31:26 5:0

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

The Main Decoder

Inst. R-type lw sw beq addiu OP 000000 100011 101011 000100 001001 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp 1 1 0 0 1 1 0 0
MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite CLK 0 1 PC' PC A RD Instr
25:21

0 1 1 0 1

0 0 0 1 0

0 0 1 0 0

0 1 0

100 00 01 00

PCSrc

31:26 5:0

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16 15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

Additional Elements for the j Instruction

Inst. R-type lw sw beq addiu j OP 000000 100011 101011 000100 001001 000010 RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp Jump 1 1 0 0 1 0
Jump

1 0 0 MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op ALUSrc Funct RegDst RegWrite

0 1 1 0 1 -

0 0 0 1 0 -

0 0 1 0 0 0

0 1 0 -

100 00 01 00 --

0 0 0 0 0 1

PCSrc

31:26 5:0

CLK 0 1 0 1 PC' PC A RD Instr

25:21

CLK A1 WE3 RD1 SrcA Zero

CLK WE A RD Data Memory WD ReadData 0 Result 1

ALU

ALUResult

Instruction Memory

20:16

A2 RD2 A3 Register WD3 File 0 1

0 SrcB 1

WriteData

20:16

PCJump

15:11

PCPlus4
15:0

WriteReg4:0 Sign Extend

4
27:0 31:28

SignImm

<<2

25:0

<<2

PCBranch

Processor Performance

Seconds Program

Instructions Program

Clock Cycles Instruction

Seconds Clock Cycle

Seconds Program Instructions Program Clock Cycles Instruction Seconds Clock Cycle

How long you have to wait Number that must execute to complete the task CPI: Cycles per instruction The clock period (1/frequency)

The Critical Path Here: Load from Memory

MemtoReg Control MemWrite Unit Branch ALUControl 2:0 Op ALUSrc Funct RegDst RegWrite CLK 0 1 PC' PC A RD Instr
25:21

PCSrc

31:26 5:0

CLK A1 A2 A3

1 WE3 RD1 1 RD2 SrcA 0 SrcB 1 0 0 1

CLK 010 Zero ALUResult A

0 WE 1 ReadData 0 1

ALU

Instruction Memory

20:16

Register WD3 File

20:16 15:11

WriteData

RD Data Memory WD

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

Instruction Memory to Register File to ALU to Data Memory to Register File

The Critical Path Dictates the Clock Period

Element Register clk-to-Q Register setup Multiplexer ALU Memory Read Register le read Register le setup Delay tpcq-PC 30 ps tsetup 20 tmux 25 tALU 200 tmem 250 tRFread 150 tRFsetup 20
31:26 5:0

MemtoReg Control MemWrite Unit Branch ALUControl 2:0 Op ALUSrc Funct RegDst RegWrite

PCSrc

CLK 0 1 PC' PC A RD Instr

25:21

CLK A1 A2 A3 WD3
20:16 15:11

1 WE3

CLK RD1 RD2 SrcA 1 0 SrcB 1 0 0 1 010 Zero ALUResult A

0 WE ReadData 0 1

ALU

Instruction Memory

20:16

Register File

WriteData

RD Data Memory WD

PCPlus4
15:0

WriteReg4:0 Sign Extend

SignImm

<<2

PCBranch

Result

TC

= = = =

tpcq-PC + tmem-I + tRFread + tALU + tmem-D + tmux + tRFsetup (30 + 250 + 150 + 200 + 250 + 25 + 20) ps 925 ps 1.08 GHz

Execution Time for Our Single-Cycle Processor

For a 100 billion-instruction task on our single-cycle processor with a 925 ps clock period,
Seconds Program

Instructions Program

Clock Cycles Instruction

Seconds Clock Cycle

= 100 109 = 92.5 seconds

925 ps