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Two Steps:: Instruction Cycle y

The document describes the instruction cycle and interrupt cycle of a processor. The instruction cycle has two steps - fetch and execute. In fetch, the program counter holds the address of the next instruction, which is fetched from memory and loaded into the instruction register. In execute, the processor performs actions like data transfer, arithmetic, and flow control. Interrupts can suspend program execution to handle events like I/O, timers, and failures. The processor saves context, handles the interrupt, restores context, and continues the interrupted program. Interrupts can be prioritized, disabled, or nested.

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Mahi Nur
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24 views

Two Steps:: Instruction Cycle y

The document describes the instruction cycle and interrupt cycle of a processor. The instruction cycle has two steps - fetch and execute. In fetch, the program counter holds the address of the next instruction, which is fetched from memory and loaded into the instruction register. In execute, the processor performs actions like data transfer, arithmetic, and flow control. Interrupts can suspend program execution to handle events like I/O, timers, and failures. The processor saves context, handles the interrupt, restores context, and continues the interrupted program. Interrupts can be prioritized, disabled, or nested.

Uploaded by

Mahi Nur
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Instruction Cycle y Two steps:

Fetch F t h Execute

Fetch Cycle y Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory l location pointed to b PC i i d by C Increment PC
Unless told otherwise

Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

Execute Cycle y Processor-memory


data t d t transfer b t f between CPU and main memory d i

Processor I/O
Data transfer between CPU and I/O module

Data processing p g
Some arithmetic or logical operation on data

Control
Alteration of sequence of operations e g jump e.g.

Combination of above

Example of Program Execution p g

Instruction Cycle State Diagram y g

Interrupts p Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
e.g. overflow, division by zero

Timer
Generated by internal processor timer y p Used in pre-emptive multi-tasking

I/O
from I/O controller

Hardware failure
e.g. memory parity error

Program Flow Control g

Interrupt Cycle p y Added to instruction cycle Processor checks for interrupt h k f


Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:


Suspend execution of current program Save context Save Set PC to start address of interrupt handler routine Process interrupt Restore Restore context and continue interrupted program

Transfer of Control via Interrupts p

Instruction Cycle with Interrupts y p

Program Timing Short I/O Wait

Program Timing Long I/O Wait g

Instruction Cycle (with Interrupts) State Diagram g

Multiple Interrupts p p Disable interrupts


Processor will ignore further interrupts whilst P ill i f th i t t hil t processing one interrupt Interrupts remain pending and are checked Interrupts after first interrupt has been processed Interrupts handled in sequence as they occur

Define priorities
Low priority i t L i it interrupts can be interrupted by t b i t t db higher priority interrupts When higher priority interrupt has been When processed, processor returns to previous interrupt

Multiple Interrupts - Sequential p p q

Multiple Interrupts Nested p p

Time Sequence of Multiple Interrupts q p p

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