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Verification of and Gate

The document contains descriptions of six logic gate exercises: AND, OR, NOT, NAND, XOR, and XNOR. For each exercise, it defines the port inputs and outputs for the gate and provides the VHDL code to implement the logic function for that gate.

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siddhant5031
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24 views

Verification of and Gate

The document contains descriptions of six logic gate exercises: AND, OR, NOT, NAND, XOR, and XNOR. For each exercise, it defines the port inputs and outputs for the gate and provides the VHDL code to implement the logic function for that gate.

Uploaded by

siddhant5031
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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LAB EXRCISE#1

VERIFICATION OF AND GATE


library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity and2 is
port(a,b:in bit;
y:out bit);
end and2;
--------------------------------------------------------architecture and2 of and2 is
begin
y<= a and b;
end and2;

LAB EXRCISE#2

VERIFICATION OF OR GATE
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity or2 is
port(a,b:in bit;
y:out bit);
end or2;
--------------------------------------------------------architecture or2 of or2 is
begin
y<= a or2 b;
end or2;

LAB EXRCISE#3

VERIFICATION OF NOT GATE


library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity not1 is
port(a:in bit;
y:out bit);
end not1;
--------------------------------------------------------architecture not1 of not1 is
begin
y<= not a;
end not1;

LAB EXRCISE#4

VERIFICATION OF NAND GATE


library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity nand2 is
port(a,b:in bit;
y:out bit);
end nand2;
--------------------------------------------------------architecture nand2 of nand2 is
begin
y<= a nand b;
end nand2;

LAB EXRCISE#5

VERIFICATION OF EX-OR GATE


library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity exor2 is
port(a,b:in bit;
y:out bit);
end exor2;
--------------------------------------------------------architecture exor2 of exor2 is
begin
y<=((not a) and b)or (a and (not b));
--y<=((not a)and b)or(a and(not b)));
end exor2;
----------------------------------------------------------------------

LAB EXRCISE#6

VERIFICATION OF EX-NOR GATE


library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------entity exor2 is
port(a,b:in bit;
y:out bit);
end exor2;
--------------------------------------------------------architecture exor2 of exor2 is
begin
y<=((not a) and b)or (a and (not b));
--y<=((not a)and b)or(a and(not b)));
end exor2;
----------------------------------------------------------------------

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