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Hardware Based Speculation

Hardware based speculation uses dynamic branch prediction to speculatively execute instructions before control dependencies are resolved. It implements a modified Tomasulo algorithm to separate instruction completion from committing results to processor state. Instructions execute out-of-order but commit in-order by writing results to a reorder buffer first before committing to registers or memory. There are four stages: issue, execute, write results, and commit. If a branch is mispredicted, the reorder buffer and reservation stations are flushed.

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99 views2 pages

Hardware Based Speculation

Hardware based speculation uses dynamic branch prediction to speculatively execute instructions before control dependencies are resolved. It implements a modified Tomasulo algorithm to separate instruction completion from committing results to processor state. Instructions execute out-of-order but commit in-order by writing results to a reorder buffer first before committing to registers or memory. There are four stages: issue, execute, write results, and commit. If a branch is mispredicted, the reorder buffer and reservation stations are flushed.

Uploaded by

Christina Deepthy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Hardware Based Speculation

Hardware based speculation combines three key ideas: Dynamic branch prediction to choose which instructions to execute Speculation to allow execution of instructions before control dependencies are resolved Dynamic scheduling to deal with different combinations of basic blocks. The most common implementation is based on a modification of the Tomasulo algorithm. The idea is to separate when an instruction writes its results from when those results are "committed" to processor state. Instructions can execute out of order, but must commit in order. Results are stored in the reorder buffer between instruction completion and commit. Instructions are tracked by the reorder buffer. Four stages of instruction execution: Issue Issue the instruction to a reservation station and a slot in the reorder buffer. (the reorder buffer index can be used as the tag for the result). Source operand values or tags are retrieved from the register file. Execute Monitor the CDB until all operands are available, and issue the operation to the functional unit. Write Results Broadcast the result with its tag on the CDB. Results are stored in the reorder buffer (and any coresponding tagged operands in the reservation stations) - NOT in the register file. Commit When an instruction reaches the head of the reorder buffer (a queue - keeping instruction completion in order), with it's result value, the value is written to the register file (or memory for a store) and removed from the reorder buffer, thus committing the instruction to processor state. If the instruction is a branch, incorrectly predicted, the reorder buffer is flushed, as well as corresponding outstanding reservation station entries.

Advantages of hardware speculation


Memory reference disambiguation can only be done at run time, especially when pointers are used. Hardware speculation is better because dynamic branch prediction can be better that static, especially in integer programs Maintains precise exceptions, even with speculation No "fix-up" code is required Legacy code

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