Logic Design

A Review

Boolean Algebra
y Two Values: zero and one y Three Basic Functions: And, Or, Not y Any Boolean Function Can be

Constructed from These Three

A nd 0 1 0 0 0 1 0 1 Or 0 1 0 0 1 1 1 1 N ot 0 1

1 0

Algebraic Laws
Classification Identity Dominance Commutativity Associativity Distributive Demorgans Laws Law a1=1a=a a+0=0+a=a a0=0a=0 1+a=a+1=1 a+b=b+a ab=ba a(bc)=(ab)c a+(b+c)=(a+b)+c a(b+c)=ab+ac a+bc=(a+b)(a+c) ( a + b ) = a b ( ab ) = a + b

Boolean Expressions
y Addition represents OR y Multiplication represents AND y Not is represented by a prime a or an

overbar a y Examples: y s = abc + abc + abc + abc y q = ab + bc + ac + abc

Superfluous Terms
y The following Two Equations Represent

The Same Function. q = ab + bc + ac + abc q = ab + bc + ac

a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c q 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1

Prime Implicants
y A Prime Implicant is a Product of

Variables or Their Complements, eg. abcd y If a Prime Implicant has the Value 1, then the Function has the Value 1 y A Minimal Equation is a Sum of Prime Implicants

Minimization and Minterms

y Minimization Reduces the Size and

Number of Prime Implicants y A MinTerm is a Prime Implicant with the Maximum Number of Variables y For a 3-input Function abc is a MinTerm, while ab is not. y Prime Implicants can be Combined to Eliminate Variables, abc+abc = ab

Minimization with Maps

y A Karnaugh Map

^ ^
01 0 0 11 0 0 10 1 0

^1

00 0 1 1

Procedure
y Select Regions Containing All 1s y Regions should be as Large as Possible y Regions must contain 2k cells y Regions should overlap as little as

possible y The complete set of regions must contain all 1s in the map

Procedure 2
y Top and Bottom of Map are Contiguous y Left and Right of Map are Contiguous y Regions represent Prime Implicants y Use Variable name guides to construct

equation
Completely inside the region of a variable means prime implicant contains variable Completely outside the region of a variable means prime implicant contains negation

Applied to Previous Map C B

^ ^
01 0 0 11 0 0 10 1 0

^1

00 0 1 1

q=cb+ca

A 4-Variable Karnaugh Map D C

00 00 0 01 10 0
0 11

^ ^
01 0 1
1

^
A

11 0 1
0

10 0 1
1

First Minimization D
00 00 0 01 10 0
0 11

^ ^
01 0 1
1

^
A

11 0 1
0

10 0 1
1

Second Minimization D
00 00 0 01 10 0
0 11

^ ^
01 0 1
1

^
A

11 0 1
0

10 0 1
1

Minimal Forms for Previous Slides:

y

ab d + bc d + a bc + acd
ac d + a bd + bcd + ab c

y Moral: A Boolean Function May Have

Several Different Minimal Forms y Karnaugh Maps are Ineffective for Functions with More than Six Inputs.

Quine McClusky Minimization

y Amenable to Machine Implementation y Applicable to Circuits with an Arbitrary

Number of Inputs y Effective Procedure for Finding Prime Implicants, but y Can Require an Exponential Amount of Time for Some Circuits

Quine-McClusky Procedure
y Start with The Function Truth Table y Extract All Input Combinations that

Produce a TRUE Output (MinTerms) y Group All MinTerms by The Number of Ones They Contain y Combine Minterms from Adjacent Groups

More Quine-McClusky
y Two Min-Terms Combine If They Differ

by Only One Bit y The Combined MinTerm has an x in the Differing Position y Create New Groups From Combined Min-Terms y Each Member of A New Group Must Have the Same Number of 1s and xs

Yet More Quine-McClusky

y Each Member of A Group Must Have

xs in The Same Position. y Combine Members of the New Groups To Create More New Groups y Combined Terms Must Differ By One Bit, and Have xs in the Same Positions y Combine as Much as Possible y Select Prime Implicants to Cover All Ones in the Function

Quine-McClusky Example 1
Numbers in Parentheses are Truth-Table Positions.

0011(3) 1100(12) 0111(7) 1011(11) 1101(13) 1110(14) 1111(15)

Quine-McClusky Example 2
New Groups After Combining MinTerms

0x11(3,7) 1x11(11,15) x011(3,11) x111(7,15)

110x(12,13) 111x(14,15) 11x0(12,14) 11x1(13,15)

Quine-McClusky Example 3
The Final Two Groups Note That These Two Elements Cover All Truth-Table Positions

xx11(3,7,11,15) 11xx(12,13,14,15)

Quine-McClusky Example 4
y Each Group Element Represents a Prime

Implicant y It is Necessary to Select Group Elements to Cover All Truth-Table Positions. y In This Case, ab+cd is the Minimal Formula. y In General, Selecting a Minimal Number of Prime Implicants is NP-Complete

Basic Logic Symbols

And

Or

Not

The Exclusive Or Function

Xor 0 1

0 0 1

1 1 0

A Simple Logic Diagram

Signal Flow

Additional Logic Symbols

Nand

Nor

Buffer Xnor

Sequential Logic
y Contains Memory Elements y Memory is Provided by Feedback y Circuit diagrams generally have

implicit or explicit cycles y Two Styles: Synchronous and Asynchronous

An RS Flip-Flop

RS Characteristics
y If S=0 and R=1, Q is set to 1, and Q is

reset to 0 y If R=0 and S=1, Q is reset to 0, and Q is set to 1 y If S=1 and R=1, Q and Q maintain their previous state. y If S=0 and R=0, a transision to S=1, R=1 will cause oscillation.

Instability
y RS flip-flops can become unstable if

both R and S are set to zero. y All Sequential elements are fundamentally unstable under certain conditions
Invalid Transisions Transisions too close together Transisions at the wrong time

D Flip-Flops

D-Flip Flop Characteristics

y Avoids the instability of the RS flip-flop y Retains its last input value y Formally known as a Delay flip-flop y May become unstable if transisions are

too close together y Is generally implemented as a special circuit, not as pictured here.

A Clocked D Flip-Flop

Clocked D-Flip Flop Characteristics

y Synchronizes transisions with a clock y Input should remain stable while clock

is active y Transision at the wrong time can cause instability

Changes while clock is active Changes simultaneous with clock

Flip-Flop Symbols

D Clk

T Clk

Flip-Flop Symbols Contain Implicit Feedback Loops

A CMOS Flip-Flop
Clk Q D Q Clk

CMOS Logic Elements

y CMOS = Complementary MOS y CMOS Elements Often Require 2 Clocks

or 2 Controls y Clocks or Controls must be Complements of One another y Clock-Skew (Non-Simultaneous changes in both clocks) can cause problems

An Asynchronous Sequential Circuit

Combinational Logic Q Q

D
Clk

Asynchronous Circuits
y Combinational Logic is used:

To Compute New States To Compute Outputs

y State is maintained in Asynchronous

Circuit Elements y Care must be used to avoid oscillations

A Synchronous Sequential Circuit

Combinational Logic D
Clk

Q Q

Synchronous Circuits
y Combinational Logic is used to:

Compute New States Compute Outputs

y State is maintained in Synchronous

Flip-Flops y State Changes can be made only when clock changes y Combinational Logic Must be Stable when Clock is Active

Register Symbol
Input 16

Load Clock 16

Output

Register Issues
y Generally A Collection of D Flip-Flops y Can be Synchronous or Asynchronous y Default is Assumption is

Synchronous y May have internal wiring to:

Perform Shifts Set/Clear All-Zero Status Flag

Tristate Elements
y Three States:

Zero (Output is grounded) One (Output connected to Power Terminal) High-Impedance (Output Not Connected to Either Power Or Ground)
y Can be Used to Construct Cheap

Multiplexors

CMOS Tri-state Buffers

Non-Inverting

Inverting

Tri-State Buffer Issues

y The Gate Amplifies its Signal y May be Inverting or Non-Inverting y Often used to Construct Multiplexors

Using Wired-Or Connections

More Tri-State Issues

y In a Wired-Or Connection, Only One

Buffer can be in Non-Tristate State y Violating This Rule Can Destroy The Circuit Due a Power/Ground Short
1 1

DANGER!
0

The CMOS Transmission Gate

Transmission Gate Issues

y Similar to Tristate Buffer y Has No Amplification y Number of Consecutive Transmission

Gates is Limited y Similar Problems With Wired-Or Connections

Logic Design
A Review

Boolean Algebra
Two Values: zero and one y Three Basic Functions: And, Or, Not y Any Boolean Function Can be Constructed from These Three
y

A nd 0 1

0 0 0

1 0 1

Or 0 1

0 0 1

1 1 1

N ot 0 1

1 0

Algebraic Laws
Classification Identity Dominance Commutativity Associativity Distributive Demorgans Laws Law a1=1a=a a+0=0+a=a a0=0a=0 1+a=a+1=1 a+b=b+a ab=ba a(bc)=(ab)c a+(b+c)=(a+b)+c a(b+c)=ab+ac a+bc=(a+b)(a+c) ( a + b ) = a b ( ab ) = a + b

Boolean Expressions
Addition represents OR y Multiplication represents AND y Not is represented by a prime a or an overbar a y Examples: y s = abc + abc + abc + abc y q = ab + bc + ac + abc
y

Superfluous Terms
y

The following Two Equations Represent The Same Function. q = ab + bc + ac + abc q = ab + bc + ac

a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c q 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1

Prime Implicants
A Prime Implicant is a Product of Variables or Their Complements, eg. abcd y If a Prime Implicant has the Value 1, then the Function has the Value 1 y A Minimal Equation is a Sum of Prime Implicants
y

Minimization and Minterms

Minimization Reduces the Size and Number of Prime Implicants y A MinTerm is a Prime Implicant with the Maximum Number of Variables y For a 3-input Function abc is a MinTerm, while ab is not. y Prime Implicants can be Combined to Eliminate Variables, abc+abc = ab
y

Minimization with Maps

y

A Karnaugh Map

^ ^
01 0 0 11 0 0 10 1 0

^1

00 0 1 1

Procedure
Select Regions Containing All 1s y Regions should be as Large as Possible y Regions must contain 2k cells y Regions should overlap as little as possible y The complete set of regions must contain all 1s in the map
y

Procedure 2
Top and Bottom of Map are Contiguous y Left and Right of Map are Contiguous y Regions represent Prime Implicants y Use Variable name guides to construct equation
y

Completely inside the region of a variable means prime implicant contains variable Completely outside the region of a variable means prime implicant contains negation

Applied to Previous Map C B

^ ^
01 0 0 11 0 0 10 1 0

^1

00 0 1 1

q=cb+ca

A 4-Variable Karnaugh Map D C

00 00 0 01 10 0 0 0 11 01 0 1 1 1 11 0 1 0 1 10 0 1 1 1

^ ^

^
A

First Minimization D
00 00 0 01 10 0 0 0 11 01 0 1 1 1

^ ^
11 0 1 0 1 10 0 1 1 1

^
A

Second Minimization D
00 00 0 01 10 0 0 0 11 01 0 1 1 1

^ ^
11 0 1 0 1 10 0 1 1 1

^
A

Minimal Forms for Previous Slides:

y

ab d + bc d + a bc + acd
ac d + a bd + bcd + ab c

Moral: A Boolean Function May Have Several Different Minimal Forms y Karnaugh Maps are Ineffective for Functions with More than Six Inputs.
y

Quine McClusky Minimization

Amenable to Machine Implementation y Applicable to Circuits with an Arbitrary Number of Inputs y Effective Procedure for Finding Prime Implicants, but y Can Require an Exponential Amount of Time for Some Circuits
y

Quine-McClusky Procedure
Start with The Function Truth Table y Extract All Input Combinations that Produce a TRUE Output (MinTerms) y Group All MinTerms by The Number of Ones They Contain y Combine Minterms from Adjacent Groups
y

More Quine-McClusky
Two Min-Terms Combine If They Differ by Only One Bit y The Combined MinTerm has an x in the Differing Position y Create New Groups From Combined Min-Terms y Each Member of A New Group Must Have the Same Number of 1s and xs
y

Yet More Quine-McClusky

Each Member of A Group Must Have xs in The Same Position. y Combine Members of the New Groups To Create More New Groups y Combined Terms Must Differ By One Bit, and Have xs in the Same Positions y Combine as Much as Possible y Select Prime Implicants to Cover All Ones in the Function
y

Quine-McClusky Example 1
Numbers in Parentheses are Truth-Table Positions.

0011(3) 1100(12) 0111(7) 1011(11) 1101(13) 1110(14) 1111(15)

Quine-McClusky Example 2
New Groups After Combining MinTerms

0x11(3,7) 1x11(11,15) x011(3,11) x111(7,15)

110x(12,13) 111x(14,15) 11x0(12,14) 11x1(13,15)

Quine-McClusky Example 3
The Final Two Groups Note That These Two Elements Cover All Truth-Table Positions

xx11(3,7,11,15) 11xx(12,13,14,15)

Quine-McClusky Example 4
Each Group Element Represents a Prime Implicant y It is Necessary to Select Group Elements to Cover All Truth-Table Positions. y In This Case, ab+cd is the Minimal Formula. y In General, Selecting a Minimal Number of Prime Implicants is NP-Complete
y

Basic Logic Symbols

And

Or

Not

The Exclusive Or Function

Xor 0 1

0 0 1

1 1 0

A Simple Logic Diagram

Signal Flow

Additional Logic Symbols

Nand

Nor

Buffer Xnor

Sequential Logic
Contains Memory Elements y Memory is Provided by Feedback y Circuit diagrams generally have implicit or explicit cycles y Two Styles: Synchronous and Asynchronous
y

An RS Flip-Flop

RS Characteristics
If S=0 and R=1, Q is set to 1, and Q is reset to 0 y If R=0 and S=1, Q is reset to 0, and Q is set to 1 y If S=1 and R=1, Q and Q maintain their previous state. y If S=0 and R=0, a transision to S=1, R=1 will cause oscillation.
y

Instability
RS flip-flops can become unstable if both R and S are set to zero. y All Sequential elements are fundamentally unstable under certain conditions
y

Invalid Transisions Transisions too close together Transisions at the wrong time

D Flip-Flops

D-Flip Flop Characteristics

Avoids the instability of the RS flip-flop y Retains its last input value y Formally known as a Delay flip-flop y May become unstable if transisions are too close together y Is generally implemented as a special circuit, not as pictured here.
y

A Clocked D Flip-Flop

Clocked D-Flip Flop Characteristics

Synchronizes transisions with a clock y Input should remain stable while clock is active y Transision at the wrong time can cause instability
y

Changes while clock is active Changes simultaneous with clock

Flip-Flop Symbols

D Clk

T Clk

Flip-Flop Symbols Contain Implicit Feedback Loops

A CMOS Flip-Flop
Clk Q D Q Clk

CMOS Logic Elements

CMOS = Complementary MOS y CMOS Elements Often Require 2 Clocks or 2 Controls y Clocks or Controls must be Complements of One another y Clock-Skew (Non-Simultaneous changes in both clocks) can cause problems
y

An Asynchronous Sequential Circuit

Combinational Logic Q Q

D
Clk

Asynchronous Circuits
y

Combinational Logic is used:

To Compute New States To Compute Outputs

State is maintained in Asynchronous Circuit Elements y Care must be used to avoid oscillations
y

A Synchronous Sequential Circuit

Combinational Logic D
Clk

Q Q

Synchronous Circuits
y

Combinational Logic is used to:

Compute New States Compute Outputs

State is maintained in Synchronous Flip-Flops y State Changes can be made only when clock changes y Combinational Logic Must be Stable when Clock is Active
y

Register Symbol
Input 16

Load Clock 16

Output

Register Issues
Generally A Collection of D Flip-Flops y Can be Synchronous or Asynchronous y Default is Assumption is Synchronous y May have internal wiring to:
y

Perform Shifts Set/Clear All-Zero Status Flag

Tristate Elements
y

Three States:
Zero (Output is grounded) One (Output connected to Power Terminal) High-Impedance (Output Not Connected to Either Power Or Ground)

Can be Used to Construct Cheap Multiplexors

CMOS Tri-state Buffers

Non-Inverting

Inverting

Tri-State Buffer Issues

The Gate Amplifies its Signal y May be Inverting or Non-Inverting y Often used to Construct Multiplexors Using Wired-Or Connections
y

More Tri-State Issues

In a Wired-Or Connection, Only One Buffer can be in Non-Tristate State y Violating This Rule Can Destroy The Circuit Due a Power/Ground Short
y
1 1

DANGER!
0

The CMOS Transmission Gate

Transmission Gate Issues

Similar to Tristate Buffer y Has No Amplification y Number of Consecutive Transmission Gates is Limited y Similar Problems With Wired-Or Connections
y