VCS
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Verilog Design Code
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Verilog Test bench
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File Directory
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Analyzing the file
vlogan decoder.v tb.v
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File Directory after analyze
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Elaborating the design
vcs debug_all decoder_2to4 Test_decoder_2to4
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File Directory after elaborate
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Simulating in batch mode
./simv
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File Directory after simulation
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Generation of Log File
vcs debug_all decoder_2to4 Test_decoder_2to4 -l logfile.log
File Directory structure
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Suppressing the copyright
vcs nc decoder_2to4 Test_decoder_2to4
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Elaborating in quit mode
vcs q decoder_2to4 Test_decoder_2to4
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Elaborating in Verbose mode
vcs v decoder_2to4 Test_decoder_2to4
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Compile and simulate in a single command
vcs R decoder_2to4 Test_decoder_2to4
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Generating a VCD File
Add $dumpfile(File.vcd); $dumpvars ; system task in the test bench
vlogan decoder.v tb.v vcs debug_all decoder_2to4 Test_decoder_2to4 ./simv
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File Directory Structure
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Open the DVE
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DVE Window
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Opening the vcd file
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Dve when loaded
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Viewing the waveforms
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waveforms
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Interactive mode
vlogan decoder.v tb.v vcs debug_all decoder_2to4 Test_decoder_2to4 ./simv -gui
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dve
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Simulation time insertion
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Adding to waves
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See schematic in dve
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schematic
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See path schematic
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Path schematic
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Generation of VPD file
Add $vcdplusfile(hahaFile.vpd); $vcdpluson; system task in the test bench
vlogan decoder.v tb.v vcs debug_pp decoder_2to4 Test_decoder_2to4 ./simv dve& Load the vpd file
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Seer Akademi Pvt. Ltd., 2011
Seer Akademi Pvt. Ltd., 2011
Steps to generate coverage reports
vlogan decoder.v tb.v vcs debug_all decoder_2to4 Test_decoder_2to4 -Mupdate -cm line+tgl+fsm+cond+branch ./simv -cm line+tgl+fsm+cond+branch dve -cov
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Coverage reports
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Coverage reports
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Coverage reports
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Coverage reports
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THANK YOU
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