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Verilog Tutorial Mirza A Baig CSE Department YUC Yanbu Industrial City, Saudi Arabia

This document contains Verilog code examples for various digital logic components including multiplexers, flip-flops, counters, full adders, shift registers, ALUs, and state machines. It also includes examples of module instantiation, always blocks, case statements, parameter definitions, and testbenches.

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Mirza Baig
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105 views

Verilog Tutorial Mirza A Baig CSE Department YUC Yanbu Industrial City, Saudi Arabia

This document contains Verilog code examples for various digital logic components including multiplexers, flip-flops, counters, full adders, shift registers, ALUs, and state machines. It also includes examples of module instantiation, always blocks, case statements, parameter definitions, and testbenches.

Uploaded by

Mirza Baig
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CSE 321

Verilog Tutorial Mirza A Baig CSE Department YUC Yanbu Industrial City, Saudi Arabia

Register Transfer Level Design with Verilog


Primitive instantiations

module MultiplexerA (input a, b, s, output w); wire a_sel, b_sel, s_bar; not U1 (s_bar, s); and U2 (a_sel, a, s_bar); and U3 (b_sel, b, s); or U4 (w, a_sel, b_sel); endmodule

Module Instantiation
Assign statements( Behavioral)
module MultiplexerB (input a, b, s, output w); assign w = (a & ~s) | (b & s); endmodule

Conditional expression
module MultiplexerC (input a, b, s, output w); assign w = s ? b : a; endmodule

Procedural Statement
Procedural blocks
module MultiplexerD (input a, b, s, output w); reg w; always @ (a, b, s) begin if (s) w = b; else w = a; end endmodule

Multiplexer Using ANDOR


Module instantiations
module ANDOR (input i1, i2, i3, i4, output y); assign y = (i1 & i2) | (i3 & i4); endmodule // module MultiplexerE (input a, b, s, output w); wire s_bar; not U1 (s_bar, s); ANDOR U2 (a, s_bar, s, b, w); endmodule

Octal 2-to-1 Mux


`timescale directive: This directive defines
The modules time unit `timescale 1ns/100ps module Mux8 (input sel, input [7:0] data1, data0, output [7:0] bus1); assign #6 bus1 = sel ? data1 : data0; endmodule

Flip-flop
Flip-Flop Description `timescale 1ns/100ps module Flop (reset, din, clk, qout); input reset, din, clk; output qout; reg qout; always @ (negedge clk) begin if (reset) qout <= #8 1b0; else qout <= #8 din; end endmodule

Counter
Verilog code for a 4-bit modulo-16 counter. The counter has a synchronous reset and a 4-bit count output. `timescale 1ns/100ps module Counter4 (input reset, clk, output [3:0] count); reg [3:0] count; always @ (negedge clk) begin if (reset) count <= #3 4b00_00; else count <= #5 count + 1; End endmodule

Full adder.
Full adder Verilog Code `timescale 1ns/100ps module full adder (input a, b, output sum, cout); assign #5 sum = a ^ b ^ cin; assign #3 cout = (a & b)|(a & cin)|(b & cin); endmodule

Shift-register
An 8-bit Universal Shift Register `timescale 1ns/100ps module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, input [1:0] m, output reg [7:0] ParOut); always @ (negedge clk) begin case (m) 0: ParOut <= ParOut; 1: ParOut <= {sl, ParOut [7:1]}; 2: ParOut <= {ParOut [6:0], sr}; 3: ParOut <= ParIn; default: ParOut <= 8bX; endcase end endmodule

ALU
An 8-bit ALU `timescale 1ns/100ps module ALU8 (input [7:0] left, right, input [1:0] mode, output reg [7:0] ALUout); always @(left, right, mode) begin case (mode) 0: ALUout = left + right; 1: ALUout = left - right; 2: ALUout = left & right; 3: ALUout = left | right; default: ALUout = 8bX; endcase end endmodule

Interconnections
Partial Verilog code of Fig. 2.19
ALU8 U1 ( .left(Inbus), .right(ABinput), .mode(function), .ALUout(Outbus) ); Mux8 U2 ( .sel(select_source), .data1(Aside), .data0(Bside) );

Ordered Port Connection


ALU8 U1 ( Inbus, ABinput, function, Outbus ); Mux8 U2 ( select_source, Aside, Bside );

State Machines
Sequence Detector (State Machine) `timescale 1ns/100ps module Detector110 (input a, clk, reset, output w); parameter [1:0] s0=2b00, s1=2b01, s2=2b10, s3=2b11; reg [1:0] current; always @ (posedge clk) begin if (reset) current = s0; else case (current) s0: if (a) current <= s1; else current <= s0; s1: if (a) current <= s2; else current <= s0; s2: if (a) current <= s2; else current <= s3; s3: if (a) current <= s1; else current <= s0; endcase end assign w = (current == s3) ? 1: 0; endmodule

Testbenches
Testbench for Detector110 `timescale 1ns/100ps module Detector110Tester; reg aa, clock, rst; wire ww; Detector110 UUT (aa, clock, rst, ww); initial begin aa = 0; clock = 0; rst = 1; end initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa; initial begin #31 rst = 1; #23 rst = 0; end always @ (ww) if (ww == 1) $display (A 1 was detected on w at time = %t, $time); endmodule

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